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git01.mediatek.com / filogic / uboot / a1aae6343709fa277e19c49af0d1decda2edeeb8 / . / include / configs / theadorable.h
blob: 0e5bd0dbbf79464e6c03f6498d5b4e4e7e750231 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]2/*
3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]4 */
5
6#ifndef _CONFIG_THEADORABLE_H
7#define _CONFIG_THEADORABLE_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]12
13/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]18#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
19
20/*
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]21 * The debugging version enables USB support via defconfig.
22 * This version should also enable all other non-production
23 * interfaces / features.
24 */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]25
26/* I2C */
27#define CONFIG_SYS_I2C
28#define CONFIG_SYS_I2C_MVTWSI
29#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roese07b5e042016-04-08 15:58:29 +0200[diff] [blame]30#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]31#define CONFIG_SYS_I2C_SLAVE 0x0
32#define CONFIG_SYS_I2C_SPEED 100000
33
34/* USB/EHCI configuration */
35#define CONFIG_EHCI_IS_TDI
36#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
37
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]38/* Environment in SPI NOR flash */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]39#define CONFIG_ENV_OVERWRITE
40
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]41#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
42
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]43/* Keep device tree and initrd in lower memory so the kernel can access them */
44#define CONFIG_EXTRA_ENV_SETTINGS \
45 "fdt_high=0x10000000\0" \
46 "initrd_high=0x10000000\0"
47
48/* SATA support */
49#define CONFIG_SYS_SATA_MAX_DEVICE 1
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]50#define CONFIG_LBA48
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]51
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]52/* Enable LCD and reserve 512KB from top of memory*/
53#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
54
Stefan Roesed64c1132019-01-30 08:54:13 +0100[diff] [blame]55#define CONFIG_BMP_16BPP
56#define CONFIG_BMP_24BPP
57#define CONFIG_BMP_32BPP
58
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]59/* FPGA programming support */
Stefan Roesef0547582016-02-12 14:24:07 +0100[diff] [blame]60#define CONFIG_FPGA_STRATIX_V
61
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]62/*
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]63 * Bootcounter
64 */
Stefan Roese1a4e9802016-04-07 10:48:14 +0200[diff] [blame]65/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
66#define BOOTCOUNT_ADDR 0x1000
67
68/*
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]69 * mv-common.h should be defined after CMD configs since it used them
70 * to enable certain macros
71 */
72#include "mv-common.h"
73
74/*
75 * Memory layout while starting into the bin_hdr via the
76 * BootROM:
77 *
78 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
79 * 0x4000.4030 bin_hdr start address
80 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
81 * 0x4007.fffc BootROM stack top
82 *
83 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
84 * L2 cache thus cannot be used.
85 */
86
87/* SPL */
88/* Defines for SPL */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]89#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
90
91#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
92#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
93
94#ifdef CONFIG_SPL_BUILD
95#define CONFIG_SYS_MALLOC_SIMPLE
96#endif
97
98#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
99#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
100
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]101/* SPL related SPI defines */
Stefan Roese459e0642016-01-20 08:13:29 +0100[diff] [blame]102#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
103
104/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
105#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
106
107#endif /* _CONFIG_THEADORABLE_H */