blob: c475c3f50ab3bbbe18be66ef7e8d44d8ad4e7271 [file] [log] [blame]
Chris Brandt1f3b6672017-08-23 14:53:59 -05001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017 Renesas Electronics
4 * Copyright (C) Chris Brandt
5 */
6
Simon Glassafb02152019-12-28 10:45:01 -07007#include <cpu_func.h>
Marek Vasutdc9595b2024-01-21 18:31:23 +01008#include <errno.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/global_data.h>
Chris Brandt1f3b6672017-08-23 14:53:59 -050011#include <asm/io.h>
12#include <asm/arch/sys_proto.h>
Marek Vasutdc9595b2024-01-21 18:31:23 +010013#include <asm/u-boot.h>
Chris Brandt1f3b6672017-08-23 14:53:59 -050014
15#define RZA1_WDT_BASE 0xfcfe0000
16#define WTCSR 0x00
17#define WTCNT 0x02
18#define WRCSR 0x04
19
20DECLARE_GLOBAL_DATA_PTR;
21
22int board_init(void)
23{
Tom Rinibb4dd962022-11-16 13:10:37 -050024 gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
Chris Brandt1f3b6672017-08-23 14:53:59 -050025
26 return 0;
27}
28
29int dram_init(void)
30{
31 if (fdtdec_setup_mem_size_base() != 0)
32 return -EINVAL;
33
34 return 0;
35}
36
37int dram_init_banksize(void)
38{
39 fdtdec_setup_memory_banksize();
40
41 return 0;
42}
43
Harald Seiler6f14d5f2020-12-15 16:47:52 +010044void reset_cpu(void)
Chris Brandt1f3b6672017-08-23 14:53:59 -050045{
46 /* Dummy read (must read WRCSR:WOVF at least once before clearing) */
47 readb(RZA1_WDT_BASE + WRCSR);
48
49 writew(0xa500, RZA1_WDT_BASE + WRCSR);
50 writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
51 writew(0x5a00, RZA1_WDT_BASE + WTCNT);
52 writew(0xa578, RZA1_WDT_BASE + WTCSR);
53
54 for (;;)
55 asm volatile("wfi");
56}