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liu hao1c4a2c42019-10-31 07:51:08 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019
4 * shuyiqi <shuyiqi@phytium.com.cn>
5 * liuhao <liuhao@phytium.com.cn>
6 */
7
8#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06009#include <command.h>
Simon Glassafb02152019-12-28 10:45:01 -070010#include <cpu_func.h>
Simon Glass1cedca12023-08-21 21:17:01 -060011#include <event.h>
Simon Glass97589732020-05-10 11:40:02 -060012#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
liu hao1c4a2c42019-10-31 07:51:08 +000014#include <asm/armv8/mmu.h>
Simon Glass274e0b02020-05-10 11:39:56 -060015#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
liu hao1c4a2c42019-10-31 07:51:08 +000017#include <asm/system.h>
18#include <asm/io.h>
19#include <linux/arm-smccc.h>
20#include <linux/kernel.h>
21#include <scsi.h>
22#include "cpu.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26int dram_init(void)
27{
28 gd->mem_clk = 0;
29 gd->ram_size = PHYS_SDRAM_1_SIZE;
30 return 0;
31}
32
33int dram_init_banksize(void)
34{
35 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
36 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
37
38 return 0;
39}
40
41int board_init(void)
42{
43 return 0;
44}
45
Harald Seiler6f14d5f2020-12-15 16:47:52 +010046void reset_cpu(void)
liu hao1c4a2c42019-10-31 07:51:08 +000047{
48 struct arm_smccc_res res;
49
50 arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
51 debug("reset cpu error, %lx\n", res.a0);
52}
53
54static struct mm_region durian_mem_map[] = {
55 {
56 .virt = 0x0UL,
57 .phys = 0x0UL,
58 .size = 0x80000000UL,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
60 PTE_BLOCK_NON_SHARE |
61 PTE_BLOCK_PXN |
62 PTE_BLOCK_UXN
63 },
64 {
65 .virt = (u64)PHYS_SDRAM_1,
66 .phys = (u64)PHYS_SDRAM_1,
67 .size = (u64)PHYS_SDRAM_1_SIZE,
68 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
69 PTE_BLOCK_NS |
70 PTE_BLOCK_INNER_SHARE
71 },
72 {
73 0,
74 }
75};
76
77struct mm_region *mem_map = durian_mem_map;
78
79int print_cpuinfo(void)
80{
81 printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
82 return 0;
83}
84
85int __asm_flush_l3_dcache(void)
86{
87 int i, pstate;
88
89 for (i = 0; i < HNF_COUNT; i++)
90 writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
91 for (i = 0; i < HNF_COUNT; i++) {
92 do {
93 pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
94 } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
95 }
96
97 for (i = 0; i < HNF_COUNT; i++)
98 writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
99
100 return 0;
101}
102
Simon Glass1cedca12023-08-21 21:17:01 -0600103static int last_stage_init(void)
liu hao1c4a2c42019-10-31 07:51:08 +0000104{
105 int ret;
106
107 /* pci e */
108 pci_init();
109 /* scsi scan */
110 ret = scsi_scan(true);
111 if (ret) {
112 printf("scsi scan failed\n");
113 return CMD_RET_FAILURE;
114 }
115 return ret;
116}
Simon Glass1cedca12023-08-21 21:17:01 -0600117EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);