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git01.mediatek.com / filogic / uboot / a1a88d250a50c39a52482d5a69748d7bd13216c8 / . / arch / arm / dts / rk356x-u-boot.dtsi
blob: d347080577d9cb9dd0f327d576fa26a29d7f2e2e [file] [log] [blame]
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
Quentin Schulzd9ffa5e2022-09-02 15:10:52 +0200[diff] [blame]6#include "rockchip-u-boot.dtsi"
7
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]8/ {
9 aliases {
10 mmc0 = &sdhci;
11 mmc1 = &sdmmc0;
Jonas Karlmanaec644c2023-07-28 12:05:40 +0000[diff] [blame]12 spi4 = &sfc;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]13 };
14
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]15 chosen {
Jonas Karlmandab889e2023-07-28 11:53:08 +0000[diff] [blame]16 u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]17 };
18
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]19 dmc: dmc {
20 compatible = "rockchip,rk3568-dmc";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]22 };
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000[diff] [blame]23
24 otp: nvmem@fe38c000 {
25 compatible = "rockchip,rk3568-otp";
26 reg = <0x0 0xfe38c000 0x0 0x4000>;
27 #address-cells = <1>;
28 #size-cells = <1>;
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000[diff] [blame]29
30 cpu_id: id@a {
31 reg = <0x0a 0x10>;
32 };
33 };
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]34};
35
Jonas Karlman13e3dc92023-05-17 18:26:29 +0000[diff] [blame]36&xin24m {
37 bootph-all;
Jonas Karlman13e3dc92023-05-17 18:26:29 +0000[diff] [blame]38};
39
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]40&cru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]42};
43
44&pmucru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]46};
47
48&grf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]50};
51
52&pmugrf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]54};
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]55
Jonas Karlmanf216c612023-07-28 11:53:07 +0000[diff] [blame]56&pinctrl {
57 bootph-all;
58};
59
Jonas Karlmanc6391352023-08-03 21:11:54 +0000[diff] [blame]60&pcfg_pull_none_smt {
61 bootph-all;
62};
63
Jonas Karlmanf216c612023-07-28 11:53:07 +0000[diff] [blame]64&pcfg_pull_none {
65 bootph-all;
66};
67
68&pcfg_pull_up_drv_level_2 {
69 bootph-all;
70};
71
72&pcfg_pull_up {
73 bootph-all;
74};
75
76&emmc_bus8 {
77 bootph-all;
78};
79
80&emmc_clk {
81 bootph-all;
82};
83
84&emmc_cmd {
85 bootph-all;
86};
87
88&emmc_datastrobe {
89 bootph-all;
90};
91
92&emmc_rstnout {
93 bootph-all;
94};
95
96&fspi_pins {
97 bootph-all;
98};
99
Jonas Karlmanc6391352023-08-03 21:11:54 +0000[diff] [blame]100&i2c0_xfer {
101 bootph-all;
102};
103
Jonas Karlmanf216c612023-07-28 11:53:07 +0000[diff] [blame]104&sdmmc0_bus4 {
105 bootph-all;
106};
107
108&sdmmc0_clk {
109 bootph-all;
110};
111
112&sdmmc0_cmd {
113 bootph-all;
114};
115
116&sdmmc0_det {
117 bootph-all;
118};
119
120&sdmmc0_pwren {
121 bootph-all;
122};
123
124&uart2m0_xfer {
125 bootph-all;
126};
127
FUKAUMI Naoki98dc96a2022-10-04 01:30:30 +0000[diff] [blame]128&sdhci {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Jonas Karlmane8841382023-08-04 09:34:01 +0000[diff] [blame]130 max-frequency = <200000000>;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]131};
132
FUKAUMI Naoki98dc96a2022-10-04 01:30:30 +0000[diff] [blame]133&sdmmc0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]134 bootph-pre-ram;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]135};
Jonas Karlmana9d8d532023-05-17 18:26:35 +0000[diff] [blame]136
Jonas Karlman1fb8b8d2024-01-26 22:14:51 +0000[diff] [blame]137&uart2 {
138 bootph-pre-ram;
139 clock-frequency = <24000000>;
140};
141
Jonas Karlmana9d8d532023-05-17 18:26:35 +0000[diff] [blame]142#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
143&binman {
144 simple-bin-spi {
145 mkimage {
146 args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
147 offset = <0x8000>;
148 };
149 };
150};
151#endif