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git01.mediatek.com / filogic / uboot / a181afef1bb21f41437261e938960d6f294366e0 / . / arch / arm / dts / imx8mn-ddr4-evk.dts
blob: 9b2c1727a862d2388e0ffc71a7b91be46e62568b [file] [log] [blame]
Peng Fana181afe2019-09-16 03:09:55 +0000[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mn.dtsi"
9
10/ {
11 model = "NXP i.MX8MNano DDR4 EVK board";
12 compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
13
14 chosen {
15 stdout-path = &uart2;
16 };
17
18 reg_usdhc2_vmmc: regulator-usdhc2 {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
22 regulator-name = "VSD_3V3";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
25 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
26 enable-active-high;
27 };
28};
29
30&iomuxc {
31 pinctrl-names = "default";
32
33 pinctrl_fec1: fec1grp {
34 fsl,pins = <
35 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
36 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
37 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
38 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
39 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
40 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
41 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
42 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
43 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
44 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
45 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
46 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
47 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
48 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
49 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
50 >;
51 };
52
53 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
54 fsl,pins = <
55 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
56 >;
57 };
58
59 pinctrl_uart2: uart2grp {
60 fsl,pins = <
61 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
62 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
63 >;
64 };
65
66 pinctrl_usdhc2_gpio: usdhc2grpgpio {
67 fsl,pins = <
68 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
69 >;
70 };
71
72 pinctrl_usdhc2: usdhc2grp {
73 fsl,pins = <
74 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
75 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
76 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
77 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
78 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
79 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
80 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
81 >;
82 };
83
84 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
85 fsl,pins = <
86 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
87 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
88 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
89 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
90 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
91 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
92 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
93 >;
94 };
95
96 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
97 fsl,pins = <
98 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
99 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
100 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
101 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
102 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
103 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
104 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
105 >;
106 };
107
108 pinctrl_usdhc3: usdhc3grp {
109 fsl,pins = <
110 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
111 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
112 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
113 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
114 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
115 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
116 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
117 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
118 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
119 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
120 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
121 >;
122 };
123
124 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
125 fsl,pins = <
126 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
127 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
128 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
129 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
130 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
131 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
132 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
133 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
134 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
135 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
136 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
137 >;
138 };
139
140 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
141 fsl,pins = <
142 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
143 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
144 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
145 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
146 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
147 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
148 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
149 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
150 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
151 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
152 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
153 >;
154 };
155
156 pinctrl_wdog: wdoggrp {
157 fsl,pins = <
158 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
159 >;
160 };
161};
162
163&fec1 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_fec1>;
166 phy-mode = "rgmii-id";
167 phy-handle = <&ethphy0>;
168 fsl,magic-packet;
169 status = "okay";
170
171 mdio {
172 #address-cells = <1>;
173 #size-cells = <0>;
174
175 ethphy0: ethernet-phy@0 {
176 compatible = "ethernet-phy-ieee802.3-c22";
177 reg = <0>;
178 at803x,led-act-blind-workaround;
179 at803x,eee-disabled;
180 at803x,vddio-1p8v;
181 };
182 };
183};
184
185&snvs_pwrkey {
186 status = "okay";
187};
188
189&uart2 { /* console */
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_uart2>;
192 status = "okay";
193};
194
195&usdhc2 {
196 pinctrl-names = "default", "state_100mhz", "state_200mhz";
197 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
198 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
199 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
200 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
201 bus-width = <4>;
202 vmmc-supply = <&reg_usdhc2_vmmc>;
203 status = "okay";
204};
205
206&usdhc3 {
207 pinctrl-names = "default", "state_100mhz", "state_200mhz";
208 pinctrl-0 = <&pinctrl_usdhc3>;
209 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
210 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
211 bus-width = <8>;
212 non-removable;
213 status = "okay";
214};
215
216&wdog1 {
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_wdog>;
219 fsl,ext-reset-output;
220 status = "okay";
221};