| Dan Murphy | bb5a566 | 2016-05-02 15:45:58 -0500 | [diff] [blame] | 1 | * Texas Instruments - dp83867 Giga bit ethernet phy |
| 2 | |
| 3 | Required properties: |
| 4 | - reg - The ID number for the phy, usually a small integer |
| 5 | - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h |
| 6 | for applicable values |
| 7 | - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h |
| 8 | for applicable values |
| 9 | - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h |
| 10 | for applicable values |
| Janine Hagemann | ed51bfc | 2018-08-28 08:25:37 +0200 | [diff] [blame] | 11 | - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to |
| 12 | compensate for the board being designed with the lanes swapped. |
| 13 | - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the |
| 14 | TX/RX lanes. |
| Janine Hagemann | 1c2ba09 | 2018-08-28 08:25:39 +0200 | [diff] [blame] | 15 | - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h |
| 16 | for applicable values |
| Dan Murphy | bb5a566 | 2016-05-02 15:45:58 -0500 | [diff] [blame] | 17 | |
| 18 | Default child nodes are standard Ethernet PHY device |
| 19 | nodes as described in doc/devicetree/bindings/net/ethernet.txt |
| 20 | |
| 21 | Example: |
| 22 | |
| 23 | ethernet-phy@0 { |
| 24 | reg = <0>; |
| 25 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
| 26 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; |
| 27 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| Janine Hagemann | ed51bfc | 2018-08-28 08:25:37 +0200 | [diff] [blame] | 28 | enet-phy-lane-no-swap; |
| Janine Hagemann | 1c2ba09 | 2018-08-28 08:25:39 +0200 | [diff] [blame] | 29 | ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; |
| Dan Murphy | bb5a566 | 2016-05-02 15:45:58 -0500 | [diff] [blame] | 30 | }; |
| 31 | |
| 32 | Datasheet can be found: |
| 33 | http://www.ti.com/product/DP83867IR/datasheet |