blob: 438ed41e8d5f03ab54b70c191acc0882cd8721ea [file] [log] [blame]
Yannick Fertré1334cf22019-10-07 15:29:07 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
4 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
5 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
6 *
7 * This MIPI DSI controller driver is based on the Linux Kernel driver from
8 * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c.
9 */
10
Patrick Delaunay26d05cb2020-11-06 19:01:58 +010011#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE
12
Yannick Fertré1334cf22019-10-07 15:29:07 +020013#include <clk.h>
14#include <dm.h>
15#include <dsi_host.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
Yannick Fertré1334cf22019-10-07 15:29:07 +020017#include <mipi_dsi.h>
18#include <panel.h>
19#include <reset.h>
20#include <video.h>
21#include <video_bridge.h>
22#include <asm/io.h>
Yannick Fertré1334cf22019-10-07 15:29:07 +020023#include <dm/device-internal.h>
Simon Glass9bc15642020-02-03 07:36:16 -070024#include <dm/device_compat.h>
Patrick Delaunayc44ae812019-11-12 15:39:58 +010025#include <dm/lists.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060026#include <linux/bitops.h>
Yannick Fertré1334cf22019-10-07 15:29:07 +020027#include <linux/iopoll.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060028#include <linux/printk.h>
Yannick Fertré1334cf22019-10-07 15:29:07 +020029#include <power/regulator.h>
30
31#define HWVER_130 0x31333000 /* IP version 1.30 */
32#define HWVER_131 0x31333100 /* IP version 1.31 */
33
34/* DSI digital registers & bit definitions */
35#define DSI_VERSION 0x00
36#define VERSION GENMASK(31, 8)
37
38/*
39 * DSI wrapper registers & bit definitions
40 * Note: registers are named as in the Reference Manual
41 */
42#define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
43#define WCFGR_DSIM BIT(0) /* DSI Mode */
44#define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */
45
46#define DSI_WCR 0x0404 /* Wrapper Control Reg */
47#define WCR_DSIEN BIT(3) /* DSI ENable */
48
49#define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */
50#define WISR_PLLLS BIT(8) /* PLL Lock Status */
51#define WISR_RRS BIT(12) /* Regulator Ready Status */
52
53#define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */
54#define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */
55#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
56
57#define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
58#define WRPCR_PLLEN BIT(0) /* PLL ENable */
59#define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
60#define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
61#define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
62#define WRPCR_REGEN BIT(24) /* REGulator ENable */
63#define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */
64#define IDF_MIN 1
65#define IDF_MAX 7
66#define NDIV_MIN 10
67#define NDIV_MAX 125
68#define ODF_MIN 1
69#define ODF_MAX 8
70
71/* dsi color format coding according to the datasheet */
72enum dsi_color {
73 DSI_RGB565_CONF1,
74 DSI_RGB565_CONF2,
75 DSI_RGB565_CONF3,
76 DSI_RGB666_CONF1,
77 DSI_RGB666_CONF2,
78 DSI_RGB888,
79};
80
81#define LANE_MIN_KBPS 31250
82#define LANE_MAX_KBPS 500000
83
84/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
85#define TIMEOUT_US 200000
86
87struct stm32_dsi_priv {
88 struct mipi_dsi_device device;
89 void __iomem *base;
90 struct udevice *panel;
91 u32 pllref_clk;
92 u32 hw_version;
93 int lane_min_kbps;
94 int lane_max_kbps;
95 struct udevice *vdd_reg;
96 struct udevice *dsi_host;
97};
98
99static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
100{
101 writel(val, dsi->base + reg);
102}
103
104static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
105{
106 return readl(dsi->base + reg);
107}
108
109static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
110{
111 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
112}
113
114static inline void dsi_clear(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
115{
116 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
117}
118
119static inline void dsi_update_bits(struct stm32_dsi_priv *dsi, u32 reg,
120 u32 mask, u32 val)
121{
122 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
123}
124
125static enum dsi_color dsi_color_from_mipi(u32 fmt)
126{
127 switch (fmt) {
128 case MIPI_DSI_FMT_RGB888:
129 return DSI_RGB888;
130 case MIPI_DSI_FMT_RGB666:
131 return DSI_RGB666_CONF2;
132 case MIPI_DSI_FMT_RGB666_PACKED:
133 return DSI_RGB666_CONF1;
134 case MIPI_DSI_FMT_RGB565:
135 return DSI_RGB565_CONF1;
136 default:
Patrick Delaunay26d05cb2020-11-06 19:01:58 +0100137 log_err("MIPI color invalid, so we use rgb888\n");
Yannick Fertré1334cf22019-10-07 15:29:07 +0200138 }
139 return DSI_RGB888;
140}
141
142static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
143{
144 int divisor = idf * odf;
145
146 /* prevent from division by 0 */
147 if (!divisor)
148 return 0;
149
150 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
151}
152
153static int dsi_pll_get_params(struct stm32_dsi_priv *dsi,
154 int clkin_khz, int clkout_khz,
155 int *idf, int *ndiv, int *odf)
156{
157 int i, o, n, n_min, n_max;
158 int fvco_min, fvco_max, delta, best_delta; /* all in khz */
159
160 /* Early checks preventing division by 0 & odd results */
161 if (clkin_khz <= 0 || clkout_khz <= 0)
162 return -EINVAL;
163
164 fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
165 fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
166
167 best_delta = 1000000; /* big started value (1000000khz) */
168
169 for (i = IDF_MIN; i <= IDF_MAX; i++) {
170 /* Compute ndiv range according to Fvco */
171 n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
172 n_max = (fvco_max * i) / (2 * clkin_khz);
173
174 /* No need to continue idf loop if we reach ndiv max */
175 if (n_min >= NDIV_MAX)
176 break;
177
178 /* Clamp ndiv to valid values */
179 if (n_min < NDIV_MIN)
180 n_min = NDIV_MIN;
181 if (n_max > NDIV_MAX)
182 n_max = NDIV_MAX;
183
184 for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
185 n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
186 /* Check ndiv according to vco range */
187 if (n < n_min || n > n_max)
188 continue;
189 /* Check if new delta is better & saves parameters */
190 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
191 clkout_khz;
192 if (delta < 0)
193 delta = -delta;
194 if (delta < best_delta) {
195 *idf = i;
196 *ndiv = n;
197 *odf = o;
198 best_delta = delta;
199 }
200 /* fast return in case of "perfect result" */
201 if (!delta)
202 return 0;
203 }
204 }
205
206 return 0;
207}
208
209static int dsi_phy_init(void *priv_data)
210{
211 struct mipi_dsi_device *device = priv_data;
212 struct udevice *dev = device->dev;
213 struct stm32_dsi_priv *dsi = dev_get_priv(dev);
214 u32 val;
215 int ret;
216
Patrick Delaunay26d05cb2020-11-06 19:01:58 +0100217 dev_dbg(dev, "Initialize DSI physical layer\n");
Yannick Fertré1334cf22019-10-07 15:29:07 +0200218
219 /* Enable the regulator */
220 dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
221 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
222 TIMEOUT_US);
223 if (ret) {
Patrick Delaunay26d05cb2020-11-06 19:01:58 +0100224 dev_dbg(dev, "!TIMEOUT! waiting REGU\n");
Yannick Fertré1334cf22019-10-07 15:29:07 +0200225 return ret;
226 }
227
228 /* Enable the DSI PLL & wait for its lock */
229 dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
230 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
231 TIMEOUT_US);
232 if (ret) {
Patrick Delaunay26d05cb2020-11-06 19:01:58 +0100233 dev_dbg(dev, "!TIMEOUT! waiting PLL\n");
Yannick Fertré1334cf22019-10-07 15:29:07 +0200234 return ret;
235 }
236
237 return 0;
238}
239
240static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
241{
242 struct mipi_dsi_device *device = priv_data;
243 struct udevice *dev = device->dev;
244 struct stm32_dsi_priv *dsi = dev_get_priv(dev);
245
Patrick Delaunay26d05cb2020-11-06 19:01:58 +0100246 dev_dbg(dev, "Set mode %p enable %ld\n", dsi,
247 mode_flags & MIPI_DSI_MODE_VIDEO);
Yannick Fertré1334cf22019-10-07 15:29:07 +0200248
249 if (!dsi)
250 return;
251
252 /*
253 * DSI wrapper must be enabled in video mode & disabled in command mode.
254 * If wrapper is enabled in command mode, the display controller
255 * register access will hang.
256 */
257
258 if (mode_flags & MIPI_DSI_MODE_VIDEO)
259 dsi_set(dsi, DSI_WCR, WCR_DSIEN);
260 else
261 dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
262}
263
264static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
265 u32 lanes, u32 format, unsigned int *lane_mbps)
266{
267 struct mipi_dsi_device *device = priv_data;
268 struct udevice *dev = device->dev;
269 struct stm32_dsi_priv *dsi = dev_get_priv(dev);
270 int idf, ndiv, odf, pll_in_khz, pll_out_khz;
271 int ret, bpp;
272 u32 val;
273
274 /* Update lane capabilities according to hw version */
Yannick Fertré1334cf22019-10-07 15:29:07 +0200275 dsi->lane_min_kbps = LANE_MIN_KBPS;
276 dsi->lane_max_kbps = LANE_MAX_KBPS;
277 if (dsi->hw_version == HWVER_131) {
278 dsi->lane_min_kbps *= 2;
279 dsi->lane_max_kbps *= 2;
280 }
281
282 pll_in_khz = dsi->pllref_clk / 1000;
283
284 /* Compute requested pll out */
285 bpp = mipi_dsi_pixel_format_to_bpp(format);
286 pll_out_khz = (timings->pixelclock.typ / 1000) * bpp / lanes;
287 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */
288 pll_out_khz = (pll_out_khz * 12) / 10;
289 if (pll_out_khz > dsi->lane_max_kbps) {
290 pll_out_khz = dsi->lane_max_kbps;
291 dev_warn(dev, "Warning max phy mbps is used\n");
292 }
293 if (pll_out_khz < dsi->lane_min_kbps) {
294 pll_out_khz = dsi->lane_min_kbps;
295 dev_warn(dev, "Warning min phy mbps is used\n");
296 }
297
298 /* Compute best pll parameters */
299 idf = 0;
300 ndiv = 0;
301 odf = 0;
302 ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
303 &idf, &ndiv, &odf);
304 if (ret) {
305 dev_err(dev, "Warning dsi_pll_get_params(): bad params\n");
306 return ret;
307 }
308
309 /* Get the adjusted pll out value */
310 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
311
312 /* Set the PLL division factors */
313 dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
314 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
315
316 /* Compute uix4 & set the bit period in high-speed mode */
317 val = 4000000 / pll_out_khz;
318 dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
319
320 /* Select video mode by resetting DSIM bit */
321 dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
322
323 /* Select the color coding */
324 dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
325 dsi_color_from_mipi(format) << 1);
326
327 *lane_mbps = pll_out_khz / 1000;
328
Patrick Delaunay26d05cb2020-11-06 19:01:58 +0100329 dev_dbg(dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
330 pll_in_khz, pll_out_khz, *lane_mbps);
Yannick Fertré1334cf22019-10-07 15:29:07 +0200331
332 return 0;
333}
334
335static const struct mipi_dsi_phy_ops dsi_stm_phy_ops = {
336 .init = dsi_phy_init,
337 .get_lane_mbps = dsi_get_lane_mbps,
338 .post_set_mode = dsi_phy_post_set_mode,
339};
340
341static int stm32_dsi_attach(struct udevice *dev)
342{
343 struct stm32_dsi_priv *priv = dev_get_priv(dev);
344 struct mipi_dsi_device *device = &priv->device;
345 struct mipi_dsi_panel_plat *mplat;
346 struct display_timing timings;
347 int ret;
348
Michal Suchanekac12a2f2022-10-12 21:57:59 +0200349 ret = uclass_first_device_err(UCLASS_PANEL, &priv->panel);
Yannick Fertré1334cf22019-10-07 15:29:07 +0200350 if (ret) {
351 dev_err(dev, "panel device error %d\n", ret);
352 return ret;
353 }
354
Simon Glassfa20e932020-12-03 16:55:20 -0700355 mplat = dev_get_plat(priv->panel);
Yannick Fertré1334cf22019-10-07 15:29:07 +0200356 mplat->device = &priv->device;
Yannick Fertre581449b2020-06-24 10:45:40 +0200357 device->lanes = mplat->lanes;
358 device->format = mplat->format;
359 device->mode_flags = mplat->mode_flags;
Yannick Fertré1334cf22019-10-07 15:29:07 +0200360
361 ret = panel_get_display_timing(priv->panel, &timings);
362 if (ret) {
Patrick Delaunaybf7d97d2020-09-09 17:44:13 +0200363 ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
Yannick Fertré1334cf22019-10-07 15:29:07 +0200364 0, &timings);
365 if (ret) {
366 dev_err(dev, "decode display timing error %d\n", ret);
367 return ret;
368 }
369 }
370
371 ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
372 if (ret) {
373 dev_err(dev, "No video dsi host detected %d\n", ret);
374 return ret;
375 }
376
377 ret = dsi_host_init(priv->dsi_host, device, &timings, 2,
378 &dsi_stm_phy_ops);
379 if (ret) {
380 dev_err(dev, "failed to initialize mipi dsi host\n");
381 return ret;
382 }
383
384 return 0;
385}
386
387static int stm32_dsi_set_backlight(struct udevice *dev, int percent)
388{
389 struct stm32_dsi_priv *priv = dev_get_priv(dev);
390 int ret;
391
392 ret = panel_enable_backlight(priv->panel);
393 if (ret) {
394 dev_err(dev, "panel %s enable backlight error %d\n",
395 priv->panel->name, ret);
396 return ret;
397 }
398
399 ret = dsi_host_enable(priv->dsi_host);
400 if (ret) {
401 dev_err(dev, "failed to enable mipi dsi host\n");
402 return ret;
403 }
404
405 return 0;
406}
407
Patrick Delaunayc44ae812019-11-12 15:39:58 +0100408static int stm32_dsi_bind(struct udevice *dev)
409{
410 int ret;
411
412 ret = device_bind_driver_to_node(dev, "dw_mipi_dsi", "dsihost",
413 dev_ofnode(dev), NULL);
414 if (ret)
415 return ret;
416
417 return dm_scan_fdt_dev(dev);
418}
419
Yannick Fertré1334cf22019-10-07 15:29:07 +0200420static int stm32_dsi_probe(struct udevice *dev)
421{
422 struct stm32_dsi_priv *priv = dev_get_priv(dev);
423 struct mipi_dsi_device *device = &priv->device;
424 struct reset_ctl rst;
425 struct clk clk;
426 int ret;
427
428 device->dev = dev;
429
Johan Jonker8d5d8e02023-03-13 01:32:04 +0100430 priv->base = dev_read_addr_ptr(dev);
431 if (!priv->base) {
Yannick Fertré1334cf22019-10-07 15:29:07 +0200432 dev_err(dev, "dsi dt register address error\n");
433 return -EINVAL;
434 }
435
Patrick Delaunay4d9bb102022-06-20 11:55:07 +0200436 ret = device_get_supply_regulator(dev, "phy-dsi-supply",
437 &priv->vdd_reg);
438 if (ret && ret != -ENOENT) {
439 dev_err(dev, "Warning: cannot get phy dsi supply\n");
440 return -ENODEV;
441 }
Yannick Fertré1334cf22019-10-07 15:29:07 +0200442
Patrick Delaunay4d9bb102022-06-20 11:55:07 +0200443 if (ret != -ENOENT) {
444 ret = regulator_set_enable(priv->vdd_reg, true);
445 if (ret)
446 return ret;
Yannick Fertré1334cf22019-10-07 15:29:07 +0200447 }
448
449 ret = clk_get_by_name(device->dev, "pclk", &clk);
450 if (ret) {
451 dev_err(dev, "peripheral clock get error %d\n", ret);
452 goto err_reg;
453 }
454
455 ret = clk_enable(&clk);
456 if (ret) {
457 dev_err(dev, "peripheral clock enable error %d\n", ret);
458 goto err_reg;
459 }
460
461 ret = clk_get_by_name(dev, "ref", &clk);
462 if (ret) {
463 dev_err(dev, "pll reference clock get error %d\n", ret);
464 goto err_clk;
465 }
466
467 priv->pllref_clk = (unsigned int)clk_get_rate(&clk);
468
469 ret = reset_get_by_index(device->dev, 0, &rst);
470 if (ret) {
471 dev_err(dev, "missing dsi hardware reset\n");
472 goto err_clk;
473 }
474
475 /* Reset */
476 reset_deassert(&rst);
477
Yannick Fertre402ac702020-06-24 10:43:59 +0200478 /* check hardware version */
479 priv->hw_version = dsi_read(priv, DSI_VERSION) & VERSION;
480 if (priv->hw_version != HWVER_130 &&
481 priv->hw_version != HWVER_131) {
482 dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version);
Patrick Delaunay73b67052021-03-04 13:10:33 +0100483 dev_dbg(dev, "remove and unbind all DSI child\n");
484 device_chld_remove(dev, NULL, DM_REMOVE_NORMAL);
485 device_chld_unbind(dev, NULL);
Yannick Fertre402ac702020-06-24 10:43:59 +0200486 ret = -ENODEV;
487 goto err_clk;
488 }
489
Yannick Fertré1334cf22019-10-07 15:29:07 +0200490 return 0;
491err_clk:
492 clk_disable(&clk);
493err_reg:
Patrick Delaunay4d9bb102022-06-20 11:55:07 +0200494 regulator_set_enable(priv->vdd_reg, false);
Yannick Fertré1334cf22019-10-07 15:29:07 +0200495
496 return ret;
497}
498
499struct video_bridge_ops stm32_dsi_ops = {
500 .attach = stm32_dsi_attach,
501 .set_backlight = stm32_dsi_set_backlight,
502};
503
504static const struct udevice_id stm32_dsi_ids[] = {
505 { .compatible = "st,stm32-dsi"},
506 { }
507};
508
509U_BOOT_DRIVER(stm32_dsi) = {
510 .name = "stm32-display-dsi",
511 .id = UCLASS_VIDEO_BRIDGE,
512 .of_match = stm32_dsi_ids,
Patrick Delaunayc44ae812019-11-12 15:39:58 +0100513 .bind = stm32_dsi_bind,
Yannick Fertré1334cf22019-10-07 15:29:07 +0200514 .probe = stm32_dsi_probe,
515 .ops = &stm32_dsi_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700516 .priv_auto = sizeof(struct stm32_dsi_priv),
Yannick Fertré1334cf22019-10-07 15:29:07 +0200517};