Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 2 | /* |
Michal Simek | 98d0f1f | 2018-01-17 07:37:47 +0100 | [diff] [blame] | 3 | * Copyright (c) 2013 - 2017 Xilinx Inc. |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 6 | #include <asm/io.h> |
| 7 | #include <malloc.h> |
| 8 | #include <asm/arch/hardware.h> |
Michal Simek | 90b8064 | 2014-04-25 13:48:08 +0200 | [diff] [blame] | 9 | #include <asm/arch/sys_proto.h> |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 10 | |
| 11 | #define SLCR_LOCK_MAGIC 0x767B |
| 12 | #define SLCR_UNLOCK_MAGIC 0xDF0D |
| 13 | |
Michal Simek | 42e942f | 2016-10-26 10:49:37 +0200 | [diff] [blame] | 14 | #define SLCR_NAND_L2_SEL 0x10 |
| 15 | #define SLCR_NAND_L2_SEL_MASK 0x1F |
| 16 | |
Michal Simek | ec02820 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 17 | #define SLCR_USB_L1_SEL 0x04 |
| 18 | |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 19 | #define SLCR_IDCODE_MASK 0x1F000 |
| 20 | #define SLCR_IDCODE_SHIFT 12 |
| 21 | |
Michal Simek | 8d19162 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 22 | /* |
| 23 | * zynq_slcr_mio_get_status - Get the status of MIO peripheral. |
| 24 | * |
| 25 | * @peri_name: Name of the peripheral for checking MIO status |
| 26 | * @get_pins: Pointer to array of get pin for this peripheral |
| 27 | * @num_pins: Number of pins for this peripheral |
| 28 | * @mask: Mask value |
| 29 | * @check_val: Required check value to get the status of periph |
| 30 | */ |
| 31 | struct zynq_slcr_mio_get_status { |
| 32 | const char *peri_name; |
| 33 | const int *get_pins; |
| 34 | int num_pins; |
| 35 | u32 mask; |
| 36 | u32 check_val; |
| 37 | }; |
| 38 | |
Michal Simek | 42e942f | 2016-10-26 10:49:37 +0200 | [diff] [blame] | 39 | static const int nand8_pins[] = { |
| 40 | 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 |
| 41 | }; |
| 42 | |
| 43 | static const int nand16_pins[] = { |
| 44 | 16, 17, 18, 19, 20, 21, 22, 23 |
| 45 | }; |
| 46 | |
Michal Simek | ec02820 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 47 | static const int usb0_pins[] = { |
| 48 | 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 |
| 49 | }; |
| 50 | |
| 51 | static const int usb1_pins[] = { |
| 52 | 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51 |
| 53 | }; |
| 54 | |
Michal Simek | 8d19162 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 55 | static const struct zynq_slcr_mio_get_status mio_periphs[] = { |
Michal Simek | ec02820 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 56 | { |
Michal Simek | 42e942f | 2016-10-26 10:49:37 +0200 | [diff] [blame] | 57 | "nand8", |
| 58 | nand8_pins, |
| 59 | ARRAY_SIZE(nand8_pins), |
| 60 | SLCR_NAND_L2_SEL_MASK, |
| 61 | SLCR_NAND_L2_SEL, |
| 62 | }, |
| 63 | { |
| 64 | "nand16", |
| 65 | nand16_pins, |
| 66 | ARRAY_SIZE(nand16_pins), |
| 67 | SLCR_NAND_L2_SEL_MASK, |
| 68 | SLCR_NAND_L2_SEL, |
| 69 | }, |
| 70 | { |
Michal Simek | ec02820 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 71 | "usb0", |
| 72 | usb0_pins, |
| 73 | ARRAY_SIZE(usb0_pins), |
| 74 | SLCR_USB_L1_SEL, |
| 75 | SLCR_USB_L1_SEL, |
| 76 | }, |
| 77 | { |
| 78 | "usb1", |
| 79 | usb1_pins, |
| 80 | ARRAY_SIZE(usb1_pins), |
| 81 | SLCR_USB_L1_SEL, |
| 82 | SLCR_USB_L1_SEL, |
| 83 | }, |
Michal Simek | 8d19162 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 84 | }; |
| 85 | |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 86 | static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ |
| 87 | |
| 88 | void zynq_slcr_lock(void) |
| 89 | { |
Michal Simek | bc73304 | 2013-08-30 07:26:08 +0200 | [diff] [blame] | 90 | if (!slcr_lock) { |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 91 | writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); |
Michal Simek | bc73304 | 2013-08-30 07:26:08 +0200 | [diff] [blame] | 92 | slcr_lock = 1; |
| 93 | } |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 94 | } |
| 95 | |
| 96 | void zynq_slcr_unlock(void) |
| 97 | { |
Michal Simek | bc73304 | 2013-08-30 07:26:08 +0200 | [diff] [blame] | 98 | if (slcr_lock) { |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 99 | writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); |
Michal Simek | bc73304 | 2013-08-30 07:26:08 +0200 | [diff] [blame] | 100 | slcr_lock = 0; |
| 101 | } |
Michal Simek | eb1dfa7 | 2013-02-04 12:38:59 +0100 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | /* Reset the entire system */ |
| 105 | void zynq_slcr_cpu_reset(void) |
| 106 | { |
| 107 | /* |
| 108 | * Unlock the SLCR then reset the system. |
| 109 | * Note that this seems to require raw i/o |
| 110 | * functions or there's a lockup? |
| 111 | */ |
| 112 | zynq_slcr_unlock(); |
| 113 | |
| 114 | /* |
| 115 | * Clear 0x0F000000 bits of reboot status register to workaround |
| 116 | * the FSBL not loading the bitstream after soft-reboot |
| 117 | * This is a temporary solution until we know more. |
| 118 | */ |
| 119 | clrbits_le32(&slcr_base->reboot_status, 0xF000000); |
| 120 | |
| 121 | writel(1, &slcr_base->pss_rst_ctrl); |
| 122 | } |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 123 | |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 124 | void zynq_slcr_devcfg_disable(void) |
| 125 | { |
Siva Durga Prasad Paladugu | be0bf69 | 2015-03-02 16:03:46 +0530 | [diff] [blame] | 126 | u32 reg_val; |
| 127 | |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 128 | zynq_slcr_unlock(); |
| 129 | |
Michal Simek | 7cffeb0 | 2014-03-27 10:06:43 +0100 | [diff] [blame] | 130 | /* Disable AXI interface by asserting FPGA resets */ |
Siva Durga Prasad Paladugu | 250e605 | 2014-10-28 11:22:19 +0530 | [diff] [blame] | 131 | writel(0xF, &slcr_base->fpga_rst_ctrl); |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 132 | |
Siva Durga Prasad Paladugu | be0bf69 | 2015-03-02 16:03:46 +0530 | [diff] [blame] | 133 | /* Disable Level shifters before setting PS-PL */ |
| 134 | reg_val = readl(&slcr_base->lvl_shftr_en); |
| 135 | reg_val &= ~0xF; |
| 136 | writel(reg_val, &slcr_base->lvl_shftr_en); |
| 137 | |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 138 | /* Set Level Shifters DT618760 */ |
| 139 | writel(0xA, &slcr_base->lvl_shftr_en); |
| 140 | |
| 141 | zynq_slcr_lock(); |
| 142 | } |
| 143 | |
| 144 | void zynq_slcr_devcfg_enable(void) |
| 145 | { |
| 146 | zynq_slcr_unlock(); |
| 147 | |
| 148 | /* Set Level Shifters DT618760 */ |
| 149 | writel(0xF, &slcr_base->lvl_shftr_en); |
| 150 | |
Michal Simek | 7cffeb0 | 2014-03-27 10:06:43 +0100 | [diff] [blame] | 151 | /* Enable AXI interface by de-asserting FPGA resets */ |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 152 | writel(0x0, &slcr_base->fpga_rst_ctrl); |
| 153 | |
| 154 | zynq_slcr_lock(); |
| 155 | } |
| 156 | |
Jagannadha Sutradharudu Teki | 11704c2 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 157 | u32 zynq_slcr_get_boot_mode(void) |
| 158 | { |
| 159 | /* Get the bootmode register value */ |
| 160 | return readl(&slcr_base->boot_mode); |
| 161 | } |
| 162 | |
Michal Simek | 15d654c | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 163 | u32 zynq_slcr_get_idcode(void) |
| 164 | { |
| 165 | return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> |
| 166 | SLCR_IDCODE_SHIFT; |
| 167 | } |
Michal Simek | 8d19162 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 168 | |
| 169 | /* |
| 170 | * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. |
| 171 | * |
| 172 | * @periph: Name of the peripheral |
| 173 | * |
| 174 | * Returns count to indicate the number of pins configured for the |
| 175 | * given @periph. |
| 176 | */ |
| 177 | int zynq_slcr_get_mio_pin_status(const char *periph) |
| 178 | { |
| 179 | const struct zynq_slcr_mio_get_status *mio_ptr; |
Michal Simek | fb6cfdc | 2017-11-10 13:28:07 +0100 | [diff] [blame] | 180 | int val, j; |
Michal Simek | 8d19162 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 181 | int mio = 0; |
Michal Simek | fb6cfdc | 2017-11-10 13:28:07 +0100 | [diff] [blame] | 182 | u32 i; |
Michal Simek | 8d19162 | 2014-04-25 12:21:04 +0200 | [diff] [blame] | 183 | |
| 184 | for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { |
| 185 | if (strcmp(periph, mio_periphs[i].peri_name) == 0) { |
| 186 | mio_ptr = &mio_periphs[i]; |
| 187 | for (j = 0; j < mio_ptr->num_pins; j++) { |
| 188 | val = readl(&slcr_base->mio_pin |
| 189 | [mio_ptr->get_pins[j]]); |
| 190 | if ((val & mio_ptr->mask) == mio_ptr->check_val) |
| 191 | mio++; |
| 192 | } |
| 193 | break; |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | return mio; |
| 198 | } |