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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Paul Kocialkowskic1a3e7e2015-07-15 16:02:25 +02002/*
3 * OMAP4 boot
4 *
5 * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
Paul Kocialkowskic1a3e7e2015-07-15 16:02:25 +02006 */
7
Paul Kocialkowskic1a3e7e2015-07-15 16:02:25 +02008#include <asm/io.h>
9#include <asm/omap_common.h>
Paul Kocialkowskie1660a52016-02-27 19:19:08 +010010#include <asm/arch/sys_proto.h>
Paul Kocialkowskic1a3e7e2015-07-15 16:02:25 +020011#include <spl.h>
12
13static u32 boot_devices[] = {
14 BOOT_DEVICE_MMC2,
15 BOOT_DEVICE_XIP,
16 BOOT_DEVICE_XIPWAIT,
17 BOOT_DEVICE_NAND,
18 BOOT_DEVICE_XIPWAIT,
19 BOOT_DEVICE_MMC1,
20 BOOT_DEVICE_ONENAND,
21 BOOT_DEVICE_ONENAND,
22 BOOT_DEVICE_MMC2,
23 BOOT_DEVICE_ONENAND,
24 BOOT_DEVICE_XIPWAIT,
25 BOOT_DEVICE_NAND,
26 BOOT_DEVICE_NAND,
27 BOOT_DEVICE_MMC1,
28 BOOT_DEVICE_ONENAND,
29 BOOT_DEVICE_MMC2,
30 BOOT_DEVICE_XIP,
31 BOOT_DEVICE_XIPWAIT,
32 BOOT_DEVICE_NAND,
33 BOOT_DEVICE_MMC1,
34 BOOT_DEVICE_MMC1,
35 BOOT_DEVICE_ONENAND,
36 BOOT_DEVICE_MMC2,
37 BOOT_DEVICE_XIP,
38 BOOT_DEVICE_MMC2_2,
39 BOOT_DEVICE_NAND,
40 BOOT_DEVICE_MMC2_2,
41 BOOT_DEVICE_MMC1,
42 BOOT_DEVICE_MMC2_2,
43 BOOT_DEVICE_MMC2_2,
44 BOOT_DEVICE_NONE,
45 BOOT_DEVICE_XIPWAIT,
46};
47
48u32 omap_sys_boot_device(void)
49{
50 u32 sys_boot;
51
52 /* Grab the first 5 bits of the status register for SYS_BOOT. */
53 sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1);
54
55 if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
56 return BOOT_DEVICE_NONE;
57
58 return boot_devices[sys_boot];
59}
Paul Kocialkowski4fa7bb92016-02-27 19:19:07 +010060
61int omap_reboot_mode(char *mode, unsigned int length)
62{
63 unsigned int limit;
64 unsigned int i;
65
66 if (length < 2)
67 return -1;
68
Paul Kocialkowskie1660a52016-02-27 19:19:08 +010069 if (!warm_reset())
70 return -1;
71
Paul Kocialkowski4fa7bb92016-02-27 19:19:07 +010072 limit = (length < OMAP_REBOOT_REASON_SIZE) ? length :
73 OMAP_REBOOT_REASON_SIZE;
74
75 for (i = 0; i < (limit - 1); i++)
76 mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE +
77 OMAP_REBOOT_REASON_OFFSET + i));
78
79 mode[i] = '\0';
80
81 return 0;
82}
83
84int omap_reboot_mode_clear(void)
85{
86 writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET));
87
88 return 0;
89}
90
91int omap_reboot_mode_store(char *mode)
92{
93 unsigned int i;
94
95 for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++)
96 writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE +
97 OMAP_REBOOT_REASON_OFFSET + i));
98
99 writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE +
100 OMAP_REBOOT_REASON_OFFSET + i));
101
102 return 0;
103}