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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
David Brownell45064002009-05-15 23:47:12 +02002/*
3 * Copyright (C) 2004 Texas Instruments.
4 * Copyright (C) 2009 David Brownell
David Brownell45064002009-05-15 23:47:12 +02005 */
6
Tom Rinidec7ea02024-05-20 13:35:03 -06007#include <config.h>
Tom Rini8c70baa2021-12-14 13:36:40 -05008#include <clock_legacy.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
David Brownell45064002009-05-15 23:47:12 +020010#include <asm/arch/hardware.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
Sekhar Nori302fc2f2009-11-12 11:07:22 -050012#include <asm/io.h>
David Brownell45064002009-05-15 23:47:12 +020013
Hadli, Manjunath0dfccbe2012-02-06 00:30:44 +000014DECLARE_GLOBAL_DATA_PTR;
15
David Brownell45064002009-05-15 23:47:12 +020016/* offsets from PLL controller base */
17#define PLLC_PLLCTL 0x100
18#define PLLC_PLLM 0x110
19#define PLLC_PREDIV 0x114
20#define PLLC_PLLDIV1 0x118
21#define PLLC_PLLDIV2 0x11c
22#define PLLC_PLLDIV3 0x120
23#define PLLC_POSTDIV 0x128
24#define PLLC_BPDIV 0x12c
25#define PLLC_PLLDIV4 0x160
26#define PLLC_PLLDIV5 0x164
27#define PLLC_PLLDIV6 0x168
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040028#define PLLC_PLLDIV7 0x16c
David Brownell45064002009-05-15 23:47:12 +020029#define PLLC_PLLDIV8 0x170
30#define PLLC_PLLDIV9 0x174
31
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040032unsigned int sysdiv[9] = {
33 PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
34 PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
Sekhar Nori302fc2f2009-11-12 11:07:22 -050035};
36
37int clk_get(enum davinci_clk_ids id)
38{
39 int pre_div;
40 int pllm;
41 int post_div;
42 int pll_out;
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040043 unsigned int pll_base;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050044
Tom Rini6a5dccc2022-11-16 13:10:41 -050045 pll_out = CFG_SYS_OSCIN_FREQ;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050046
47 if (id == DAVINCI_AUXCLK_CLKID)
48 goto out;
49
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040050 if ((id >> 16) == 1)
51 pll_base = (unsigned int)davinci_pllc1_regs;
52 else
53 pll_base = (unsigned int)davinci_pllc0_regs;
54
55 id &= 0xFFFF;
56
Sekhar Nori302fc2f2009-11-12 11:07:22 -050057 /*
58 * Lets keep this simple. Combining operations can result in
59 * unexpected approximations
60 */
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040061 pre_div = (readl(pll_base + PLLC_PREDIV) &
62 DAVINCI_PLLC_DIV_MASK) + 1;
63 pllm = readl(pll_base + PLLC_PLLM) + 1;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050064
65 pll_out /= pre_div;
66 pll_out *= pllm;
67
68 if (id == DAVINCI_PLLM_CLKID)
69 goto out;
70
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040071 post_div = (readl(pll_base + PLLC_POSTDIV) &
72 DAVINCI_PLLC_DIV_MASK) + 1;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050073
74 pll_out /= post_div;
75
76 if (id == DAVINCI_PLLC_CLKID)
77 goto out;
78
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -040079 pll_out /= (readl(pll_base + sysdiv[id - 1]) &
80 DAVINCI_PLLC_DIV_MASK) + 1;
Sekhar Nori302fc2f2009-11-12 11:07:22 -050081
82out:
83 return pll_out;
84}
Laurence Withersdfd07f62012-07-30 23:30:37 +000085
86int set_cpu_clk_info(void)
87{
88 gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
89 /* DDR PHY uses an x2 input clock */
90 gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
91 (clk_get(DAVINCI_DDR_CLKID) / 1000000);
92 gd->bd->bi_dsp_freq = 0;
93 return 0;
94}
Tom Riniaea2a992021-12-14 13:36:39 -050095
96unsigned long get_board_sys_clk(void)
97{
98 return clk_get(DAVINCI_ARM_CLKID);
99}