| John Rigby | a3f9d65 | 2011-04-19 10:42:40 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2009 |
| 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| John Rigby | a3f9d65 | 2011-04-19 10:42:40 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __U8500_H |
| 8 | #define __U8500_H |
| 9 | |
| 10 | /* |
| 11 | * base register values for U8500 |
| 12 | */ |
| 13 | #define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock |
| 14 | Management Unit */ |
| 15 | #define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */ |
| 16 | #define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ |
| 17 | |
| 18 | /* |
| 19 | * U8500 GPIO register base for 9 banks |
| 20 | */ |
| 21 | #define U8500_GPIO_0_BASE 0x8012E000 |
| 22 | #define U8500_GPIO_1_BASE 0x8012E080 |
| 23 | #define U8500_GPIO_2_BASE 0x8000E000 |
| 24 | #define U8500_GPIO_3_BASE 0x8000E080 |
| 25 | #define U8500_GPIO_4_BASE 0x8000E100 |
| 26 | #define U8500_GPIO_5_BASE 0x8000E180 |
| 27 | #define U8500_GPIO_6_BASE 0x8011E000 |
| 28 | #define U8500_GPIO_7_BASE 0x8011E080 |
| 29 | #define U8500_GPIO_8_BASE 0xA03FE000 |
| 30 | |
| 31 | #endif /* __U8500_H */ |