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git01.mediatek.com / filogic / uboot / a141e5a9511866a86c8396b20cab11a76e353e73 / . / arch / arm / dts / tegra124-venice2.dts
blob: 9de86c014361476b33add11e6da6fe5df1baf7fb [file] [log] [blame]
Tom Warren81f1ec72014-01-24 12:46:17 -0700[diff] [blame]1/dts-v1/;
2
3#include "tegra124.dtsi"
4
5/ {
6 model = "NVIDIA Venice2";
7 compatible = "nvidia,venice2", "nvidia,tegra124";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Tom Warren81f1ec72014-01-24 12:46:17 -0700[diff] [blame]13 aliases {
14 i2c0 = "/i2c@7000d000";
15 i2c1 = "/i2c@7000c000";
16 i2c2 = "/i2c@7000c400";
17 i2c3 = "/i2c@7000c500";
18 i2c4 = "/i2c@7000c700";
19 i2c5 = "/i2c@7000d100";
20 sdhci0 = "/sdhci@700b0600";
21 sdhci1 = "/sdhci@700b0400";
22 spi0 = "/spi@7000d400";
23 spi1 = "/spi@7000da00";
Stephen Warrend79f1582014-05-29 15:29:40 -0600[diff] [blame]24 usb0 = "/usb@7d000000";
25 usb1 = "/usb@7d008000";
Tom Warren81f1ec72014-01-24 12:46:17 -0700[diff] [blame]26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x80000000 0x80000000>;
31 };
32
33 i2c@7000c000 {
34 status = "okay";
35 clock-frequency = <100000>;
36 };
37
38 i2c@7000c400 {
39 status = "okay";
40 clock-frequency = <100000>;
41 };
42
43 i2c@7000c500 {
44 status = "okay";
45 clock-frequency = <100000>;
46 };
47
48 i2c@7000c700 {
49 status = "okay";
50 clock-frequency = <100000>;
51 };
52
53 i2c@7000d000 {
54 status = "okay";
55 clock-frequency = <400000>;
56 };
57
58 i2c@7000d100 {
59 status = "okay";
60 clock-frequency = <400000>;
61 };
62
63 spi@7000d400 {
64 status = "okay";
65 spi-max-frequency = <25000000>;
66 };
67
68 spi@7000da00 {
69 status = "okay";
70 spi-max-frequency = <25000000>;
71 };
72
73 sdhci@700b0400 {
74 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]75 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
76 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
77 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
Tom Warren81f1ec72014-01-24 12:46:17 -0700[diff] [blame]78 bus-width = <4>;
79 };
80
81 sdhci@700b0600 {
82 status = "okay";
83 bus-width = <8>;
84 };
85
Stephen Warrend79f1582014-05-29 15:29:40 -0600[diff] [blame]86 usb@7d000000 {
87 status = "okay";
88 dr_mode = "otg";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]89 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
Stephen Warrend79f1582014-05-29 15:29:40 -0600[diff] [blame]90 };
91
Tom Warren81f1ec72014-01-24 12:46:17 -0700[diff] [blame]92 usb@7d008000 {
93 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]94 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
Tom Warren81f1ec72014-01-24 12:46:17 -0700[diff] [blame]95 };
Simon Glass74c25712016-01-30 16:37:43 -0700[diff] [blame]96
97 clocks {
98 compatible = "simple-bus";
99 #address-cells = <1>;
100 #size-cells = <0>;
101
102 clk32k_in: clock@0 {
103 compatible = "fixed-clock";
104 reg = <0>;
105 #clock-cells = <0>;
106 clock-frequency = <32768>;
107 };
108 };
109
Tom Warren81f1ec72014-01-24 12:46:17 -0700[diff] [blame]110};