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git01.mediatek.com / filogic / uboot / a1398f087a5a782cda9e3f1c3a0c5be592079844 / . / configs / maxbcm_defconfig
blob: ba3631f49eaaf854cb204511d720a91747f98a52 [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_ARM=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]2CONFIG_ARCH_CPU_INIT=y
Stefan Roese383e0c12015-08-25 13:18:38 +0200[diff] [blame]3CONFIG_ARCH_MVEBU=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]4CONFIG_TEXT_BASE=0x00800000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]5CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]6CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=2
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]8CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
9CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]10CONFIG_TARGET_MAXBCM=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]11CONFIG_ENV_SIZE=0x10000
12CONFIG_ENV_OFFSET=0x100000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]13CONFIG_ENV_SECT_SIZE=0x10000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]14CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]15CONFIG_SPL_TEXT_BASE=0x40004030
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]16CONFIG_SPL_SERIAL=y
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]17CONFIG_SPL_STACK=0x4002c000
Tom Rinib9dc6842024-04-22 17:24:09 -0600[diff] [blame]18CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
19CONFIG_SPL_BSS_START_ADDR=0x40020000
20CONFIG_SPL_BSS_MAX_SIZE=0x4000
Tom Rinic427a582024-10-08 09:18:32 -0600[diff] [blame]21CONFIG_SYS_LOAD_ADDR=0x800000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]22CONFIG_SPL=y
Pali Rohár40954732022-05-09 20:17:07 +0200[diff] [blame]23CONFIG_DEBUG_UART_BASE=0xf1012000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]24CONFIG_DEBUG_UART_CLOCK=250000000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]25CONFIG_DEBUG_UART=y
Tom Rinic427a582024-10-08 09:18:32 -0600[diff] [blame]26# CONFIG_EFI_LOADER is not set
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]27CONFIG_BOOTDELAY=3
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]28CONFIG_USE_PREBOOT=y
Simon Glassbd5618d2016-10-17 20:13:00 -0600[diff] [blame]29CONFIG_SYS_CONSOLE_INFO_QUIET=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]30# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]31CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]32CONFIG_SPL_MAX_SIZE=0x1bfd0
Tom Rinie7d67a42022-05-20 12:36:05 -0400[diff] [blame]33CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]34# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]35CONFIG_SPL_I2C=y
Tom Riniba5c2b02022-05-11 16:21:06 -0400[diff] [blame]36CONFIG_SYS_MAXARGS=32
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]37CONFIG_CMD_I2C=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]38CONFIG_CMD_SPI=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]39# CONFIG_CMD_SETEXPR is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]40CONFIG_CMD_DHCP=y
Tom Rinie8f8d672018-04-17 09:22:31 -0400[diff] [blame]41CONFIG_CMD_TFTPPUT=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]42CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]43CONFIG_CMD_PING=y
44CONFIG_CMD_TIME=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]45CONFIG_ENV_OVERWRITE=y
Patrick Delaunayf8e932e2019-02-27 15:20:38 +0100[diff] [blame]46CONFIG_ENV_SPI_MAX_HZ=50000000
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]47CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinia8a77502022-03-11 09:12:01 -0500[diff] [blame]48CONFIG_ARP_TIMEOUT=200
Tom Rini26011a32022-03-11 09:12:02 -0500[diff] [blame]49CONFIG_NET_RETRY_COUNT=50
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]50CONFIG_SPL_OF_TRANSLATE=y
Stefan Roeseffa296c2021-11-18 09:19:34 +0100[diff] [blame]51CONFIG_DM_I2C=y
Tom Rini8825ec42021-08-17 17:59:47 -0400[diff] [blame]52CONFIG_SYS_I2C_MVTWSI=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]53# CONFIG_MMC is not set
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]54CONFIG_SPI_FLASH_MACRONIX=y
55CONFIG_SPI_FLASH_SPANSION=y
56CONFIG_SPI_FLASH_STMICRO=y
Marek Vasute4d70fd2024-05-31 18:47:17 +0200[diff] [blame]57CONFIG_PHY_ANEG_TIMEOUT=8000
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]58CONFIG_PHY_MARVELL=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]59CONFIG_PHY_GIGE=y
Chris Packham919041c2017-08-21 20:17:03 +1200[diff] [blame]60CONFIG_MVNETA=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]61CONFIG_MII=y
Marek Behún99e296f2022-04-27 12:41:46 +0200[diff] [blame]62CONFIG_MVMDIO=y
Pali Rohár40954732022-05-09 20:17:07 +0200[diff] [blame]63CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
Stefan Roese83097cf2015-11-25 07:37:00 +0100[diff] [blame]64CONFIG_DEBUG_UART_SHIFT=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]65CONFIG_SYS_NS16550=y
Tuomas Tynkkynen13b5cb82018-02-07 02:42:22 +0200[diff] [blame]66CONFIG_KIRKWOOD_SPI=y