Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a1295440916642b449de5a4ea9f1d6ffc1d1c1aa / . / cpu / mcf52x2 / start.S
blob: b4926e2376b51274faeae4ee7f533f121400f264 [file] [log] [blame]
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include "version.h"
26
27#ifndef CONFIG_IDENT_STRING
28#define CONFIG_IDENT_STRING ""
29#endif
30
31
32#define _START _start
33#define _FAULT _fault
34
35
36#define SAVE_ALL \
37 move.w #0x2700,%sr; /* disable intrs */ \
38 subl #60,%sp; /* space for 15 regs */ \
39 moveml %d0-%d7/%a0-%a6,%sp@; \
40
41#define RESTORE_ALL \
42 moveml %sp@,%d0-%d7/%a0-%a6; \
43 addl #60,%sp; /* space for 15 regs */ \
44 rte
45
46/* If we come from a pre-loader we don't need an initial exception
47 * table.
48 */
49#if !defined(CONFIG_MONITOR_IS_IN_RAM)
50
51.text
52/*
53 * Vector table. This is used for initial platform startup.
54 * These vectors are to catch any un-intended traps.
55 */
56_vectors:
57
58.long 0x00000000, _START
59.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
61.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
62.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94
95#endif
96
97 .text
98
99 .globl _start
100_start:
101 nop
102 nop
103 move.w #0x2700,%sr
104
105 /* if we come from a pre-loader we have no exception table and
106 * therefore no VBR to set
107 */
108#if !defined(CONFIG_MONITOR_IS_IN_RAM)
109 move.l #CFG_FLASH_BASE, %d0
110 movec %d0, %VBR
111#endif
112
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]113#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]114 move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
115 move.c %d0, %MBAR
116
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]117 /*** The 5249 has MBAR2 as well ***/
118#ifdef CFG_MBAR2
119 move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
120 movec %d0, #0xc0e /* Set MBAR2 */
121#endif
122
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]123 move.l #(CFG_INIT_RAM_ADDR + 1), %d0
124 movec %d0, %RAMBAR0
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]125#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]126
127#ifdef CONFIG_M5282
128 /* Initialize IPSBAR */
129 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
130 move.l %d0, 0x40000000
131
132 /* Initialize FLASHBAR: locate internal Flash and validate it */
133 move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
134 movec %d0, %RAMBAR0
135
136 /* Initialize RAMBAR1: locate SRAM and validate it */
137 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
138 movec %d0, %RAMBAR1
139#endif
140
141 /* invalidate and disable cache */
142 move.l #0x01000000, %d0 /* Invalidate cache cmd */
143 movec %d0, %CACR /* Invalidate cache */
144 move.l #0, %d0
145 movec %d0, %ACR0
146 movec %d0, %ACR1
147
148 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
149 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
150 clr.l %sp@-
151
152 move.l #__got_start, %a5 /* put relocation table address to a5 */
153
154 bsr cpu_init_f /* run low-level CPU init code (from flash) */
155 bsr board_init_f /* run low-level board init code (from flash) */
156
157 /* board_init_f() does not return
158
159/*------------------------------------------------------------------------------*/
160
161/*
162 * void relocate_code (addr_sp, gd, addr_moni)
163 *
164 * This "function" does not return, instead it continues in RAM
165 * after relocating the monitor code.
166 *
167 * r3 = dest
168 * r4 = src
169 * r5 = length in bytes
170 * r6 = cachelinesize
171 */
172 .globl relocate_code
173relocate_code:
174 link.w %a6,#0
175 move.l 8(%a6), %sp /* set new stack pointer */
176
177 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
178 move.l 16(%a6), %a0 /* Save copy of Destination Address */
179
180 move.l #CFG_MONITOR_BASE, %a1
181 move.l #__init_end, %a2
182 move.l %a0, %a3
183
184 /* copy the code to RAM */
1851:
186 move.l (%a1)+, (%a3)+
187 cmp.l %a1,%a2
188 bgt.s 1b
189
190/*
191 * We are done. Do not return, instead branch to second part of board
192 * initialization, now running from RAM.
193 */
194 move.l %a0, %a1
195 add.l #(in_ram - CFG_MONITOR_BASE), %a1
196 jmp (%a1)
197
198in_ram:
199
200clear_bss:
201 /*
202 * Now clear BSS segment
203 */
204 move.l %a0, %a1
205 add.l #(_sbss - CFG_MONITOR_BASE),%a1
206 move.l %a0, %d1
207 add.l #(_ebss - CFG_MONITOR_BASE),%d1
2086:
209 clr.l (%a1)+
210 cmp.l %a1,%d1
211 bgt.s 6b
212
213 /*
214 * fix got table in RAM
215 */
216 move.l %a0, %a1
217 add.l #(__got_start - CFG_MONITOR_BASE),%a1
218 move.l %a1,%a5 /* * fix got pointer register a5 */
219
220 move.l %a0, %a2
221 add.l #(__got_end - CFG_MONITOR_BASE),%a2
222
2237:
224 move.l (%a1),%d1
225 sub.l #_start,%d1
226 add.l %a0,%d1
227 move.l %d1,(%a1)+
228 cmp.l %a2, %a1
229 bne 7b
230
231 /* calculate relative jump to board_init_r in ram */
232 move.l %a0, %a1
233 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
234
235 /* set parameters for board_init_r */
236 move.l %a0,-(%sp) /* dest_addr */
237 move.l %d0,-(%sp) /* gd */
238 jsr (%a1)
239
240/*------------------------------------------------------------------------------*/
241/* exception code */
242 .globl _fault
243_fault:
244 jmp _fault
245
246 .globl _exc_handler
247_exc_handler:
248 SAVE_ALL
249 movel %sp,%sp@-
250 bsr exc_handler
251 addql #4,%sp
252 RESTORE_ALL
253
254 .globl _int_handler
255_int_handler:
256 SAVE_ALL
257 movel %sp,%sp@-
258 bsr int_handler
259 addql #4,%sp
260 RESTORE_ALL
261
262/*------------------------------------------------------------------------------*/
263/* cache functions */
264#ifdef CONFIG_M5272
265 .globl icache_enable
266icache_enable:
267 move.l #0x01000000, %d0 /* Invalidate cache cmd */
268 movec %d0, %CACR /* Invalidate cache */
269 move.l #0x0000c000, %d0 /* Setup cache mask */
270 movec %d0, %ACR0 /* Enable cache */
271 move.l #0xff00c000, %d0 /* Setup cache mask */
272 movec %d0, %ACR1 /* Enable cache */
273 move.l #0x80000100, %d0 /* Setup cache mask */
274 movec %d0, %CACR /* Enable cache */
275 moveq #1, %d0
276 move.l %d0, icache_state
277 rts
278#endif
279
280#ifdef CONFIG_M5282
281 .globl icache_enable
282icache_enable:
283 move.l #0x01000000, %d0 /* Invalidate cache cmd */
284 movec %d0, %CACR /* Invalidate cache */
285 move.l #0x0000c000, %d0 /* Setup cache mask */
286 movec %d0, %ACR0 /* Enable cache */
287 move.l #0xff00c000, %d0 /* Setup cache mask */
288 movec %d0, %ACR1 /* Enable cache */
289 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
290 movec %d0, %CACR /* Enable cache */
291 moveq #1, %d0
292 move.l %d0, icache_state
293 rts
294#endif
295
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]296#ifdef CONFIG_M5249
297 .globl icache_enable
298icache_enable:
299 /*
300 * Note: The 5249 Documentation doesn't give a bit position for CINV!
301 * From the 5272 and the 5307 documentation, I have deduced that it is
302 * probably CACR[24]. Should someone say something to Motorola?
303 * ~Jeremy
304 */
305 move.l #0x01000000, %d0 /* Invalidate whole cache */
306 move.c %d0,%CACR
307 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
308 move.c %d0, %ACR0
309 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
310 move.c %d0, %ACR1
311 move.l #0x90000200, %d0 /* Set cache enable cmd */
312 move.c %d0,%CACR
313 moveq #1, %d0
314 move.l %d0, icache_state
315 rts
316#endif
317
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]318 .globl icache_disable
319icache_disable:
320 move.l #0x00000100, %d0 /* Setup cache mask */
321 movec %d0, %CACR /* Enable cache */
322 clr.l %d0 /* Setup cache mask */
323 movec %d0, %ACR0 /* Enable cache */
324 movec %d0, %ACR1 /* Enable cache */
325 moveq #0, %d0
326 move.l %d0, icache_state
327 rts
328
329 .globl icache_status
330icache_status:
331 move.l icache_state, %d0
332 rts
333
334 .data
335icache_state:
336 .long 1
337
stroese53395a22004-12-16 18:09:49 +0000[diff] [blame]338
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]339/*------------------------------------------------------------------------------*/
340
341 .globl version_string
342version_string:
343 .ascii U_BOOT_VERSION
344 .ascii " (", __DATE__, " - ", __TIME__, ")"
345 .ascii CONFIG_IDENT_STRING, "\0"