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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Kumar Gala124b0822008-08-26 15:01:29 -05002/*
York Sun6db4fdd2018-01-29 09:44:35 -08003 * Copyright 2008-2016 Freescale Semiconductor, Inc.
Maninder Singhe8fee9a2021-10-10 09:12:16 -07004 * Copyright 2017-2021 NXP Semiconductor
Kumar Gala124b0822008-08-26 15:01:29 -05005 */
6
7#include <common.h>
York Sunf0626592013-09-30 09:22:09 -07008#include <fsl_ddr_sdram.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060010#include <asm/bitops.h>
Kumar Gala124b0822008-08-26 15:01:29 -050011
York Sunf0626592013-09-30 09:22:09 -070012#include <fsl_ddr.h>
Kumar Gala124b0822008-08-26 15:01:29 -050013
York Sun2896cb72014-03-27 17:54:47 -070014#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Kim Phillips82f576f2012-10-29 13:34:37 +000015static unsigned int
York Sun2c0b62d2015-01-06 13:18:50 -080016compute_cas_latency(const unsigned int ctrl_num,
17 const dimm_params_t *dimm_params,
York Sun2896cb72014-03-27 17:54:47 -070018 common_timing_params_t *outpdimm,
19 unsigned int number_of_dimms)
Dave Liu4be87b22009-03-14 12:48:30 +080020{
21 unsigned int i;
Dave Liu4be87b22009-03-14 12:48:30 +080022 unsigned int common_caslat;
23 unsigned int caslat_actual;
24 unsigned int retry = 16;
York Sunfc63b282015-03-19 09:30:27 -070025 unsigned int tmp = ~0;
Maninder Singhe8fee9a2021-10-10 09:12:16 -070026 unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
York Sun2896cb72014-03-27 17:54:47 -070027#ifdef CONFIG_SYS_FSL_DDR3
28 const unsigned int taamax = 20000;
29#else
30 const unsigned int taamax = 18000;
31#endif
Dave Liu4be87b22009-03-14 12:48:30 +080032
33 /* compute the common CAS latency supported between slots */
York Sunfc63b282015-03-19 09:30:27 -070034 for (i = 0; i < number_of_dimms; i++) {
York Sunfa3ede52012-08-17 08:22:41 +000035 if (dimm_params[i].n_ranks)
Priyanka Jain4a717412013-09-25 10:41:19 +053036 tmp &= dimm_params[i].caslat_x;
York Sunfa3ede52012-08-17 08:22:41 +000037 }
Dave Liu4be87b22009-03-14 12:48:30 +080038 common_caslat = tmp;
39
Maninder Singhe8fee9a2021-10-10 09:12:16 -070040 if (!mclk_ps) {
41 printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n",
42 outpdimm->tckmin_x_ps);
43 mclk_ps = outpdimm->tckmin_x_ps;
44 }
45
Dave Liu4be87b22009-03-14 12:48:30 +080046 /* validate if the memory clk is in the range of dimms */
York Sun2896cb72014-03-27 17:54:47 -070047 if (mclk_ps < outpdimm->tckmin_x_ps) {
York Sunc04da042011-05-06 07:14:14 +080048 printf("DDR clock (MCLK cycle %u ps) is faster than "
49 "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
York Sun2896cb72014-03-27 17:54:47 -070050 mclk_ps, outpdimm->tckmin_x_ps);
Dave Liu4be87b22009-03-14 12:48:30 +080051 }
York Sun2896cb72014-03-27 17:54:47 -070052#ifdef CONFIG_SYS_FSL_DDR4
53 if (mclk_ps > outpdimm->tckmax_ps) {
54 printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n",
55 mclk_ps, outpdimm->tckmax_ps);
56 }
57#endif
Dave Liu4be87b22009-03-14 12:48:30 +080058 /* determine the acutal cas latency */
York Sun2896cb72014-03-27 17:54:47 -070059 caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps;
Dave Liu4be87b22009-03-14 12:48:30 +080060 /* check if the dimms support the CAS latency */
61 while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
62 caslat_actual++;
63 retry--;
64 }
65 /* once the caculation of caslat_actual is completed
66 * we must verify that this CAS latency value does not
York Sun2896cb72014-03-27 17:54:47 -070067 * exceed tAAmax, which is 20 ns for all DDR3 speed grades,
68 * 18ns for all DDR4 speed grades.
Dave Liu4be87b22009-03-14 12:48:30 +080069 */
York Sun2896cb72014-03-27 17:54:47 -070070 if (caslat_actual * mclk_ps > taamax) {
Alexander Merkle0137e602016-03-17 15:44:47 +010071 printf("The chosen cas latency %d is too large\n",
72 caslat_actual);
Dave Liu4be87b22009-03-14 12:48:30 +080073 }
York Sun2896cb72014-03-27 17:54:47 -070074 outpdimm->lowest_common_spd_caslat = caslat_actual;
75 debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual);
Dave Liu4be87b22009-03-14 12:48:30 +080076
77 return 0;
78}
York Sun2896cb72014-03-27 17:54:47 -070079#else /* for DDR1 and DDR2 */
80static unsigned int
York Sun2c0b62d2015-01-06 13:18:50 -080081compute_cas_latency(const unsigned int ctrl_num,
82 const dimm_params_t *dimm_params,
York Sun2896cb72014-03-27 17:54:47 -070083 common_timing_params_t *outpdimm,
84 unsigned int number_of_dimms)
85{
86 int i;
York Sun2c0b62d2015-01-06 13:18:50 -080087 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
York Sun2896cb72014-03-27 17:54:47 -070088 unsigned int lowest_good_caslat;
89 unsigned int not_ok;
90 unsigned int temp1, temp2;
91
92 debug("using mclk_ps = %u\n", mclk_ps);
93 if (mclk_ps > outpdimm->tckmax_ps) {
94 printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n",
95 mclk_ps, outpdimm->tckmax_ps);
96 }
97
98 /*
99 * Compute a CAS latency suitable for all DIMMs
100 *
101 * Strategy for SPD-defined latencies: compute only
102 * CAS latency defined by all DIMMs.
103 */
104
105 /*
106 * Step 1: find CAS latency common to all DIMMs using bitwise
107 * operation.
108 */
109 temp1 = 0xFF;
110 for (i = 0; i < number_of_dimms; i++) {
111 if (dimm_params[i].n_ranks) {
112 temp2 = 0;
113 temp2 |= 1 << dimm_params[i].caslat_x;
114 temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
115 temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
116 /*
117 * If there was no entry for X-2 (X-1) in
118 * the SPD, then caslat_x_minus_2
119 * (caslat_x_minus_1) contains either 255 or
120 * 0xFFFFFFFF because that's what the glorious
121 * __ilog2 function returns for an input of 0.
122 * On 32-bit PowerPC, left shift counts with bit
123 * 26 set (that the value of 255 or 0xFFFFFFFF
124 * will have), cause the destination register to
125 * be 0. That is why this works.
126 */
127 temp1 &= temp2;
128 }
129 }
130
131 /*
132 * Step 2: check each common CAS latency against tCK of each
133 * DIMM's SPD.
134 */
135 lowest_good_caslat = 0;
136 temp2 = 0;
137 while (temp1) {
138 not_ok = 0;
139 temp2 = __ilog2(temp1);
140 debug("checking common caslat = %u\n", temp2);
141
142 /* Check if this CAS latency will work on all DIMMs at tCK. */
143 for (i = 0; i < number_of_dimms; i++) {
144 if (!dimm_params[i].n_ranks)
145 continue;
146
147 if (dimm_params[i].caslat_x == temp2) {
148 if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
149 debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n",
150 temp2, i, mclk_ps,
151 dimm_params[i].tckmin_x_ps);
152 continue;
153 } else {
154 not_ok++;
155 }
156 }
157
158 if (dimm_params[i].caslat_x_minus_1 == temp2) {
159 unsigned int tckmin_x_minus_1_ps
160 = dimm_params[i].tckmin_x_minus_1_ps;
161 if (mclk_ps >= tckmin_x_minus_1_ps) {
162 debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n",
163 temp2, i, mclk_ps,
164 tckmin_x_minus_1_ps);
165 continue;
166 } else {
167 not_ok++;
168 }
169 }
170
171 if (dimm_params[i].caslat_x_minus_2 == temp2) {
172 unsigned int tckmin_x_minus_2_ps
173 = dimm_params[i].tckmin_x_minus_2_ps;
174 if (mclk_ps >= tckmin_x_minus_2_ps) {
175 debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n",
176 temp2, i, mclk_ps,
177 tckmin_x_minus_2_ps);
178 continue;
179 } else {
180 not_ok++;
181 }
182 }
183 }
184
185 if (!not_ok)
186 lowest_good_caslat = temp2;
187
188 temp1 &= ~(1 << temp2);
189 }
190
191 debug("lowest common SPD-defined CAS latency = %u\n",
192 lowest_good_caslat);
193 outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
194
195
196 /*
197 * Compute a common 'de-rated' CAS latency.
198 *
199 * The strategy here is to find the *highest* dereated cas latency
200 * with the assumption that all of the DIMMs will support a dereated
201 * CAS latency higher than or equal to their lowest dereated value.
202 */
203 temp1 = 0;
204 for (i = 0; i < number_of_dimms; i++)
205 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
206
207 outpdimm->highest_common_derated_caslat = temp1;
208 debug("highest common dereated CAS latency = %u\n", temp1);
209
210 return 0;
211}
Kim Phillips82f576f2012-10-29 13:34:37 +0000212#endif
Dave Liu4be87b22009-03-14 12:48:30 +0800213
Kumar Gala124b0822008-08-26 15:01:29 -0500214/*
215 * compute_lowest_common_dimm_parameters()
216 *
217 * Determine the worst-case DIMM timing parameters from the set of DIMMs
218 * whose parameters have been computed into the array pointed to
219 * by dimm_params.
220 */
221unsigned int
York Sun2c0b62d2015-01-06 13:18:50 -0800222compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
223 const dimm_params_t *dimm_params,
Kumar Gala124b0822008-08-26 15:01:29 -0500224 common_timing_params_t *outpdimm,
York Sun98df4d12012-10-08 07:44:23 +0000225 const unsigned int number_of_dimms)
Kumar Gala124b0822008-08-26 15:01:29 -0500226{
yorkde879322010-07-02 22:25:55 +0000227 unsigned int i, j;
Kumar Gala124b0822008-08-26 15:01:29 -0500228
Priyanka Jain4a717412013-09-25 10:41:19 +0530229 unsigned int tckmin_x_ps = 0;
230 unsigned int tckmax_ps = 0xFFFFFFFF;
Priyanka Jain4a717412013-09-25 10:41:19 +0530231 unsigned int trcd_ps = 0;
232 unsigned int trp_ps = 0;
233 unsigned int tras_ps = 0;
York Sun2896cb72014-03-27 17:54:47 -0700234#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
235 unsigned int taamin_ps = 0;
236#endif
237#ifdef CONFIG_SYS_FSL_DDR4
238 unsigned int twr_ps = 15000;
239 unsigned int trfc1_ps = 0;
240 unsigned int trfc2_ps = 0;
241 unsigned int trfc4_ps = 0;
242 unsigned int trrds_ps = 0;
243 unsigned int trrdl_ps = 0;
244 unsigned int tccdl_ps = 0;
York Sun6db4fdd2018-01-29 09:44:35 -0800245 unsigned int trfc_slr_ps = 0;
York Sun2896cb72014-03-27 17:54:47 -0700246#else
Priyanka Jain4a717412013-09-25 10:41:19 +0530247 unsigned int twr_ps = 0;
248 unsigned int twtr_ps = 0;
249 unsigned int trfc_ps = 0;
250 unsigned int trrd_ps = 0;
York Sun2896cb72014-03-27 17:54:47 -0700251 unsigned int trtp_ps = 0;
252#endif
Priyanka Jain4a717412013-09-25 10:41:19 +0530253 unsigned int trc_ps = 0;
Kumar Gala124b0822008-08-26 15:01:29 -0500254 unsigned int refresh_rate_ps = 0;
Valentin Longchamp0b810932013-10-18 11:47:20 +0200255 unsigned int extended_op_srt = 1;
York Sun2896cb72014-03-27 17:54:47 -0700256#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
Priyanka Jain4a717412013-09-25 10:41:19 +0530257 unsigned int tis_ps = 0;
258 unsigned int tih_ps = 0;
259 unsigned int tds_ps = 0;
260 unsigned int tdh_ps = 0;
Priyanka Jain4a717412013-09-25 10:41:19 +0530261 unsigned int tdqsq_max_ps = 0;
262 unsigned int tqhs_ps = 0;
York Sun2896cb72014-03-27 17:54:47 -0700263#endif
York Sund56624f2011-01-10 12:02:56 +0000264 unsigned int temp1, temp2;
Kumar Gala124b0822008-08-26 15:01:29 -0500265 unsigned int additive_latency = 0;
Kumar Gala124b0822008-08-26 15:01:29 -0500266
267 temp1 = 0;
268 for (i = 0; i < number_of_dimms; i++) {
269 /*
270 * If there are no ranks on this DIMM,
271 * it probably doesn't exist, so skip it.
272 */
273 if (dimm_params[i].n_ranks == 0) {
274 temp1++;
275 continue;
276 }
yorkf4f93c62010-07-02 22:25:53 +0000277 if (dimm_params[i].n_ranks == 4 && i != 0) {
278 printf("Found Quad-rank DIMM in wrong bank, ignored."
279 " Software may not run as expected.\n");
280 temp1++;
281 continue;
282 }
York Sun98df4d12012-10-08 07:44:23 +0000283
284 /*
285 * check if quad-rank DIMM is plugged if
286 * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
287 * Only the board with proper design is capable
288 */
289#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
yorkf4f93c62010-07-02 22:25:53 +0000290 if (dimm_params[i].n_ranks == 4 && \
291 CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
292 printf("Found Quad-rank DIMM, not able to support.");
293 temp1++;
294 continue;
295 }
York Sun98df4d12012-10-08 07:44:23 +0000296#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500297 /*
Priyanka Jain4a717412013-09-25 10:41:19 +0530298 * Find minimum tckmax_ps to find fastest slow speed,
Kumar Gala124b0822008-08-26 15:01:29 -0500299 * i.e., this is the slowest the whole system can go.
300 */
Masahiro Yamadadb204642014-11-07 03:03:31 +0900301 tckmax_ps = min(tckmax_ps,
302 (unsigned int)dimm_params[i].tckmax_ps);
York Sun2896cb72014-03-27 17:54:47 -0700303#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Masahiro Yamadadb204642014-11-07 03:03:31 +0900304 taamin_ps = max(taamin_ps,
305 (unsigned int)dimm_params[i].taa_ps);
York Sun2896cb72014-03-27 17:54:47 -0700306#endif
Masahiro Yamadadb204642014-11-07 03:03:31 +0900307 tckmin_x_ps = max(tckmin_x_ps,
308 (unsigned int)dimm_params[i].tckmin_x_ps);
309 trcd_ps = max(trcd_ps, (unsigned int)dimm_params[i].trcd_ps);
310 trp_ps = max(trp_ps, (unsigned int)dimm_params[i].trp_ps);
311 tras_ps = max(tras_ps, (unsigned int)dimm_params[i].tras_ps);
York Sun2896cb72014-03-27 17:54:47 -0700312#ifdef CONFIG_SYS_FSL_DDR4
Masahiro Yamadadb204642014-11-07 03:03:31 +0900313 trfc1_ps = max(trfc1_ps,
314 (unsigned int)dimm_params[i].trfc1_ps);
315 trfc2_ps = max(trfc2_ps,
316 (unsigned int)dimm_params[i].trfc2_ps);
317 trfc4_ps = max(trfc4_ps,
318 (unsigned int)dimm_params[i].trfc4_ps);
319 trrds_ps = max(trrds_ps,
320 (unsigned int)dimm_params[i].trrds_ps);
321 trrdl_ps = max(trrdl_ps,
322 (unsigned int)dimm_params[i].trrdl_ps);
323 tccdl_ps = max(tccdl_ps,
324 (unsigned int)dimm_params[i].tccdl_ps);
York Sun6db4fdd2018-01-29 09:44:35 -0800325 trfc_slr_ps = max(trfc_slr_ps,
326 (unsigned int)dimm_params[i].trfc_slr_ps);
York Sun2896cb72014-03-27 17:54:47 -0700327#else
Masahiro Yamadadb204642014-11-07 03:03:31 +0900328 twr_ps = max(twr_ps, (unsigned int)dimm_params[i].twr_ps);
329 twtr_ps = max(twtr_ps, (unsigned int)dimm_params[i].twtr_ps);
330 trfc_ps = max(trfc_ps, (unsigned int)dimm_params[i].trfc_ps);
331 trrd_ps = max(trrd_ps, (unsigned int)dimm_params[i].trrd_ps);
332 trtp_ps = max(trtp_ps, (unsigned int)dimm_params[i].trtp_ps);
York Sun2896cb72014-03-27 17:54:47 -0700333#endif
Masahiro Yamadadb204642014-11-07 03:03:31 +0900334 trc_ps = max(trc_ps, (unsigned int)dimm_params[i].trc_ps);
York Sun2896cb72014-03-27 17:54:47 -0700335#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
Masahiro Yamadadb204642014-11-07 03:03:31 +0900336 tis_ps = max(tis_ps, (unsigned int)dimm_params[i].tis_ps);
337 tih_ps = max(tih_ps, (unsigned int)dimm_params[i].tih_ps);
338 tds_ps = max(tds_ps, (unsigned int)dimm_params[i].tds_ps);
339 tdh_ps = max(tdh_ps, (unsigned int)dimm_params[i].tdh_ps);
340 tqhs_ps = max(tqhs_ps, (unsigned int)dimm_params[i].tqhs_ps);
Kumar Gala124b0822008-08-26 15:01:29 -0500341 /*
Priyanka Jain4a717412013-09-25 10:41:19 +0530342 * Find maximum tdqsq_max_ps to find slowest.
Kumar Gala124b0822008-08-26 15:01:29 -0500343 *
344 * FIXME: is finding the slowest value the correct
345 * strategy for this parameter?
346 */
Masahiro Yamadadb204642014-11-07 03:03:31 +0900347 tdqsq_max_ps = max(tdqsq_max_ps,
348 (unsigned int)dimm_params[i].tdqsq_max_ps);
York Sun2896cb72014-03-27 17:54:47 -0700349#endif
350 refresh_rate_ps = max(refresh_rate_ps,
Masahiro Yamadadb204642014-11-07 03:03:31 +0900351 (unsigned int)dimm_params[i].refresh_rate_ps);
York Sun2896cb72014-03-27 17:54:47 -0700352 /* extended_op_srt is either 0 or 1, 0 having priority */
353 extended_op_srt = min(extended_op_srt,
Masahiro Yamadadb204642014-11-07 03:03:31 +0900354 (unsigned int)dimm_params[i].extended_op_srt);
Kumar Gala124b0822008-08-26 15:01:29 -0500355 }
356
357 outpdimm->ndimms_present = number_of_dimms - temp1;
358
359 if (temp1 == number_of_dimms) {
360 debug("no dimms this memory controller\n");
361 return 0;
362 }
363
Priyanka Jain4a717412013-09-25 10:41:19 +0530364 outpdimm->tckmin_x_ps = tckmin_x_ps;
365 outpdimm->tckmax_ps = tckmax_ps;
York Sun2896cb72014-03-27 17:54:47 -0700366#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
367 outpdimm->taamin_ps = taamin_ps;
368#endif
Priyanka Jain4a717412013-09-25 10:41:19 +0530369 outpdimm->trcd_ps = trcd_ps;
370 outpdimm->trp_ps = trp_ps;
371 outpdimm->tras_ps = tras_ps;
York Sun2896cb72014-03-27 17:54:47 -0700372#ifdef CONFIG_SYS_FSL_DDR4
373 outpdimm->trfc1_ps = trfc1_ps;
374 outpdimm->trfc2_ps = trfc2_ps;
375 outpdimm->trfc4_ps = trfc4_ps;
376 outpdimm->trrds_ps = trrds_ps;
377 outpdimm->trrdl_ps = trrdl_ps;
378 outpdimm->tccdl_ps = tccdl_ps;
York Sun6db4fdd2018-01-29 09:44:35 -0800379 outpdimm->trfc_slr_ps = trfc_slr_ps;
York Sun2896cb72014-03-27 17:54:47 -0700380#else
Priyanka Jain4a717412013-09-25 10:41:19 +0530381 outpdimm->twtr_ps = twtr_ps;
382 outpdimm->trfc_ps = trfc_ps;
383 outpdimm->trrd_ps = trrd_ps;
York Sun2896cb72014-03-27 17:54:47 -0700384 outpdimm->trtp_ps = trtp_ps;
385#endif
386 outpdimm->twr_ps = twr_ps;
Priyanka Jain4a717412013-09-25 10:41:19 +0530387 outpdimm->trc_ps = trc_ps;
Kumar Gala124b0822008-08-26 15:01:29 -0500388 outpdimm->refresh_rate_ps = refresh_rate_ps;
Valentin Longchamp0b810932013-10-18 11:47:20 +0200389 outpdimm->extended_op_srt = extended_op_srt;
York Sun2896cb72014-03-27 17:54:47 -0700390#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
Priyanka Jain4a717412013-09-25 10:41:19 +0530391 outpdimm->tis_ps = tis_ps;
392 outpdimm->tih_ps = tih_ps;
393 outpdimm->tds_ps = tds_ps;
394 outpdimm->tdh_ps = tdh_ps;
Priyanka Jain4a717412013-09-25 10:41:19 +0530395 outpdimm->tdqsq_max_ps = tdqsq_max_ps;
396 outpdimm->tqhs_ps = tqhs_ps;
York Sun2896cb72014-03-27 17:54:47 -0700397#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500398
399 /* Determine common burst length for all DIMMs. */
400 temp1 = 0xff;
401 for (i = 0; i < number_of_dimms; i++) {
402 if (dimm_params[i].n_ranks) {
403 temp1 &= dimm_params[i].burst_lengths_bitmask;
404 }
405 }
Priyanka Jain4a717412013-09-25 10:41:19 +0530406 outpdimm->all_dimms_burst_lengths_bitmask = temp1;
Kumar Gala124b0822008-08-26 15:01:29 -0500407
408 /* Determine if all DIMMs registered buffered. */
409 temp1 = temp2 = 0;
410 for (i = 0; i < number_of_dimms; i++) {
411 if (dimm_params[i].n_ranks) {
York Sunb06fcb52011-02-04 13:58:00 -0800412 if (dimm_params[i].registered_dimm) {
Kumar Gala124b0822008-08-26 15:01:29 -0500413 temp1 = 1;
Ying Zhang9ff70262013-08-16 15:16:11 +0800414#ifndef CONFIG_SPL_BUILD
York Sunb06fcb52011-02-04 13:58:00 -0800415 printf("Detected RDIMM %s\n",
416 dimm_params[i].mpart);
Ying Zhang9ff70262013-08-16 15:16:11 +0800417#endif
York Sunb06fcb52011-02-04 13:58:00 -0800418 } else {
Kumar Gala124b0822008-08-26 15:01:29 -0500419 temp2 = 1;
Ying Zhang9ff70262013-08-16 15:16:11 +0800420#ifndef CONFIG_SPL_BUILD
York Sunb06fcb52011-02-04 13:58:00 -0800421 printf("Detected UDIMM %s\n",
422 dimm_params[i].mpart);
Ying Zhang9ff70262013-08-16 15:16:11 +0800423#endif
York Sunb06fcb52011-02-04 13:58:00 -0800424 }
Kumar Gala124b0822008-08-26 15:01:29 -0500425 }
426 }
427
Priyanka Jain4a717412013-09-25 10:41:19 +0530428 outpdimm->all_dimms_registered = 0;
429 outpdimm->all_dimms_unbuffered = 0;
Kumar Gala124b0822008-08-26 15:01:29 -0500430 if (temp1 && !temp2) {
Priyanka Jain4a717412013-09-25 10:41:19 +0530431 outpdimm->all_dimms_registered = 1;
York Sund56624f2011-01-10 12:02:56 +0000432 } else if (!temp1 && temp2) {
Priyanka Jain4a717412013-09-25 10:41:19 +0530433 outpdimm->all_dimms_unbuffered = 1;
York Sund56624f2011-01-10 12:02:56 +0000434 } else {
Kumar Gala124b0822008-08-26 15:01:29 -0500435 printf("ERROR: Mix of registered buffered and unbuffered "
436 "DIMMs detected!\n");
437 }
438
yorkde879322010-07-02 22:25:55 +0000439 temp1 = 0;
Priyanka Jain4a717412013-09-25 10:41:19 +0530440 if (outpdimm->all_dimms_registered)
yorkde879322010-07-02 22:25:55 +0000441 for (j = 0; j < 16; j++) {
442 outpdimm->rcw[j] = dimm_params[0].rcw[j];
York Sun98df4d12012-10-08 07:44:23 +0000443 for (i = 1; i < number_of_dimms; i++) {
444 if (!dimm_params[i].n_ranks)
445 continue;
yorkde879322010-07-02 22:25:55 +0000446 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
York Sund56624f2011-01-10 12:02:56 +0000447 temp1 = 1;
yorkde879322010-07-02 22:25:55 +0000448 break;
449 }
York Sun98df4d12012-10-08 07:44:23 +0000450 }
yorkde879322010-07-02 22:25:55 +0000451 }
452
453 if (temp1 != 0)
454 printf("ERROR: Mix different RDIMM detected!\n");
455
York Sun2896cb72014-03-27 17:54:47 -0700456 /* calculate cas latency for all DDR types */
York Sun2c0b62d2015-01-06 13:18:50 -0800457 if (compute_cas_latency(ctrl_num, dimm_params,
458 outpdimm, number_of_dimms))
Dave Liu4be87b22009-03-14 12:48:30 +0800459 return 1;
Kumar Gala124b0822008-08-26 15:01:29 -0500460
461 /* Determine if all DIMMs ECC capable. */
462 temp1 = 1;
463 for (i = 0; i < number_of_dimms; i++) {
York Sunfbe65952011-03-17 11:18:10 -0700464 if (dimm_params[i].n_ranks &&
465 !(dimm_params[i].edc_config & EDC_ECC)) {
Kumar Gala124b0822008-08-26 15:01:29 -0500466 temp1 = 0;
467 break;
468 }
469 }
470 if (temp1) {
471 debug("all DIMMs ECC capable\n");
472 } else {
473 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
474 }
Priyanka Jain4a717412013-09-25 10:41:19 +0530475 outpdimm->all_dimms_ecc_capable = temp1;
Kumar Gala124b0822008-08-26 15:01:29 -0500476
Kumar Gala124b0822008-08-26 15:01:29 -0500477 /*
478 * Compute additive latency.
479 *
480 * For DDR1, additive latency should be 0.
481 *
482 * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
483 * which comes from Trcd, and also note that:
484 * add_lat + caslat must be >= 4
485 *
Dave Liu4be87b22009-03-14 12:48:30 +0800486 * For DDR3, we use the AL=0
Kumar Gala124b0822008-08-26 15:01:29 -0500487 *
488 * When to use additive latency for DDR2:
489 *
490 * I. Because you are using CL=3 and need to do ODT on writes and
491 * want functionality.
492 * 1. Are you going to use ODT? (Does your board not have
493 * additional termination circuitry for DQ, DQS, DQS_,
494 * DM, RDQS, RDQS_ for x4/x8 configs?)
495 * 2. If so, is your lowest supported CL going to be 3?
496 * 3. If so, then you must set AL=1 because
497 *
498 * WL >= 3 for ODT on writes
499 * RL = AL + CL
500 * WL = RL - 1
501 * ->
502 * WL = AL + CL - 1
503 * AL + CL - 1 >= 3
504 * AL + CL >= 4
505 * QED
506 *
507 * RL >= 3 for ODT on reads
508 * RL = AL + CL
509 *
510 * Since CL aren't usually less than 2, AL=0 is a minimum,
511 * so the WL-derived AL should be the -- FIXME?
512 *
513 * II. Because you are using auto-precharge globally and want to
514 * use additive latency (posted CAS) to get more bandwidth.
515 * 1. Are you going to use auto-precharge mode globally?
516 *
517 * Use addtivie latency and compute AL to be 1 cycle less than
518 * tRCD, i.e. the READ or WRITE command is in the cycle
519 * immediately following the ACTIVATE command..
520 *
521 * III. Because you feel like it or want to do some sort of
522 * degraded-performance experiment.
523 * 1. Do you just want to use additive latency because you feel
524 * like it?
525 *
526 * Validation: AL is less than tRCD, and within the other
527 * read-to-precharge constraints.
528 */
529
530 additive_latency = 0;
531
York Sunf0626592013-09-30 09:22:09 -0700532#if defined(CONFIG_SYS_FSL_DDR2)
York Sun2896cb72014-03-27 17:54:47 -0700533 if ((outpdimm->lowest_common_spd_caslat < 4) &&
York Sun2c0b62d2015-01-06 13:18:50 -0800534 (picos_to_mclk(ctrl_num, trcd_ps) >
535 outpdimm->lowest_common_spd_caslat)) {
536 additive_latency = picos_to_mclk(ctrl_num, trcd_ps) -
York Sun2896cb72014-03-27 17:54:47 -0700537 outpdimm->lowest_common_spd_caslat;
York Sun2c0b62d2015-01-06 13:18:50 -0800538 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
539 additive_latency = picos_to_mclk(ctrl_num, trcd_ps);
Kumar Gala124b0822008-08-26 15:01:29 -0500540 debug("setting additive_latency to %u because it was "
541 " greater than tRCD_ps\n", additive_latency);
542 }
543 }
Kumar Gala124b0822008-08-26 15:01:29 -0500544#endif
545
546 /*
547 * Validate additive latency
Kumar Gala124b0822008-08-26 15:01:29 -0500548 *
549 * AL <= tRCD(min)
550 */
York Sun2c0b62d2015-01-06 13:18:50 -0800551 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
Kumar Gala124b0822008-08-26 15:01:29 -0500552 printf("Error: invalid additive latency exceeds tRCD(min).\n");
553 return 1;
554 }
555
556 /*
557 * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled
558 * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled
559 * ADD_LAT (the register) must be set to a value less
560 * than ACTTORW if WL = 1, then AL must be set to 1
561 * RD_TO_PRE (the register) must be set to a minimum
562 * tRTP + AL if AL is nonzero
563 */
564
565 /*
566 * Additive latency will be applied only if the memctl option to
567 * use it.
568 */
569 outpdimm->additive_latency = additive_latency;
570
Priyanka Jain4a717412013-09-25 10:41:19 +0530571 debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps);
572 debug("trcd_ps = %u\n", outpdimm->trcd_ps);
573 debug("trp_ps = %u\n", outpdimm->trp_ps);
574 debug("tras_ps = %u\n", outpdimm->tras_ps);
York Sun2896cb72014-03-27 17:54:47 -0700575#ifdef CONFIG_SYS_FSL_DDR4
576 debug("trfc1_ps = %u\n", trfc1_ps);
577 debug("trfc2_ps = %u\n", trfc2_ps);
578 debug("trfc4_ps = %u\n", trfc4_ps);
579 debug("trrds_ps = %u\n", trrds_ps);
580 debug("trrdl_ps = %u\n", trrdl_ps);
581 debug("tccdl_ps = %u\n", tccdl_ps);
York Sun6db4fdd2018-01-29 09:44:35 -0800582 debug("trfc_slr_ps = %u\n", trfc_slr_ps);
York Sun2896cb72014-03-27 17:54:47 -0700583#else
Priyanka Jain4a717412013-09-25 10:41:19 +0530584 debug("twtr_ps = %u\n", outpdimm->twtr_ps);
585 debug("trfc_ps = %u\n", outpdimm->trfc_ps);
586 debug("trrd_ps = %u\n", outpdimm->trrd_ps);
York Sun2896cb72014-03-27 17:54:47 -0700587#endif
588 debug("twr_ps = %u\n", outpdimm->twr_ps);
Priyanka Jain4a717412013-09-25 10:41:19 +0530589 debug("trc_ps = %u\n", outpdimm->trc_ps);
York Suncd077cf2012-08-17 08:22:40 +0000590
Kumar Gala124b0822008-08-26 15:01:29 -0500591 return 0;
592}