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Minkyu Kangb1b24682011-01-24 15:22:23 +09001/*
2 * (C) Copyright 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
20 */
21
Chander Kashyap4131a772011-12-06 23:34:12 +000022#ifndef _EXYNOS4_CPU_H
23#define _EXYNOS4_CPU_H
Minkyu Kangb1b24682011-01-24 15:22:23 +090024
Chander Kashyap34076a02012-02-05 23:01:46 +000025#define DEVICE_NOT_AVAILABLE 0
26
Chander Kashyap4131a772011-12-06 23:34:12 +000027#define EXYNOS4_ADDR_BASE 0x10000000
Minkyu Kangb1b24682011-01-24 15:22:23 +090028
Chander Kashyap4131a772011-12-06 23:34:12 +000029/* EXYNOS4 */
30#define EXYNOS4_GPIO_PART3_BASE 0x03860000
31#define EXYNOS4_PRO_ID 0x10000000
32#define EXYNOS4_POWER_BASE 0x10020000
33#define EXYNOS4_SWRESET 0x10020400
34#define EXYNOS4_CLOCK_BASE 0x10030000
35#define EXYNOS4_SYSTIMER_BASE 0x10050000
36#define EXYNOS4_WATCHDOG_BASE 0x10060000
37#define EXYNOS4_MIU_BASE 0x10600000
38#define EXYNOS4_DMC0_BASE 0x10400000
39#define EXYNOS4_DMC1_BASE 0x10410000
40#define EXYNOS4_GPIO_PART2_BASE 0x11000000
41#define EXYNOS4_GPIO_PART1_BASE 0x11400000
42#define EXYNOS4_FIMD_BASE 0x11C00000
43#define EXYNOS4_USBOTG_BASE 0x12480000
44#define EXYNOS4_MMC_BASE 0x12510000
45#define EXYNOS4_SROMC_BASE 0x12570000
46#define EXYNOS4_USBPHY_BASE 0x125B0000
47#define EXYNOS4_UART_BASE 0x13800000
48#define EXYNOS4_ADC_BASE 0x13910000
49#define EXYNOS4_PWMTIMER_BASE 0x139D0000
50#define EXYNOS4_MODEM_BASE 0x13A00000
Chander Kashyap34076a02012-02-05 23:01:46 +000051#define EXYNOS4_USBPHY_CONTROL 0x10020704
52
53#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
54
55/* EXYNOS5 */
56#define EXYNOS5_GPIO_PART4_BASE 0x03860000
57#define EXYNOS5_PRO_ID 0x10000000
58#define EXYNOS5_CLOCK_BASE 0x10010000
59#define EXYNOS5_POWER_BASE 0x10040000
60#define EXYNOS5_SWRESET 0x10040400
61#define EXYNOS5_SYSREG_BASE 0x10050000
62#define EXYNOS5_WATCHDOG_BASE 0x101D0000
63#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
64#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
65#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
66#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
67#define EXYNOS5_GPIO_PART1_BASE 0x11400000
68#define EXYNOS5_MMC_BASE 0x12200000
69#define EXYNOS5_SROMC_BASE 0x12250000
70#define EXYNOS5_USBOTG_BASE 0x12480000
71#define EXYNOS5_USBPHY_BASE 0x12480000
72#define EXYNOS5_UART_BASE 0x12C00000
73#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
74#define EXYNOS5_GPIO_PART2_BASE 0x13400000
75#define EXYNOS5_FIMD_BASE 0x14400000
76
77#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
78#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
Minkyu Kangb1b24682011-01-24 15:22:23 +090079
80#ifndef __ASSEMBLY__
81#include <asm/io.h>
82/* CPU detection macros */
83extern unsigned int s5p_cpu_id;
Minkyu Kang13398722011-05-16 19:45:54 +090084extern unsigned int s5p_cpu_rev;
85
86static inline int s5p_get_cpu_rev(void)
87{
88 return s5p_cpu_rev;
89}
Minkyu Kangb1b24682011-01-24 15:22:23 +090090
91static inline void s5p_set_cpu_id(void)
92{
Chander Kashyap4131a772011-12-06 23:34:12 +000093 s5p_cpu_id = readl(EXYNOS4_PRO_ID);
Minkyu Kangb1b24682011-01-24 15:22:23 +090094 s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
95
96 /*
Chander Kashyap4131a772011-12-06 23:34:12 +000097 * 0xC200: EXYNOS4210 EVT0
98 * 0xC210: EXYNOS4210 EVT1
Minkyu Kangb1b24682011-01-24 15:22:23 +090099 */
Minkyu Kang13398722011-05-16 19:45:54 +0900100 if (s5p_cpu_id == 0xC200) {
Minkyu Kangb1b24682011-01-24 15:22:23 +0900101 s5p_cpu_id |= 0x10;
Minkyu Kang13398722011-05-16 19:45:54 +0900102 s5p_cpu_rev = 0;
103 } else if (s5p_cpu_id == 0xC210) {
104 s5p_cpu_rev = 1;
105 }
Minkyu Kangb1b24682011-01-24 15:22:23 +0900106}
107
108#define IS_SAMSUNG_TYPE(type, id) \
109static inline int cpu_is_##type(void) \
110{ \
111 return s5p_cpu_id == id ? 1 : 0; \
112}
113
Chander Kashyap4131a772011-12-06 23:34:12 +0000114IS_SAMSUNG_TYPE(exynos4, 0xc210)
Chander Kashyap34076a02012-02-05 23:01:46 +0000115IS_SAMSUNG_TYPE(exynos5, 0xc520)
Minkyu Kangb1b24682011-01-24 15:22:23 +0900116
117#define SAMSUNG_BASE(device, base) \
118static inline unsigned int samsung_get_base_##device(void) \
119{ \
Chander Kashyap4131a772011-12-06 23:34:12 +0000120 if (cpu_is_exynos4()) \
121 return EXYNOS4_##base; \
Chander Kashyap34076a02012-02-05 23:01:46 +0000122 else if (cpu_is_exynos5()) \
123 return EXYNOS5_##base; \
Minkyu Kangb1b24682011-01-24 15:22:23 +0900124 else \
125 return 0; \
126}
127
128SAMSUNG_BASE(adc, ADC_BASE)
129SAMSUNG_BASE(clock, CLOCK_BASE)
130SAMSUNG_BASE(fimd, FIMD_BASE)
131SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
132SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
133SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
Chander Kashyap34076a02012-02-05 23:01:46 +0000134SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
Minkyu Kangb1b24682011-01-24 15:22:23 +0900135SAMSUNG_BASE(pro_id, PRO_ID)
136SAMSUNG_BASE(mmc, MMC_BASE)
137SAMSUNG_BASE(modem, MODEM_BASE)
138SAMSUNG_BASE(sromc, SROMC_BASE)
139SAMSUNG_BASE(swreset, SWRESET)
140SAMSUNG_BASE(timer, PWMTIMER_BASE)
141SAMSUNG_BASE(uart, UART_BASE)
142SAMSUNG_BASE(usb_phy, USBPHY_BASE)
143SAMSUNG_BASE(usb_otg, USBOTG_BASE)
144SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
HeungJun, Kimb3717272012-01-16 21:13:04 +0000145SAMSUNG_BASE(power, POWER_BASE)
Minkyu Kangb1b24682011-01-24 15:22:23 +0900146#endif
147
Chander Kashyap4131a772011-12-06 23:34:12 +0000148#endif /* _EXYNOS4_CPU_H */