blob: 432e380cca65268e72beb9a6f61b6955c2ae630d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Patrick Bruennba81b042016-11-04 11:57:02 +01002/*
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
5 *
6 * Configuration settings for Beckhoff CX9020.
7 *
8 * Based on Freescale's Linux i.MX mx53loco.h file:
9 * Copyright (C) 2010-2011 Freescale Semiconductor.
Patrick Bruennba81b042016-11-04 11:57:02 +010010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#include <asm/arch/imx-regs.h>
16
17#define CONFIG_CMDLINE_TAG
18#define CONFIG_SETUP_MEMORY_TAGS
19#define CONFIG_INITRD_TAG
20
21#define CONFIG_SYS_FSL_CLK
22
Patrick Bruennba81b042016-11-04 11:57:02 +010023#define CONFIG_REVISION_TAG
24
25#define CONFIG_MXC_UART_BASE UART2_BASE
26
27#define CONFIG_FPGA_COUNT 1
28
29/* MMC Configs */
Patrick Bruennba81b042016-11-04 11:57:02 +010030#define CONFIG_SYS_FSL_ESDHC_ADDR 0
31#define CONFIG_SYS_FSL_ESDHC_NUM 2
32
Patrick Bruennba81b042016-11-04 11:57:02 +010033/* bootz: zImage/initrd.img support */
Patrick Bruennba81b042016-11-04 11:57:02 +010034
Patrick Bruennba81b042016-11-04 11:57:02 +010035
36/* USB Configs */
Patrick Bruennba81b042016-11-04 11:57:02 +010037#define CONFIG_MXC_USB_PORT 1
38#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
39#define CONFIG_MXC_USB_FLAGS 0
40
Patrick Bruennba81b042016-11-04 11:57:02 +010041/* Command definition */
Patrick Bruennba81b042016-11-04 11:57:02 +010042
Steffen Dirkwinkelab0ed602019-10-23 07:40:43 +020043#define BOOT_TARGET_DEVICES(func) \
44 func(MMC, mmc, 0) \
45 func(MMC, mmc, 1) \
46 func(USB, usb, 0) \
47 func(PXE, pxe, na)
48
49#include <config_distro_bootcmd.h>
50
Patrick Bruennba81b042016-11-04 11:57:02 +010051#define CONFIG_EXTRA_ENV_SETTINGS \
Steffen Dirkwinkelab0ed602019-10-23 07:40:43 +020052 "fdt_addr_r=0x75000000\0" \
Patrick Bruenn2ef943e2017-07-11 11:23:21 +020053 "pxefile_addr_r=0x73000000\0" \
Steffen Dirkwinkelab0ed602019-10-23 07:40:43 +020054 "scriptaddr=0x74000000\0" \
55 "ramdisk_addr_r=0x80000000\0" \
56 "kernel_addr_r=0x72000000\0" \
57 "fdt_high=0xffffffff\0" \
Patrick Bruennba81b042016-11-04 11:57:02 +010058 "console=ttymxc1,115200\0" \
Steffen Dirkwinkela2cab662019-10-23 07:40:42 +020059 "stdin=serial\0" \
60 "stdout=serial,vidconsole\0" \
61 "stderr=serial,vidconsole\0" \
Steffen Dirkwinkelab0ed602019-10-23 07:40:43 +020062 "fdtfile=imx53-cx9020.dtb\0" \
63 BOOTENV
Patrick Bruennba81b042016-11-04 11:57:02 +010064
65#define CONFIG_ARP_TIMEOUT 200UL
66
67/* Miscellaneous configurable options */
Patrick Bruennba81b042016-11-04 11:57:02 +010068#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
69
Patrick Bruennba81b042016-11-04 11:57:02 +010070/* Physical Memory Map */
Patrick Bruennba81b042016-11-04 11:57:02 +010071#define PHYS_SDRAM_1 CSD0_BASE_ADDR
72#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
73#define PHYS_SDRAM_2 CSD1_BASE_ADDR
74#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
75#define PHYS_SDRAM_SIZE (gd->ram_size)
76
77#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
78#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
79#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
80
81#define CONFIG_SYS_INIT_SP_OFFSET \
82 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
83#define CONFIG_SYS_INIT_SP_ADDR \
84 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
85
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090086/* environment organization */
Patrick Bruennba81b042016-11-04 11:57:02 +010087
88/* Framebuffer and LCD */
Steffen Dirkwinkel31736182019-04-17 13:57:17 +020089#define CONFIG_IMX_VIDEO_SKIP
Patrick Bruennba81b042016-11-04 11:57:02 +010090
91#endif /* __CONFIG_H */