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git01.mediatek.com / filogic / uboot / a06d8a17800bf2fb705fb70a0be2482eb59cd9d9 / . / arch / sandbox / dts / test.dts
blob: 6803c00f90ac155531f2f5bc7d9f2572fb99ef78 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glassed96cde2018-12-10 10:37:33 -0700[diff] [blame]45 audio: audio-codec {
46 compatible = "sandbox,audio-codec";
47 #sound-dai-cells = <1>;
48 };
49
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]50 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]51 reg = <0 0>;
52 compatible = "google,cros-ec-sandbox";
53
54 /*
55 * This describes the flash memory within the EC. Note
56 * that the STM32L flash erases to 0, not 0xff.
57 */
58 flash {
59 image-pos = <0x08000000>;
60 size = <0x20000>;
61 erase-value = <0>;
62
63 /* Information for sandbox */
64 ro {
65 image-pos = <0>;
66 size = <0xf000>;
67 };
68 wp-ro {
69 image-pos = <0xf000>;
70 size = <0x1000>;
71 };
72 rw {
73 image-pos = <0x10000>;
74 size = <0x10000>;
75 };
76 };
77 };
78
Yannick Fertré9712c822019-10-07 15:29:05 +0200[diff] [blame]79 dsi_host: dsi_host {
80 compatible = "sandbox,dsi-host";
81 };
82
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]83 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]84 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]85 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]86 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]87 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]88 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]89 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
90 <0>, <&gpio_a 12>;
91 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
92 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
93 <&gpio_b 9 0xc 3 2 1>;
Simon Glass6df01f92018-12-10 10:37:37 -0700[diff] [blame]94 int-value = <1234>;
95 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200[diff] [blame]96 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200[diff] [blame]97 int-array = <5678 9123 4567>;
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]98 interrupts-extended = <&irq 3 0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]99 };
100
101 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]102 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]103 compatible = "not,compatible";
104 };
105
106 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]107 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]108 };
109
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]110 backlight: backlight {
111 compatible = "pwm-backlight";
112 enable-gpios = <&gpio_a 1>;
113 power-supply = <&ldo_1>;
114 pwms = <&pwm 0 1000>;
115 default-brightness-level = <5>;
116 brightness-levels = <0 16 32 64 128 170 202 234 255>;
117 };
118
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]119 bind-test {
120 bind-test-child1 {
121 compatible = "sandbox,phy";
122 #phy-cells = <1>;
123 };
124
125 bind-test-child2 {
126 compatible = "simple-bus";
127 };
128 };
129
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]130 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]131 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]132 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]133 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]134 ping-add = <3>;
135 };
136
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]137 phy_provider0: gen_phy@0 {
138 compatible = "sandbox,phy";
139 #phy-cells = <1>;
140 };
141
142 phy_provider1: gen_phy@1 {
143 compatible = "sandbox,phy";
144 #phy-cells = <0>;
145 broken;
146 };
147
148 gen_phy_user: gen_phy_user {
149 compatible = "simple-bus";
150 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
151 phy-names = "phy1", "phy2", "phy3";
152 };
153
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]154 some-bus {
155 #address-cells = <1>;
156 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]157 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]158 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]159 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]160 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]161 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]162 compatible = "denx,u-boot-fdt-test";
163 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]164 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]165 ping-add = <5>;
166 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]167 c-test@0 {
168 compatible = "denx,u-boot-fdt-test";
169 reg = <0>;
170 ping-expect = <6>;
171 ping-add = <6>;
172 };
173 c-test@1 {
174 compatible = "denx,u-boot-fdt-test";
175 reg = <1>;
176 ping-expect = <7>;
177 ping-add = <7>;
178 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]179 };
180
181 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]182 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]183 ping-expect = <6>;
184 ping-add = <6>;
185 compatible = "google,another-fdt-test";
186 };
187
188 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]189 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]190 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]191 ping-add = <6>;
192 compatible = "google,another-fdt-test";
193 };
194
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]195 f-test {
196 compatible = "denx,u-boot-fdt-test";
197 };
198
199 g-test {
200 compatible = "denx,u-boot-fdt-test";
201 };
202
Bin Mengd9d24782018-10-10 22:07:01 -0700[diff] [blame]203 h-test {
204 compatible = "denx,u-boot-fdt-test1";
205 };
206
Simon Glass204675c2019-12-29 21:19:25 -0700[diff] [blame]207 devres-test {
208 compatible = "denx,u-boot-devres-test";
209 };
210
Simon Glass2d67fdf2020-04-08 16:57:34 -0600[diff] [blame]211 acpi-test {
212 compatible = "denx,u-boot-acpi-test";
213 };
214
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]215 clocks {
216 clk_fixed: clk-fixed {
217 compatible = "fixed-clock";
218 #clock-cells = <0>;
219 clock-frequency = <1234>;
220 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]221
222 clk_fixed_factor: clk-fixed-factor {
223 compatible = "fixed-factor-clock";
224 #clock-cells = <0>;
225 clock-div = <3>;
226 clock-mult = <2>;
227 clocks = <&clk_fixed>;
228 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200[diff] [blame]229
230 osc {
231 compatible = "fixed-clock";
232 #clock-cells = <0>;
233 clock-frequency = <20000000>;
234 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]235 };
236
237 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]238 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]239 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200[diff] [blame]240 assigned-clocks = <&clk_sandbox 3>;
241 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]242 };
243
244 clk-test {
245 compatible = "sandbox,clk-test";
246 clocks = <&clk_fixed>,
247 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]248 <&clk_sandbox 0>,
249 <&clk_sandbox 3>,
250 <&clk_sandbox 2>;
251 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]252 };
253
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200[diff] [blame]254 ccf: clk-ccf {
255 compatible = "sandbox,clk-ccf";
256 };
257
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]258 eth@10002000 {
259 compatible = "sandbox,eth";
260 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]261 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]262 };
263
264 eth_5: eth@10003000 {
265 compatible = "sandbox,eth";
266 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]267 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]268 };
269
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]270 eth_3: sbe5 {
271 compatible = "sandbox,eth";
272 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]273 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]274 };
275
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]276 eth@10004000 {
277 compatible = "sandbox,eth";
278 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]279 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]280 };
281
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700[diff] [blame]282 firmware {
283 sandbox_firmware: sandbox-firmware {
284 compatible = "sandbox,firmware";
285 };
286 };
287
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]288 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]289 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]290 gpio-controller;
291 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]292 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]293 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]294 };
295
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]296 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]297 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]298 gpio-controller;
299 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]300 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]301 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]302 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]303
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]304 i2c@0 {
305 #address-cells = <1>;
306 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]307 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]308 compatible = "sandbox,i2c";
309 clock-frequency = <100000>;
310 eeprom@2c {
311 reg = <0x2c>;
312 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]313 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]314 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]315
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]316 rtc_0: rtc@43 {
317 reg = <0x43>;
318 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]319 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]320 };
321
322 rtc_1: rtc@61 {
323 reg = <0x61>;
324 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]325 sandbox,emul = <&emul1>;
326 };
327
328 i2c_emul: emul {
329 reg = <0xff>;
330 compatible = "sandbox,i2c-emul-parent";
331 emul_eeprom: emul-eeprom {
332 compatible = "sandbox,i2c-eeprom";
333 sandbox,filename = "i2c.bin";
334 sandbox,size = <256>;
335 };
336 emul0: emul0 {
337 compatible = "sandbox,i2c-rtc";
338 };
339 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]340 compatible = "sandbox,i2c-rtc";
341 };
342 };
343
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]344 sandbox_pmic: sandbox_pmic {
345 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]346 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]347 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]348
349 mc34708: pmic@41 {
350 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]351 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]352 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]353 };
354
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100[diff] [blame]355 bootcount@0 {
356 compatible = "u-boot,bootcount-rtc";
357 rtc = <&rtc_1>;
358 offset = <0x13>;
359 };
360
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]361 adc@0 {
362 compatible = "sandbox,adc";
363 vdd-supply = <&buck2>;
364 vss-microvolts = <0>;
365 };
366
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]367 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700[diff] [blame]368 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]369 interrupt-controller;
370 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700[diff] [blame]371 };
372
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]373 lcd {
374 u-boot,dm-pre-reloc;
375 compatible = "sandbox,lcd-sdl";
376 xres = <1366>;
377 yres = <768>;
378 };
379
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]380 leds {
381 compatible = "gpio-leds";
382
383 iracibble {
384 gpios = <&gpio_a 1 0>;
385 label = "sandbox:red";
386 };
387
388 martinet {
389 gpios = <&gpio_a 2 0>;
390 label = "sandbox:green";
391 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]392
393 default_on {
394 gpios = <&gpio_a 5 0>;
395 label = "sandbox:default_on";
396 default-state = "on";
397 };
398
399 default_off {
400 gpios = <&gpio_a 6 0>;
401 label = "sandbox:default_off";
402 default-state = "off";
403 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]404 };
405
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]406 mbox: mbox {
407 compatible = "sandbox,mbox";
408 #mbox-cells = <1>;
409 };
410
411 mbox-test {
412 compatible = "sandbox,mbox-test";
413 mboxes = <&mbox 100>, <&mbox 1>;
414 mbox-names = "other", "test";
415 };
416
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]417 cpus {
418 cpu-test1 {
419 compatible = "sandbox,cpu_sandbox";
420 u-boot,dm-pre-reloc;
421 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]422
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]423 cpu-test2 {
424 compatible = "sandbox,cpu_sandbox";
425 u-boot,dm-pre-reloc;
426 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]427
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]428 cpu-test3 {
429 compatible = "sandbox,cpu_sandbox";
430 u-boot,dm-pre-reloc;
431 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]432 };
433
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]434 i2s: i2s {
435 compatible = "sandbox,i2s";
436 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700[diff] [blame]437 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]438 };
439
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200[diff] [blame]440 nop-test_0 {
441 compatible = "sandbox,nop_sandbox1";
442 nop-test_1 {
443 compatible = "sandbox,nop_sandbox2";
444 bind = "True";
445 };
446 nop-test_2 {
447 compatible = "sandbox,nop_sandbox2";
448 bind = "False";
449 };
450 };
451
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]452 misc-test {
453 compatible = "sandbox,misc_sandbox";
454 };
455
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]456 mmc2 {
457 compatible = "sandbox,mmc";
458 };
459
460 mmc1 {
461 compatible = "sandbox,mmc";
462 };
463
464 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]465 compatible = "sandbox,mmc";
466 };
467
Simon Glass53a68b32019-02-16 20:24:50 -0700[diff] [blame]468 pch {
469 compatible = "sandbox,pch";
470 };
471
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]472 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]473 compatible = "sandbox,pci";
474 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]475 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]476 #address-cells = <3>;
477 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600[diff] [blame]478 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]479 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]480 pci@0,0 {
481 compatible = "pci-generic";
482 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]483 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]484 };
Alex Margineanf1274432019-06-07 11:24:24 +0300[diff] [blame]485 pci@1,0 {
486 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600[diff] [blame]487 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
488 reg = <0x02000814 0 0 0 0
489 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]490 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300[diff] [blame]491 };
Simon Glass937bb472019-12-06 21:41:57 -0700[diff] [blame]492 p2sb-pci@2,0 {
493 compatible = "sandbox,p2sb";
494 reg = <0x02001010 0 0 0 0>;
495 sandbox,emul = <&p2sb_emul>;
496
497 adder {
498 intel,p2sb-port-id = <3>;
499 compatible = "sandbox,adder";
500 };
501 };
Simon Glass8c501022019-12-06 21:41:54 -0700[diff] [blame]502 pci@1e,0 {
503 compatible = "sandbox,pmc";
504 reg = <0xf000 0 0 0 0>;
505 sandbox,emul = <&pmc_emul1e>;
506 acpi-base = <0x400>;
507 gpe0-dwx-mask = <0xf>;
508 gpe0-dwx-shift-base = <4>;
509 gpe0-dw = <6 7 9>;
510 gpe0-sts = <0x20>;
511 gpe0-en = <0x30>;
512 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]513 pci@1f,0 {
514 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600[diff] [blame]515 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
516 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]517 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]518 };
519 };
520
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]521 pci-emul0 {
522 compatible = "sandbox,pci-emul-parent";
523 swap_case_emul0_0: emul0@0,0 {
524 compatible = "sandbox,swap-case";
525 };
526 swap_case_emul0_1: emul0@1,0 {
527 compatible = "sandbox,swap-case";
528 use-ea;
529 };
530 swap_case_emul0_1f: emul0@1f,0 {
531 compatible = "sandbox,swap-case";
532 };
Simon Glass937bb472019-12-06 21:41:57 -0700[diff] [blame]533 p2sb_emul: emul@2,0 {
534 compatible = "sandbox,p2sb-emul";
535 };
Simon Glass8c501022019-12-06 21:41:54 -0700[diff] [blame]536 pmc_emul1e: emul@1e,0 {
537 compatible = "sandbox,pmc-emul";
538 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]539 };
540
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]541 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]542 compatible = "sandbox,pci";
543 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]544 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]545 #address-cells = <3>;
546 #size-cells = <2>;
547 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
548 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]549 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200[diff] [blame]550 0x0c 0x00 0x1234 0x5678
551 0x10 0x00 0x1234 0x5678>;
552 pci@10,0 {
553 reg = <0x8000 0 0 0 0>;
554 };
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]555 };
556
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]557 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]558 compatible = "sandbox,pci";
559 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]560 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]561 #address-cells = <3>;
562 #size-cells = <2>;
563 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
564 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
565 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
566 pci@1f,0 {
567 compatible = "pci-generic";
568 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]569 sandbox,emul = <&swap_case_emul2_1f>;
570 };
571 };
572
573 pci-emul2 {
574 compatible = "sandbox,pci-emul-parent";
575 swap_case_emul2_1f: emul2@1f,0 {
576 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]577 };
578 };
579
Ramon Friedc64f19b2019-04-27 11:15:23 +0300[diff] [blame]580 pci_ep: pci_ep {
581 compatible = "sandbox,pci_ep";
582 };
583
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]584 probing {
585 compatible = "simple-bus";
586 test1 {
587 compatible = "denx,u-boot-probe-test";
588 };
589
590 test2 {
591 compatible = "denx,u-boot-probe-test";
592 };
593
594 test3 {
595 compatible = "denx,u-boot-probe-test";
596 };
597
598 test4 {
599 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]600 first-syscon = <&syscon0>;
601 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100[diff] [blame]602 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]603 };
604 };
605
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]606 pwrdom: power-domain {
607 compatible = "sandbox,power-domain";
608 #power-domain-cells = <1>;
609 };
610
611 power-domain-test {
612 compatible = "sandbox,power-domain-test";
613 power-domains = <&pwrdom 2>;
614 };
615
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]616 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]617 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]618 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]619 };
620
621 pwm2 {
622 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]623 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]624 };
625
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]626 ram {
627 compatible = "sandbox,ram";
628 };
629
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]630 reset@0 {
631 compatible = "sandbox,warm-reset";
632 };
633
634 reset@1 {
635 compatible = "sandbox,reset";
636 };
637
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]638 resetc: reset-ctl {
639 compatible = "sandbox,reset-ctl";
640 #reset-cells = <1>;
641 };
642
643 reset-ctl-test {
644 compatible = "sandbox,reset-ctl-test";
645 resets = <&resetc 100>, <&resetc 2>;
646 reset-names = "other", "test";
647 };
648
Sughosh Ganu23e37512019-12-28 23:58:31 +0530[diff] [blame]649 rng {
650 compatible = "sandbox,sandbox-rng";
651 };
652
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]653 rproc_1: rproc@1 {
654 compatible = "sandbox,test-processor";
655 remoteproc-name = "remoteproc-test-dev1";
656 };
657
658 rproc_2: rproc@2 {
659 compatible = "sandbox,test-processor";
660 internal-memory-mapped;
661 remoteproc-name = "remoteproc-test-dev2";
662 };
663
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]664 panel {
665 compatible = "simple-panel";
666 backlight = <&backlight 0 100>;
667 };
668
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]669 smem@0 {
670 compatible = "sandbox,smem";
671 };
672
Simon Glass76072ac2018-12-10 10:37:36 -0700[diff] [blame]673 sound {
674 compatible = "sandbox,sound";
675 cpu {
676 sound-dai = <&i2s 0>;
677 };
678
679 codec {
680 sound-dai = <&audio 0>;
681 };
682 };
683
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]684 spi@0 {
685 #address-cells = <1>;
686 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]687 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]688 compatible = "sandbox,spi";
689 cs-gpios = <0>, <&gpio_a 0>;
690 spi.bin@0 {
691 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]692 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]693 spi-max-frequency = <40000000>;
694 sandbox,filename = "spi.bin";
695 };
696 };
697
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]698 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]699 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200[diff] [blame]700 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]701 };
702
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]703 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]704 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]705 reg = <0x20 5
706 0x28 6
707 0x30 7
708 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]709 };
710
Patrick Delaunayee010432019-03-07 09:57:13 +0100[diff] [blame]711 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]712 compatible = "simple-mfd", "syscon";
713 reg = <0x40 5
714 0x48 6
715 0x50 7
716 0x58 8>;
717 };
718
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]719 timer {
720 compatible = "sandbox,timer";
721 clock-frequency = <1000000>;
722 };
723
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]724 tpm2 {
725 compatible = "sandbox,tpm2";
726 };
727
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]728 uart0: serial {
729 compatible = "sandbox,serial";
730 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]731 };
732
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]733 usb_0: usb@0 {
734 compatible = "sandbox,usb";
735 status = "disabled";
736 hub {
737 compatible = "sandbox,usb-hub";
738 #address-cells = <1>;
739 #size-cells = <0>;
740 flash-stick {
741 reg = <0>;
742 compatible = "sandbox,usb-flash";
743 };
744 };
745 };
746
747 usb_1: usb@1 {
748 compatible = "sandbox,usb";
749 hub {
750 compatible = "usb-hub";
751 usb,device-class = <9>;
752 hub-emul {
753 compatible = "sandbox,usb-hub";
754 #address-cells = <1>;
755 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]756 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]757 reg = <0>;
758 compatible = "sandbox,usb-flash";
759 sandbox,filepath = "testflash.bin";
760 };
761
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]762 flash-stick@1 {
763 reg = <1>;
764 compatible = "sandbox,usb-flash";
765 sandbox,filepath = "testflash1.bin";
766 };
767
768 flash-stick@2 {
769 reg = <2>;
770 compatible = "sandbox,usb-flash";
771 sandbox,filepath = "testflash2.bin";
772 };
773
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]774 keyb@3 {
775 reg = <3>;
776 compatible = "sandbox,usb-keyb";
777 };
778
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]779 };
780 };
781 };
782
783 usb_2: usb@2 {
784 compatible = "sandbox,usb";
785 status = "disabled";
786 };
787
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]788 spmi: spmi@0 {
789 compatible = "sandbox,spmi";
790 #address-cells = <0x1>;
791 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600[diff] [blame]792 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]793 pm8916@0 {
794 compatible = "qcom,spmi-pmic";
795 reg = <0x0 0x1>;
796 #address-cells = <0x1>;
797 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600[diff] [blame]798 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]799
800 spmi_gpios: gpios@c000 {
801 compatible = "qcom,pm8916-gpio";
802 reg = <0xc000 0x400>;
803 gpio-controller;
804 gpio-count = <4>;
805 #gpio-cells = <2>;
806 gpio-bank-name="spmi";
807 };
808 };
809 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]810
811 wdt0: wdt@0 {
812 compatible = "sandbox,wdt";
813 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]814
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]815 axi: axi@0 {
816 compatible = "sandbox,axi";
817 #address-cells = <0x1>;
818 #size-cells = <0x1>;
819 store@0 {
820 compatible = "sandbox,sandbox_store";
821 reg = <0x0 0x400>;
822 };
823 };
824
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]825 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]826 #address-cells = <1>;
827 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -0700[diff] [blame]828 setting = "sunrise ohoka";
829 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -0700[diff] [blame]830 int-values = <0x1937 72993>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]831 chosen-test {
832 compatible = "denx,u-boot-fdt-test";
833 reg = <9 1>;
834 };
835 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]836
837 translation-test@8000 {
838 compatible = "simple-bus";
839 reg = <0x8000 0x4000>;
840
841 #address-cells = <0x2>;
842 #size-cells = <0x1>;
843
844 ranges = <0 0x0 0x8000 0x1000
845 1 0x100 0x9000 0x1000
846 2 0x200 0xA000 0x1000
847 3 0x300 0xB000 0x1000
848 >;
849
Fabien Dessenne22236e02019-05-31 15:11:30 +0200[diff] [blame]850 dma-ranges = <0 0x000 0x10000000 0x1000
851 1 0x100 0x20000000 0x1000
852 >;
853
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]854 dev@0,0 {
855 compatible = "denx,u-boot-fdt-dummy";
856 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100[diff] [blame]857 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]858 };
859
860 dev@1,100 {
861 compatible = "denx,u-boot-fdt-dummy";
862 reg = <1 0x100 0x1000>;
863
864 };
865
866 dev@2,200 {
867 compatible = "denx,u-boot-fdt-dummy";
868 reg = <2 0x200 0x1000>;
869 };
870
871
872 noxlatebus@3,300 {
873 compatible = "simple-bus";
874 reg = <3 0x300 0x1000>;
875
876 #address-cells = <0x1>;
877 #size-cells = <0x0>;
878
879 dev@42 {
880 compatible = "denx,u-boot-fdt-dummy";
881 reg = <0x42>;
882 };
883 };
884 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]885
886 osd {
887 compatible = "sandbox,sandbox_osd";
888 };
Tom Rinib93eea72018-09-30 18:16:51 -0400[diff] [blame]889
Mario Sixab664ff2018-07-31 11:44:13 +0200[diff] [blame]890 board {
891 compatible = "sandbox,board_sandbox";
892 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200[diff] [blame]893
894 sandbox_tee {
895 compatible = "sandbox,tee";
896 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700[diff] [blame]897
898 sandbox_virtio1 {
899 compatible = "sandbox,virtio1";
900 };
901
902 sandbox_virtio2 {
903 compatible = "sandbox,virtio2";
904 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200[diff] [blame]905
906 pinctrl {
907 compatible = "sandbox,pinctrl";
908 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100[diff] [blame]909
910 hwspinlock@0 {
911 compatible = "sandbox,hwspinlock";
912 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]913
914 dma: dma {
915 compatible = "sandbox,dma";
916 #dma-cells = <1>;
917
918 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
919 dma-names = "m2m", "tx0", "rx0";
920 };
Alex Marginean0daa53a2019-06-03 19:12:28 +0300[diff] [blame]921
Alex Marginean0649be52019-07-12 10:13:53 +0300[diff] [blame]922 /*
923 * keep mdio-mux ahead of mdio so that the mux is removed first at the
924 * end of the test. If parent mdio is removed first, clean-up of the
925 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
926 * active at the end of the test. That it turn doesn't allow the mdio
927 * class to be destroyed, triggering an error.
928 */
929 mdio-mux-test {
930 compatible = "sandbox,mdio-mux";
931 #address-cells = <1>;
932 #size-cells = <0>;
933 mdio-parent-bus = <&mdio>;
934
935 mdio-ch-test@0 {
936 reg = <0>;
937 };
938 mdio-ch-test@1 {
939 reg = <1>;
940 };
941 };
942
943 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +0300[diff] [blame]944 compatible = "sandbox,mdio";
945 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]946};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]947
948#include "sandbox_pmic.dtsi"