dts/upstream/src/arm64/ti/k3-j722s-evm.dts

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree file for the J722S EVM
 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Schematics: https://www.ti.com/lit/zip/sprr495
 */

/dts-v1/;

#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy.h>
#include "k3-j722s.dtsi"
#include "k3-serdes.h"

/ {
	compatible = "ti,j722s-evm", "ti,j722s";
	model = "Texas Instruments J722S EVM";

	aliases {
		serial0 = &wkup_uart0;
		serial2 = &main_uart0;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
	};

	chosen {
		stdout-path = &main_uart0;
	};

	memory@80000000 {
		/* 8G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
		      <0x00000008 0x80000000 0x00000001 0x80000000>;
		device_type = "memory";
		bootph-pre-ram;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_tfa_ddr: tfa@9e780000 {
			reg = <0x00 0x9e780000 0x00 0x80000>;
			no-map;
		};

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>;
			no-map;
		};

		wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

	};

	vmain_pd: regulator-0 {
		/* TPS65988 PD CONTROLLER OUTPUT */
		compatible = "regulator-fixed";
		regulator-name = "vmain_pd";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
		bootph-all;
	};

	vsys_5v0: regulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vmain_pd>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: regulator-mmc1 {
		/* TPS22918DBVR */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		gpio = <&exp1 15 GPIO_ACTIVE_HIGH>;
		bootph-all;
	};

	vdd_sd_dv: regulator-TLV71033 {
		compatible = "regulator-gpio";
		regulator-name = "tlv71033";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	vsys_io_3v3: regulator-vsys-io-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_io_1v8: regulator-vsys-io-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_io_1v2: regulator-vsys-io-1v2 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_1v2";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-always-on;
		regulator-boot-on;
	};

	codec_audio: sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "J722S-EVM";
		simple-audio-card,widgets =
			"Headphone",	"Headphone Jack",
			"Line",		"Line In",
			"Microphone",	"Microphone Jack";
		simple-audio-card,routing =
			"Headphone Jack",	"HPLOUT",
			"Headphone Jack",	"HPROUT",
			"LINE1L",		"Line In",
			"LINE1R",		"Line In",
			"MIC3R",		"Microphone Jack",
			"Microphone Jack",	"Mic Bias";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound_master>;
		simple-audio-card,frame-master = <&sound_master>;
		simple-audio-card,bitclock-inversion;

		simple-audio-card,cpu {
			sound-dai = <&mcasp1>;
		};

		sound_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			clocks = <&audio_refclk1>;
		};
	};
};

&main_pmx0 {

	main_i2c0_pins_default: main-i2c0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */
			J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */
		>;
		bootph-all;
	};

	main_uart0_pins_default: main-uart0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x01c8, PIN_INPUT, 0)	/* (A22) UART0_RXD */
			J722S_IOPAD(0x01cc, PIN_OUTPUT, 0)	/* (B22) UART0_TXD */
		>;
		bootph-all;
	};

	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */
		>;
		bootph-all;
	};

	main_mmc1_pins_default: main-mmc1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */
			J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */
			J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */
			J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */
			J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */
			J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */
			J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */
		>;
		bootph-all;
	};

	mdio_pins_default: mdio-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */
			J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */
		>;
	};

	ospi0_pins_default: ospi0-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */
			J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */
			J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */
			J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */
			J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */
			J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */
			J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */
			J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */
			J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */
			J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */
			J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */
		>;
		bootph-all;
	};

	rgmii1_pins_default: rgmii1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */
			J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */
			J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */
			J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */
			J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */
			J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */
			J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */
			J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */
			J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */
			J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */
			J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
			J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
		>;
	};

	main_usb1_pins_default: main-usb1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
		>;
	};

	main_mcasp1_pins_default: main-mcasp1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (P27) GPMC0_BE0n_CLE.MCASP1_ACLKX */
			J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (V21) GPMC0_WAIT0.MCASP1_AFSX */
			J722S_IOPAD(0x008c, PIN_OUTPUT, 2) /* (N23) GPMC0_WEn.MCASP1_AXR0 */
			J722S_IOPAD(0x0084, PIN_INPUT, 2) /* (N21) GPMC0_ADVn_ALE.MCASP1_AXR2 */
		>;
	};

	audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
		pinctrl-single,pins = <
			J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
		>;
	};
};

&cpsw3g {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii1_pins_default>;
};

&cpsw3g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default>;

	cpsw3g_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy0>;
	status = "okay";
};

&main_gpio1 {
	status = "okay";
};

&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	status = "okay";
	bootph-all;
};

&mcu_pmx0 {

	wkup_uart0_pins_default: wkup-uart0-default-pins {
		pinctrl-single,pins = <
			J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C7) WKUP_UART0_CTSn */
			J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (C6) WKUP_UART0_RTSn */
			J722S_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (D8) WKUP_UART0_RXD */
			J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
		>;
		bootph-all;
	};

	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
		pinctrl-single,pins = <
			J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0)	/* (C7) WKUP_I2C0_SCL */
			J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0)	/* (C6) WKUP_I2C1_SDA */
		>;
		bootph-all;
	};
};

&wkup_uart0 {
	/* WKUP UART0 is used by Device Manager firmware */
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
	status = "reserved";
	bootph-all;
};

&wkup_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_i2c0_pins_default>;
	clock-frequency = <400000>;
	status = "okay";
	bootph-all;
};

&k3_clks {
	/* Configure AUDIO_EXT_REFCLK1 pin as output */
	pinctrl-names = "default";
	pinctrl-0 = <&audio_ext_refclk1_pins_default>;
};

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;
	status = "okay";
	bootph-all;

	exp1: gpio@23 {
		compatible = "ti,tca6424";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL",
				  "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#",
				  "CSI_VIO_SEL", "USB2.0_MUX_SEL",
				  "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2",
				  "LMK1_OE1", "LMK1_OE0",
				  "LMK2_OE0", "LMK2_OE1",
				  "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn",
				  "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN",
				  "USER_LED2", "MCAN0_STB",
				  "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
				  "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
				  "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";

		p05-hog {
			/* P05 - USB2.0_MUX_SEL */
			gpio-hog;
			gpios = <5 GPIO_ACTIVE_HIGH>;
			output-high;
		};

		p01_hog: p01-hog {
			/* P01 - TRC_MUX_SEL */
			gpio-hog;
			gpios = <0 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "TRC_MUX_SEL";
		};

		p02_hog: p02-hog {
			/* P02 - MCASP1_FET_SEL */
			gpio-hog;
			gpios = <2 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "MCASP1_FET_SEL";
		};

		p13_hog: p13-hog {
			/* P13 - GPIO_AUD_RSTn */
			gpio-hog;
			gpios = <13 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "GPIO_AUD_RSTn";
		};
	};

	tlv320aic3106: audio-codec@1b {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x1b>;
		ai3x-micbias-vg = <1>;  /* 2.0V */
		AVDD-supply = <&vsys_io_3v3>;
		IOVDD-supply = <&vsys_io_3v3>;
		DRVDD-supply = <&vsys_io_3v3>;
		DVDD-supply = <&vsys_io_1v8>;
	};
};

&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;
		bootph-all;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "ospi.tiboot3";
				reg = <0x00 0x80000>;
			};

			partition@80000 {
				label = "ospi.tispl";
				reg = <0x80000 0x200000>;
			};

			partition@280000 {
				label = "ospi.u-boot";
				reg = <0x280000 0x400000>;
			};

			partition@680000 {
				label = "ospi.env";
				reg = <0x680000 0x40000>;
			};

			partition@6c0000 {
				label = "ospi.env.backup";
				reg = <0x6c0000 0x40000>;
			};

			partition@800000 {
				label = "ospi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fc0000 {
				label = "ospi.phypattern";
				reg = <0x3fc0000 0x40000>;
			};
		};
	};

};

&sdhci0 {
	disable-wp;
	bootph-all;
	ti,driver-strength-ohm = <50>;
	status = "okay";
};

&sdhci1 {
	/* SD/MMC */
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	status = "okay";
	bootph-all;
};

&serdes_ln_ctrl {
	idle-states = <J722S_SERDES0_LANE0_USB>,
		      <J722S_SERDES1_LANE0_PCIE0_LANE0>;
};

&serdes0 {
	status = "okay";
	serdes0_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz0 1>;
	};
};

&serdes1 {
	status = "okay";
	serdes1_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>;
	};
};

&pcie0_rc {
	reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
	phys = <&serdes1_pcie_link>;
	phy-names = "pcie-phy";
	status = "okay";
};

&usbss0 {
	ti,vbus-divider;
	status = "okay";
};

&usb0 {
	dr_mode = "otg";
	usb-role-switch;
};

&usbss1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usb1_pins_default>;
	ti,vbus-divider;
	status = "okay";
};

&usb1 {
	dr_mode = "host";
	maximum-speed = "super-speed";
	phys = <&serdes0_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&mcasp1 {
	status = "okay";
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcasp1_pins_default>;
	op-mode = <0>; /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
	       1 0 2 0
	       0 0 0 0
	       0 0 0 0
	       0 0 0 0
	>;
};