| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | #include <dt-bindings/bus/ti-sysc.h> |
| 4 | #include <dt-bindings/clock/dm814.h> |
| 5 | #include <dt-bindings/gpio/gpio.h> |
| 6 | #include <dt-bindings/pinctrl/dm814x.h> |
| 7 | |
| 8 | / { |
| 9 | compatible = "ti,dm814"; |
| 10 | interrupt-parent = <&intc>; |
| 11 | #address-cells = <1>; |
| 12 | #size-cells = <1>; |
| 13 | chosen { }; |
| 14 | |
| 15 | aliases { |
| 16 | i2c0 = &i2c1; |
| 17 | i2c1 = &i2c2; |
| 18 | serial0 = &uart1; |
| 19 | serial1 = &uart2; |
| 20 | serial2 = &uart3; |
| 21 | ethernet0 = &cpsw_emac0; |
| 22 | ethernet1 = &cpsw_emac1; |
| 23 | usb0 = &usb0; |
| 24 | usb1 = &usb1; |
| 25 | phy0 = &usb0_phy; |
| 26 | phy1 = &usb1_phy; |
| 27 | }; |
| 28 | |
| 29 | cpus { |
| 30 | #address-cells = <1>; |
| 31 | #size-cells = <0>; |
| 32 | cpu@0 { |
| 33 | compatible = "arm,cortex-a8"; |
| 34 | device_type = "cpu"; |
| 35 | reg = <0>; |
| 36 | }; |
| 37 | }; |
| 38 | |
| 39 | pmu { |
| 40 | compatible = "arm,cortex-a8-pmu"; |
| 41 | interrupts = <3>; |
| 42 | }; |
| 43 | |
| 44 | /* |
| 45 | * The soc node represents the soc top level view. It is used for IPs |
| 46 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 47 | */ |
| 48 | soc { |
| 49 | compatible = "ti,omap-infra"; |
| 50 | mpu { |
| 51 | compatible = "ti,omap3-mpu"; |
| 52 | ti,hwmods = "mpu"; |
| 53 | }; |
| 54 | }; |
| 55 | |
| 56 | ocp { |
| 57 | compatible = "simple-bus"; |
| 58 | #address-cells = <1>; |
| 59 | #size-cells = <1>; |
| 60 | ranges; |
| 61 | ti,hwmods = "l3_main"; |
| 62 | |
| 63 | usb: usb@47400000 { |
| 64 | compatible = "ti,am33xx-usb"; |
| 65 | reg = <0x47400000 0x1000>; |
| 66 | ranges; |
| 67 | #address-cells = <1>; |
| 68 | #size-cells = <1>; |
| 69 | ti,hwmods = "usb_otg_hs"; |
| 70 | |
| 71 | usb0_phy: usb-phy@47401300 { |
| 72 | compatible = "ti,am335x-usb-phy"; |
| 73 | reg = <0x47401300 0x100>; |
| 74 | reg-names = "phy"; |
| 75 | ti,ctrl_mod = <&usb_ctrl_mod>; |
| 76 | #phy-cells = <0>; |
| 77 | }; |
| 78 | |
| 79 | usb0: usb@47401000 { |
| 80 | compatible = "ti,musb-am33xx"; |
| 81 | reg = <0x47401400 0x400 |
| 82 | 0x47401000 0x200>; |
| 83 | reg-names = "mc", "control"; |
| 84 | |
| 85 | interrupts = <18>; |
| 86 | interrupt-names = "mc"; |
| 87 | dr_mode = "otg"; |
| 88 | mentor,multipoint = <1>; |
| 89 | mentor,num-eps = <16>; |
| 90 | mentor,ram-bits = <12>; |
| 91 | mentor,power = <500>; |
| 92 | phys = <&usb0_phy>; |
| 93 | |
| 94 | dmas = <&cppi41dma 0 0 &cppi41dma 1 0 |
| 95 | &cppi41dma 2 0 &cppi41dma 3 0 |
| 96 | &cppi41dma 4 0 &cppi41dma 5 0 |
| 97 | &cppi41dma 6 0 &cppi41dma 7 0 |
| 98 | &cppi41dma 8 0 &cppi41dma 9 0 |
| 99 | &cppi41dma 10 0 &cppi41dma 11 0 |
| 100 | &cppi41dma 12 0 &cppi41dma 13 0 |
| 101 | &cppi41dma 14 0 &cppi41dma 0 1 |
| 102 | &cppi41dma 1 1 &cppi41dma 2 1 |
| 103 | &cppi41dma 3 1 &cppi41dma 4 1 |
| 104 | &cppi41dma 5 1 &cppi41dma 6 1 |
| 105 | &cppi41dma 7 1 &cppi41dma 8 1 |
| 106 | &cppi41dma 9 1 &cppi41dma 10 1 |
| 107 | &cppi41dma 11 1 &cppi41dma 12 1 |
| 108 | &cppi41dma 13 1 &cppi41dma 14 1>; |
| 109 | dma-names = |
| 110 | "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", |
| 111 | "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", |
| 112 | "rx14", "rx15", |
| 113 | "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", |
| 114 | "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", |
| 115 | "tx14", "tx15"; |
| 116 | }; |
| 117 | |
| 118 | usb1: usb@47401800 { |
| 119 | compatible = "ti,musb-am33xx"; |
| 120 | reg = <0x47401c00 0x400 |
| 121 | 0x47401800 0x200>; |
| 122 | reg-names = "mc", "control"; |
| 123 | interrupts = <19>; |
| 124 | interrupt-names = "mc"; |
| 125 | dr_mode = "otg"; |
| 126 | mentor,multipoint = <1>; |
| 127 | mentor,num-eps = <16>; |
| 128 | mentor,ram-bits = <12>; |
| 129 | mentor,power = <500>; |
| 130 | phys = <&usb1_phy>; |
| 131 | |
| 132 | dmas = <&cppi41dma 15 0 &cppi41dma 16 0 |
| 133 | &cppi41dma 17 0 &cppi41dma 18 0 |
| 134 | &cppi41dma 19 0 &cppi41dma 20 0 |
| 135 | &cppi41dma 21 0 &cppi41dma 22 0 |
| 136 | &cppi41dma 23 0 &cppi41dma 24 0 |
| 137 | &cppi41dma 25 0 &cppi41dma 26 0 |
| 138 | &cppi41dma 27 0 &cppi41dma 28 0 |
| 139 | &cppi41dma 29 0 &cppi41dma 15 1 |
| 140 | &cppi41dma 16 1 &cppi41dma 17 1 |
| 141 | &cppi41dma 18 1 &cppi41dma 19 1 |
| 142 | &cppi41dma 20 1 &cppi41dma 21 1 |
| 143 | &cppi41dma 22 1 &cppi41dma 23 1 |
| 144 | &cppi41dma 24 1 &cppi41dma 25 1 |
| 145 | &cppi41dma 26 1 &cppi41dma 27 1 |
| 146 | &cppi41dma 28 1 &cppi41dma 29 1>; |
| 147 | dma-names = |
| 148 | "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", |
| 149 | "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", |
| 150 | "rx14", "rx15", |
| 151 | "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", |
| 152 | "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", |
| 153 | "tx14", "tx15"; |
| 154 | }; |
| 155 | |
| 156 | cppi41dma: dma-controller@47402000 { |
| 157 | compatible = "ti,am3359-cppi41"; |
| 158 | reg = <0x47400000 0x1000 |
| 159 | 0x47402000 0x1000 |
| 160 | 0x47403000 0x1000 |
| 161 | 0x47404000 0x4000>; |
| 162 | reg-names = "glue", "controller", "scheduler", "queuemgr"; |
| 163 | interrupts = <17>; |
| 164 | interrupt-names = "glue"; |
| 165 | #dma-cells = <2>; |
| 166 | /* For backwards compatibility: */ |
| 167 | #dma-channels = <30>; |
| 168 | dma-channels = <30>; |
| 169 | #dma-requests = <256>; |
| 170 | dma-requests = <256>; |
| 171 | }; |
| 172 | }; |
| 173 | |
| 174 | /* |
| 175 | * See TRM "Table 1-317. L4LS Instance Summary" for hints. |
| 176 | * It shows the module target agent registers though, so the |
| 177 | * actual device is typically 0x1000 before the target agent |
| 178 | * except in cases where the module is larger than 0x1000. |
| 179 | */ |
| 180 | l4ls: l4ls@48000000 { |
| 181 | compatible = "ti,dm814-l4ls", "simple-bus"; |
| 182 | #address-cells = <1>; |
| 183 | #size-cells = <1>; |
| 184 | ranges = <0 0x48000000 0x2000000>; |
| 185 | |
| 186 | i2c1: i2c@28000 { |
| 187 | compatible = "ti,omap4-i2c"; |
| 188 | #address-cells = <1>; |
| 189 | #size-cells = <0>; |
| 190 | ti,hwmods = "i2c1"; |
| 191 | reg = <0x28000 0x1000>; |
| 192 | interrupts = <70>; |
| 193 | }; |
| 194 | |
| 195 | elm: elm@80000 { |
| 196 | compatible = "ti,814-elm"; |
| 197 | ti,hwmods = "elm"; |
| 198 | reg = <0x80000 0x2000>; |
| 199 | interrupts = <4>; |
| 200 | }; |
| 201 | |
| 202 | gpio1: gpio@32000 { |
| 203 | compatible = "ti,omap4-gpio"; |
| 204 | ti,hwmods = "gpio1"; |
| 205 | ti,gpio-always-on; |
| 206 | reg = <0x32000 0x2000>; |
| 207 | interrupts = <96>; |
| 208 | gpio-controller; |
| 209 | #gpio-cells = <2>; |
| 210 | interrupt-controller; |
| 211 | #interrupt-cells = <2>; |
| 212 | }; |
| 213 | |
| 214 | gpio2: gpio@4c000 { |
| 215 | compatible = "ti,omap4-gpio"; |
| 216 | ti,hwmods = "gpio2"; |
| 217 | ti,gpio-always-on; |
| 218 | reg = <0x4c000 0x2000>; |
| 219 | interrupts = <98>; |
| 220 | gpio-controller; |
| 221 | #gpio-cells = <2>; |
| 222 | interrupt-controller; |
| 223 | #interrupt-cells = <2>; |
| 224 | }; |
| 225 | |
| 226 | gpio3: gpio@1ac000 { |
| 227 | compatible = "ti,omap4-gpio"; |
| 228 | ti,hwmods = "gpio3"; |
| 229 | ti,gpio-always-on; |
| 230 | reg = <0x1ac000 0x2000>; |
| 231 | interrupts = <32>; |
| 232 | gpio-controller; |
| 233 | #gpio-cells = <2>; |
| 234 | interrupt-controller; |
| 235 | #interrupt-cells = <2>; |
| 236 | }; |
| 237 | |
| 238 | gpio4: gpio@1ae000 { |
| 239 | compatible = "ti,omap4-gpio"; |
| 240 | ti,hwmods = "gpio4"; |
| 241 | ti,gpio-always-on; |
| 242 | reg = <0x1ae000 0x2000>; |
| 243 | interrupts = <62>; |
| 244 | gpio-controller; |
| 245 | #gpio-cells = <2>; |
| 246 | interrupt-controller; |
| 247 | #interrupt-cells = <2>; |
| 248 | }; |
| 249 | |
| 250 | i2c2: i2c@2a000 { |
| 251 | compatible = "ti,omap4-i2c"; |
| 252 | #address-cells = <1>; |
| 253 | #size-cells = <0>; |
| 254 | ti,hwmods = "i2c2"; |
| 255 | reg = <0x2a000 0x1000>; |
| 256 | interrupts = <71>; |
| 257 | }; |
| 258 | |
| 259 | mcspi1: spi@30000 { |
| 260 | compatible = "ti,omap4-mcspi"; |
| 261 | reg = <0x30000 0x1000>; |
| 262 | #address-cells = <1>; |
| 263 | #size-cells = <0>; |
| 264 | interrupts = <65>; |
| 265 | ti,spi-num-cs = <4>; |
| 266 | ti,hwmods = "mcspi1"; |
| 267 | dmas = <&edma 16 0 &edma 17 0 |
| 268 | &edma 18 0 &edma 19 0 |
| 269 | &edma 20 0 &edma 21 0 |
| 270 | &edma 22 0 &edma 23 0>; |
| 271 | |
| 272 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 273 | "tx2", "rx2", "tx3", "rx3"; |
| 274 | }; |
| 275 | |
| 276 | mcspi2: spi@1a0000 { |
| 277 | compatible = "ti,omap4-mcspi"; |
| 278 | reg = <0x1a0000 0x1000>; |
| 279 | #address-cells = <1>; |
| 280 | #size-cells = <0>; |
| 281 | interrupts = <125>; |
| 282 | ti,spi-num-cs = <4>; |
| 283 | ti,hwmods = "mcspi2"; |
| 284 | dmas = <&edma 42 0 &edma 43 0 |
| 285 | &edma 44 0 &edma 45 0>; |
| 286 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 287 | }; |
| 288 | |
| 289 | /* Board must configure dmas with edma_xbar for EDMA */ |
| 290 | mcspi3: spi@1a2000 { |
| 291 | compatible = "ti,omap4-mcspi"; |
| 292 | reg = <0x1a2000 0x1000>; |
| 293 | #address-cells = <1>; |
| 294 | #size-cells = <0>; |
| 295 | interrupts = <126>; |
| 296 | ti,spi-num-cs = <4>; |
| 297 | ti,hwmods = "mcspi3"; |
| 298 | }; |
| 299 | |
| 300 | mcspi4: spi@1a4000 { |
| 301 | compatible = "ti,omap4-mcspi"; |
| 302 | reg = <0x1a4000 0x1000>; |
| 303 | #address-cells = <1>; |
| 304 | #size-cells = <0>; |
| 305 | interrupts = <127>; |
| 306 | ti,spi-num-cs = <4>; |
| 307 | ti,hwmods = "mcspi4"; |
| 308 | }; |
| 309 | |
| 310 | timer1_target: target-module@2e000 { |
| 311 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| 312 | reg = <0x2e000 0x4>, |
| 313 | <0x2e010 0x4>; |
| 314 | reg-names = "rev", "sysc"; |
| 315 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 316 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 317 | <SYSC_IDLE_NO>, |
| 318 | <SYSC_IDLE_SMART>, |
| 319 | <SYSC_IDLE_SMART_WKUP>; |
| 320 | clocks = <&timer1_fck>; |
| 321 | clock-names = "fck"; |
| 322 | #address-cells = <1>; |
| 323 | #size-cells = <1>; |
| 324 | ranges = <0x0 0x2e000 0x1000>; |
| 325 | |
| 326 | timer1: timer@0 { |
| 327 | compatible = "ti,am335x-timer-1ms"; |
| 328 | reg = <0x0 0x400>; |
| 329 | interrupts = <67>; |
| 330 | ti,timer-alwon; |
| 331 | clocks = <&timer1_fck>; |
| 332 | clock-names = "fck"; |
| 333 | }; |
| 334 | }; |
| 335 | |
| 336 | uart1: serial@20000 { |
| 337 | compatible = "ti,am3352-uart", "ti,omap3-uart"; |
| 338 | ti,hwmods = "uart1"; |
| 339 | reg = <0x20000 0x2000>; |
| 340 | clock-frequency = <48000000>; |
| 341 | interrupts = <72>; |
| 342 | dmas = <&edma 26 0 &edma 27 0>; |
| 343 | dma-names = "tx", "rx"; |
| 344 | }; |
| 345 | |
| 346 | uart2: serial@22000 { |
| 347 | compatible = "ti,am3352-uart", "ti,omap3-uart"; |
| 348 | ti,hwmods = "uart2"; |
| 349 | reg = <0x22000 0x2000>; |
| 350 | clock-frequency = <48000000>; |
| 351 | interrupts = <73>; |
| 352 | dmas = <&edma 28 0 &edma 29 0>; |
| 353 | dma-names = "tx", "rx"; |
| 354 | }; |
| 355 | |
| 356 | uart3: serial@24000 { |
| 357 | compatible = "ti,am3352-uart", "ti,omap3-uart"; |
| 358 | ti,hwmods = "uart3"; |
| 359 | reg = <0x24000 0x2000>; |
| 360 | clock-frequency = <48000000>; |
| 361 | interrupts = <74>; |
| 362 | dmas = <&edma 30 0 &edma 31 0>; |
| 363 | dma-names = "tx", "rx"; |
| 364 | }; |
| 365 | |
| 366 | timer2_target: target-module@40000 { |
| 367 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; |
| 368 | reg = <0x40000 0x4>, |
| 369 | <0x40010 0x4>; |
| 370 | reg-names = "rev", "sysc"; |
| 371 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 372 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 373 | <SYSC_IDLE_NO>, |
| 374 | <SYSC_IDLE_SMART>, |
| 375 | <SYSC_IDLE_SMART_WKUP>; |
| 376 | clocks = <&timer2_fck>; |
| 377 | clock-names = "fck"; |
| 378 | #address-cells = <1>; |
| 379 | #size-cells = <1>; |
| 380 | ranges = <0x0 0x40000 0x1000>; |
| 381 | |
| 382 | timer2: timer@0 { |
| 383 | compatible = "ti,dm814-timer"; |
| 384 | reg = <0 0x1000>; |
| 385 | interrupts = <68>; |
| 386 | clocks = <&timer2_fck>; |
| 387 | clock-names = "fck"; |
| 388 | }; |
| 389 | }; |
| 390 | |
| 391 | timer3: timer@42000 { |
| 392 | compatible = "ti,dm814-timer"; |
| 393 | reg = <0x42000 0x2000>; |
| 394 | interrupts = <69>; |
| 395 | ti,hwmods = "timer3"; |
| 396 | }; |
| 397 | |
| 398 | mmc1: mmc@60000 { |
| 399 | compatible = "ti,omap4-hsmmc"; |
| 400 | ti,hwmods = "mmc1"; |
| 401 | dmas = <&edma 24 0 |
| 402 | &edma 25 0>; |
| 403 | dma-names = "tx", "rx"; |
| 404 | interrupts = <64>; |
| 405 | interrupt-parent = <&intc>; |
| 406 | reg = <0x60000 0x1000>; |
| 407 | }; |
| 408 | |
| 409 | rtc: rtc@c0000 { |
| 410 | compatible = "ti,am3352-rtc", "ti,da830-rtc"; |
| 411 | reg = <0xc0000 0x1000>; |
| 412 | interrupts = <75 76>; |
| 413 | ti,hwmods = "rtc"; |
| 414 | }; |
| 415 | |
| 416 | mmc2: mmc@1d8000 { |
| 417 | compatible = "ti,omap4-hsmmc"; |
| 418 | ti,hwmods = "mmc2"; |
| 419 | dmas = <&edma 2 0 |
| 420 | &edma 3 0>; |
| 421 | dma-names = "tx", "rx"; |
| 422 | interrupts = <28>; |
| 423 | interrupt-parent = <&intc>; |
| 424 | reg = <0x1d8000 0x1000>; |
| 425 | }; |
| 426 | |
| 427 | control: control@140000 { |
| 428 | compatible = "ti,dm814-scm", "simple-bus"; |
| 429 | reg = <0x140000 0x20000>; |
| 430 | #address-cells = <1>; |
| 431 | #size-cells = <1>; |
| 432 | ranges = <0 0x140000 0x20000>; |
| 433 | |
| 434 | scm_conf: scm_conf@0 { |
| 435 | compatible = "syscon", "simple-bus"; |
| 436 | reg = <0x0 0x800>; |
| 437 | #address-cells = <1>; |
| 438 | #size-cells = <1>; |
| 439 | ranges = <0 0 0x800>; |
| 440 | |
| 441 | phy_gmii_sel: phy-gmii-sel { |
| 442 | compatible = "ti,dm814-phy-gmii-sel"; |
| 443 | reg = <0x650 0x4>; |
| 444 | #phy-cells = <1>; |
| 445 | }; |
| 446 | |
| 447 | scm_clocks: clocks { |
| 448 | #address-cells = <1>; |
| 449 | #size-cells = <0>; |
| 450 | }; |
| 451 | |
| 452 | scm_clockdomains: clockdomains { |
| 453 | }; |
| 454 | }; |
| 455 | |
| 456 | usb_ctrl_mod: control@620 { |
| 457 | compatible = "ti,am335x-usb-ctrl-module"; |
| 458 | reg = <0x620 0x10 |
| 459 | 0x648 0x4>; |
| 460 | reg-names = "phy_ctrl", "wakeup"; |
| 461 | }; |
| 462 | |
| 463 | edma_xbar: dma-router@f90 { |
| 464 | compatible = "ti,am335x-edma-crossbar"; |
| 465 | reg = <0xf90 0x40>; |
| 466 | #dma-cells = <3>; |
| 467 | dma-requests = <32>; |
| 468 | dma-masters = <&edma>; |
| 469 | }; |
| 470 | |
| 471 | /* |
| 472 | * Note that silicon revision 2.1 and older |
| 473 | * require input enabled (bit 18 set) for all |
| 474 | * 3.3V I/Os to avoid cumulative hardware damage. |
| 475 | * For more info, see errata advisory 2.1.87. |
| 476 | * We leave bit 18 out of function-mask and rely |
| 477 | * on the bootloader for it. |
| 478 | */ |
| 479 | pincntl: pinmux@800 { |
| 480 | compatible = "pinctrl-single"; |
| 481 | reg = <0x800 0x438>; |
| 482 | #address-cells = <1>; |
| 483 | #size-cells = <0>; |
| 484 | #pinctrl-cells = <1>; |
| 485 | pinctrl-single,register-width = <32>; |
| 486 | pinctrl-single,function-mask = <0x307ff>; |
| 487 | }; |
| 488 | |
| 489 | usb1_phy: usb-phy@1b00 { |
| 490 | compatible = "ti,am335x-usb-phy"; |
| 491 | reg = <0x1b00 0x100>; |
| 492 | reg-names = "phy"; |
| 493 | ti,ctrl_mod = <&usb_ctrl_mod>; |
| 494 | #phy-cells = <0>; |
| 495 | }; |
| 496 | }; |
| 497 | |
| 498 | prcm: prcm@180000 { |
| 499 | compatible = "ti,dm814-prcm", "simple-bus"; |
| 500 | reg = <0x180000 0x2000>; |
| 501 | #address-cells = <1>; |
| 502 | #size-cells = <1>; |
| 503 | ranges = <0 0x180000 0x2000>; |
| 504 | |
| 505 | prcm_clocks: clocks { |
| 506 | #address-cells = <1>; |
| 507 | #size-cells = <0>; |
| 508 | }; |
| 509 | |
| 510 | prcm_clockdomains: clockdomains { |
| 511 | }; |
| 512 | }; |
| 513 | |
| 514 | /* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */ |
| 515 | pllss: pllss@1c5000 { |
| 516 | compatible = "ti,dm814-pllss", "simple-bus"; |
| 517 | reg = <0x1c5000 0x1000>; |
| 518 | #address-cells = <1>; |
| 519 | #size-cells = <1>; |
| 520 | ranges = <0 0x1c5000 0x1000>; |
| 521 | |
| 522 | pllss_clocks: clocks { |
| 523 | #address-cells = <1>; |
| 524 | #size-cells = <0>; |
| 525 | }; |
| 526 | |
| 527 | pllss_clockdomains: clockdomains { |
| 528 | }; |
| 529 | }; |
| 530 | |
| 531 | wdt1: wdt@1c7000 { |
| 532 | compatible = "ti,omap3-wdt"; |
| 533 | ti,hwmods = "wd_timer"; |
| 534 | reg = <0x1c7000 0x1000>; |
| 535 | interrupts = <91>; |
| 536 | }; |
| 537 | }; |
| 538 | |
| 539 | intc: interrupt-controller@48200000 { |
| 540 | compatible = "ti,dm814-intc"; |
| 541 | interrupt-controller; |
| 542 | #interrupt-cells = <1>; |
| 543 | reg = <0x48200000 0x1000>; |
| 544 | }; |
| 545 | |
| 546 | /* Board must configure evtmux with edma_xbar for EDMA */ |
| 547 | mmc3: mmc@47810000 { |
| 548 | compatible = "ti,omap4-hsmmc"; |
| 549 | ti,hwmods = "mmc3"; |
| 550 | interrupts = <29>; |
| 551 | interrupt-parent = <&intc>; |
| 552 | reg = <0x47810000 0x1000>; |
| 553 | }; |
| 554 | |
| 555 | target-module@49000000 { |
| 556 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 557 | reg = <0x49000000 0x4>; |
| 558 | reg-names = "rev"; |
| 559 | clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>; |
| 560 | clock-names = "fck"; |
| 561 | #address-cells = <1>; |
| 562 | #size-cells = <1>; |
| 563 | ranges = <0x0 0x49000000 0x10000>; |
| 564 | |
| 565 | edma: dma@0 { |
| 566 | compatible = "ti,edma3-tpcc"; |
| 567 | reg = <0 0x10000>; |
| 568 | reg-names = "edma3_cc"; |
| 569 | interrupts = <12 13 14>; |
| 570 | interrupt-names = "edma3_ccint", "edma3_mperr", |
| 571 | "edma3_ccerrint"; |
| 572 | dma-requests = <64>; |
| 573 | #dma-cells = <2>; |
| 574 | |
| 575 | ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, |
| 576 | <&edma_tptc2 3>, <&edma_tptc3 0>; |
| 577 | |
| 578 | ti,edma-memcpy-channels = <20 21>; |
| 579 | }; |
| 580 | }; |
| 581 | |
| 582 | target-module@49800000 { |
| 583 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 584 | reg = <0x49800000 0x4>, |
| 585 | <0x49800010 0x4>; |
| 586 | reg-names = "rev", "sysc"; |
| 587 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 588 | ti,sysc-midle = <SYSC_IDLE_FORCE>; |
| 589 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 590 | <SYSC_IDLE_SMART>; |
| 591 | clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>; |
| 592 | clock-names = "fck"; |
| 593 | #address-cells = <1>; |
| 594 | #size-cells = <1>; |
| 595 | ranges = <0x0 0x49800000 0x100000>; |
| 596 | |
| 597 | edma_tptc0: dma@0 { |
| 598 | compatible = "ti,edma3-tptc"; |
| 599 | reg = <0 0x100000>; |
| 600 | interrupts = <112>; |
| 601 | interrupt-names = "edma3_tcerrint"; |
| 602 | }; |
| 603 | }; |
| 604 | |
| 605 | target-module@49900000 { |
| 606 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 607 | reg = <0x49900000 0x4>, |
| 608 | <0x49900010 0x4>; |
| 609 | reg-names = "rev", "sysc"; |
| 610 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 611 | ti,sysc-midle = <SYSC_IDLE_FORCE>; |
| 612 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 613 | <SYSC_IDLE_SMART>; |
| 614 | clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>; |
| 615 | clock-names = "fck"; |
| 616 | #address-cells = <1>; |
| 617 | #size-cells = <1>; |
| 618 | ranges = <0x0 0x49900000 0x100000>; |
| 619 | |
| 620 | edma_tptc1: dma@0 { |
| 621 | compatible = "ti,edma3-tptc"; |
| 622 | reg = <0 0x100000>; |
| 623 | interrupts = <113>; |
| 624 | interrupt-names = "edma3_tcerrint"; |
| 625 | }; |
| 626 | }; |
| 627 | |
| 628 | target-module@49a00000 { |
| 629 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 630 | reg = <0x49a00000 0x4>, |
| 631 | <0x49a00010 0x4>; |
| 632 | reg-names = "rev", "sysc"; |
| 633 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 634 | ti,sysc-midle = <SYSC_IDLE_FORCE>; |
| 635 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 636 | <SYSC_IDLE_SMART>; |
| 637 | clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>; |
| 638 | clock-names = "fck"; |
| 639 | #address-cells = <1>; |
| 640 | #size-cells = <1>; |
| 641 | ranges = <0x0 0x49a00000 0x100000>; |
| 642 | |
| 643 | edma_tptc2: dma@0 { |
| 644 | compatible = "ti,edma3-tptc"; |
| 645 | reg = <0 0x100000>; |
| 646 | interrupts = <114>; |
| 647 | interrupt-names = "edma3_tcerrint"; |
| 648 | }; |
| 649 | }; |
| 650 | |
| 651 | target-module@49b00000 { |
| 652 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 653 | reg = <0x49b00000 0x4>, |
| 654 | <0x49b00010 0x4>; |
| 655 | reg-names = "rev", "sysc"; |
| 656 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 657 | ti,sysc-midle = <SYSC_IDLE_FORCE>; |
| 658 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 659 | <SYSC_IDLE_SMART>; |
| 660 | clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>; |
| 661 | clock-names = "fck"; |
| 662 | #address-cells = <1>; |
| 663 | #size-cells = <1>; |
| 664 | ranges = <0x0 0x49b00000 0x100000>; |
| 665 | |
| 666 | edma_tptc3: dma@0 { |
| 667 | compatible = "ti,edma3-tptc"; |
| 668 | reg = <0 0x100000>; |
| 669 | interrupts = <115>; |
| 670 | interrupt-names = "edma3_tcerrint"; |
| 671 | }; |
| 672 | }; |
| 673 | |
| 674 | /* See TRM "Table 1-318. L4HS Instance Summary" */ |
| 675 | l4hs: l4hs@4a000000 { |
| 676 | compatible = "ti,dm814-l4hs", "simple-bus"; |
| 677 | #address-cells = <1>; |
| 678 | #size-cells = <1>; |
| 679 | ranges = <0 0x4a000000 0x1b4040>; |
| 680 | |
| 681 | target-module@100000 { |
| 682 | compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
| 683 | reg = <0x100900 0x4>, |
| 684 | <0x100908 0x4>, |
| 685 | <0x100904 0x4>; |
| 686 | reg-names = "rev", "sysc", "syss"; |
| 687 | ti,sysc-mask = <0>; |
| 688 | ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| 689 | <SYSC_IDLE_NO>; |
| 690 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 691 | <SYSC_IDLE_NO>; |
| 692 | ti,syss-mask = <1>; |
| 693 | clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>; |
| 694 | clock-names = "fck"; |
| 695 | #address-cells = <1>; |
| 696 | #size-cells = <1>; |
| 697 | ranges = <0 0x100000 0x8000>; |
| 698 | |
| 699 | mac: ethernet@0 { |
| 700 | compatible = "ti,cpsw"; |
| 701 | clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; |
| 702 | clock-names = "fck", "cpts"; |
| 703 | cpdma_channels = <8>; |
| 704 | ale_entries = <1024>; |
| 705 | bd_ram_size = <0x2000>; |
| 706 | mac_control = <0x20>; |
| 707 | slaves = <2>; |
| 708 | active_slave = <0>; |
| 709 | cpts_clock_mult = <0x80000000>; |
| 710 | cpts_clock_shift = <29>; |
| 711 | reg = <0 0x800>, |
| 712 | <0x900 0x100>; |
| 713 | #address-cells = <1>; |
| 714 | #size-cells = <1>; |
| 715 | /* |
| 716 | * c0_rx_thresh_pend |
| 717 | * c0_rx_pend |
| 718 | * c0_tx_pend |
| 719 | * c0_misc_pend |
| 720 | */ |
| 721 | interrupts = <40 41 42 43>; |
| 722 | ranges = <0 0 0x8000>; |
| 723 | syscon = <&scm_conf>; |
| 724 | |
| 725 | davinci_mdio: mdio@800 { |
| 726 | compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; |
| 727 | clocks = <&cpsw_125mhz_gclk>; |
| 728 | clock-names = "fck"; |
| 729 | #address-cells = <1>; |
| 730 | #size-cells = <0>; |
| 731 | bus_freq = <1000000>; |
| 732 | reg = <0x800 0x100>; |
| 733 | }; |
| 734 | |
| 735 | cpsw_emac0: slave@200 { |
| 736 | /* Filled in by U-Boot */ |
| 737 | mac-address = [ 00 00 00 00 00 00 ]; |
| 738 | phys = <&phy_gmii_sel 1>; |
| 739 | }; |
| 740 | |
| 741 | cpsw_emac1: slave@300 { |
| 742 | /* Filled in by U-Boot */ |
| 743 | mac-address = [ 00 00 00 00 00 00 ]; |
| 744 | phys = <&phy_gmii_sel 2>; |
| 745 | }; |
| 746 | }; |
| 747 | }; |
| 748 | }; |
| 749 | |
| 750 | gpmc: gpmc@50000000 { |
| 751 | compatible = "ti,am3352-gpmc"; |
| 752 | ti,hwmods = "gpmc"; |
| 753 | ti,no-idle-on-init; |
| 754 | reg = <0x50000000 0x2000>; |
| 755 | interrupts = <100>; |
| 756 | gpmc,num-cs = <7>; |
| 757 | gpmc,num-waitpins = <2>; |
| 758 | #address-cells = <2>; |
| 759 | #size-cells = <1>; |
| 760 | interrupt-controller; |
| 761 | #interrupt-cells = <2>; |
| 762 | gpio-controller; |
| 763 | #gpio-cells = <2>; |
| 764 | }; |
| 765 | }; |
| 766 | }; |
| 767 | |
| 768 | #include "dm814x-clocks.dtsi" |
| 769 | |
| 770 | /* Preferred always-on timer for clocksource */ |
| 771 | &timer1_target { |
| 772 | ti,no-reset-on-init; |
| 773 | ti,no-idle; |
| 774 | timer@0 { |
| 775 | assigned-clocks = <&timer1_fck>; |
| 776 | assigned-clock-parents = <&devosc_ck>; |
| 777 | }; |
| 778 | }; |
| 779 | |
| 780 | /* Preferred timer for clockevent */ |
| 781 | &timer2_target { |
| 782 | ti,no-reset-on-init; |
| 783 | ti,no-idle; |
| 784 | timer@0 { |
| 785 | assigned-clocks = <&timer2_fck>; |
| 786 | assigned-clock-parents = <&devosc_ck>; |
| 787 | }; |
| 788 | }; |