| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Microsemi/Microchip Serial GPIO controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Lars Povlsen <lars.povlsen@microchip.com> |
| 11 | |
| 12 | description: | |
| 13 | By using a serial interface, the SIO controller significantly extend |
| 14 | the number of available GPIOs with a minimum number of additional |
| 15 | pins on the device. The primary purpose of the SIO controllers is to |
| 16 | connect control signals from SFP modules and to act as an LED |
| 17 | controller. |
| 18 | |
| 19 | properties: |
| 20 | $nodename: |
| 21 | pattern: "^gpio@[0-9a-f]+$" |
| 22 | |
| 23 | compatible: |
| 24 | enum: |
| 25 | - microchip,sparx5-sgpio |
| 26 | - mscc,ocelot-sgpio |
| 27 | - mscc,luton-sgpio |
| 28 | |
| 29 | "#address-cells": |
| 30 | const: 1 |
| 31 | |
| 32 | "#size-cells": |
| 33 | const: 0 |
| 34 | |
| 35 | reg: |
| 36 | maxItems: 1 |
| 37 | |
| 38 | clocks: |
| 39 | maxItems: 1 |
| 40 | |
| 41 | microchip,sgpio-port-ranges: |
| 42 | description: This is a sequence of tuples, defining intervals of |
| 43 | enabled ports in the serial input stream. The enabled ports must |
| 44 | match the hardware configuration in order for signals to be |
| 45 | properly written/read to/from the controller holding |
| 46 | registers. Being tuples, then number of arguments must be |
| 47 | even. The tuples mast be ordered (low, high) and are |
| 48 | inclusive. |
| 49 | $ref: /schemas/types.yaml#/definitions/uint32-matrix |
| 50 | items: |
| 51 | items: |
| 52 | - description: | |
| 53 | "low" indicates start bit number of range |
| 54 | minimum: 0 |
| 55 | maximum: 31 |
| 56 | - description: | |
| 57 | "high" indicates end bit number of range |
| 58 | minimum: 0 |
| 59 | maximum: 31 |
| 60 | minItems: 1 |
| 61 | maxItems: 32 |
| 62 | |
| 63 | bus-frequency: |
| 64 | description: The sgpio controller frequency (Hz). This dictates |
| 65 | the serial bitstream speed, which again affects the latency in |
| 66 | getting control signals back and forth between external shift |
| 67 | registers. The speed must be no larger than half the system |
| 68 | clock, and larger than zero. |
| 69 | default: 12500000 |
| 70 | |
| 71 | resets: |
| 72 | maxItems: 1 |
| 73 | |
| 74 | reset-names: |
| 75 | items: |
| 76 | - const: switch |
| 77 | |
| 78 | patternProperties: |
| 79 | "^gpio@[0-1]$": |
| 80 | type: object |
| 81 | properties: |
| 82 | compatible: |
| 83 | const: microchip,sparx5-sgpio-bank |
| 84 | |
| 85 | reg: |
| 86 | description: | |
| 87 | The GPIO bank number. "0" is designates the input pin bank, |
| 88 | "1" the output bank. |
| 89 | maxItems: 1 |
| 90 | |
| 91 | gpio-controller: true |
| 92 | |
| 93 | '#gpio-cells': |
| 94 | description: | |
| 95 | Specifies the pin (port and bit) and flags. Note that the |
| 96 | SGIO pin is defined by *2* numbers, a port number between 0 |
| 97 | and 31, and a bit index, 0 to 3. The maximum bit number is |
| 98 | controlled indirectly by the "ngpios" property: (ngpios/32). |
| 99 | const: 3 |
| 100 | |
| 101 | interrupts: |
| 102 | description: Specifies the sgpio IRQ (in parent controller) |
| 103 | maxItems: 1 |
| 104 | |
| 105 | interrupt-controller: true |
| 106 | |
| 107 | '#interrupt-cells': |
| 108 | description: |
| 109 | Specifies the pin (port and bit) and flags, as defined in |
| 110 | defined in include/dt-bindings/interrupt-controller/irq.h |
| 111 | const: 3 |
| 112 | |
| 113 | ngpios: |
| 114 | description: The numbers of GPIO's exposed. This must be a |
| 115 | multiple of 32. |
| 116 | minimum: 32 |
| 117 | maximum: 128 |
| 118 | |
| 119 | required: |
| 120 | - compatible |
| 121 | - reg |
| 122 | - gpio-controller |
| 123 | - '#gpio-cells' |
| 124 | - ngpios |
| 125 | |
| 126 | additionalProperties: false |
| 127 | |
| 128 | additionalProperties: false |
| 129 | |
| 130 | required: |
| 131 | - compatible |
| 132 | - reg |
| 133 | - clocks |
| 134 | - microchip,sgpio-port-ranges |
| 135 | - "#address-cells" |
| 136 | - "#size-cells" |
| 137 | |
| 138 | examples: |
| 139 | - | |
| 140 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 141 | sgpio2: gpio@1101059c { |
| 142 | #address-cells = <1>; |
| 143 | #size-cells = <0>; |
| 144 | compatible = "microchip,sparx5-sgpio"; |
| 145 | clocks = <&sys_clk>; |
| 146 | pinctrl-0 = <&sgpio2_pins>; |
| 147 | pinctrl-names = "default"; |
| 148 | reg = <0x1101059c 0x118>; |
| 149 | microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; |
| 150 | bus-frequency = <25000000>; |
| 151 | sgpio_in2: gpio@0 { |
| 152 | reg = <0>; |
| 153 | compatible = "microchip,sparx5-sgpio-bank"; |
| 154 | gpio-controller; |
| 155 | #gpio-cells = <3>; |
| 156 | ngpios = <96>; |
| 157 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 158 | interrupt-controller; |
| 159 | #interrupt-cells = <3>; |
| 160 | }; |
| 161 | sgpio_out2: gpio@1 { |
| 162 | compatible = "microchip,sparx5-sgpio-bank"; |
| 163 | reg = <1>; |
| 164 | gpio-controller; |
| 165 | #gpio-cells = <3>; |
| 166 | ngpios = <96>; |
| 167 | }; |
| 168 | }; |