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git01.mediatek.com / filogic / uboot / a03cb92688346145a51229f3467fe208c0ad6d9e / . / dts / upstream / Bindings / pinctrl / mediatek,mt7981-pinctrl.yaml
blob: 74d52a741f6f417230272517cab7a3ead83899c9 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek MT7981 Pin Controller
8
9maintainers:
10 - Daniel Golle <daniel@makrotopia.org>
11
12description:
13 The MediaTek's MT7981 Pin controller is used to control SoC pins.
14
15properties:
16 compatible:
17 enum:
18 - mediatek,mt7981-pinctrl
19
20 reg:
21 minItems: 9
22 maxItems: 9
23
24 reg-names:
25 items:
26 - const: gpio
27 - const: iocfg_rt
28 - const: iocfg_rm
29 - const: iocfg_rb
30 - const: iocfg_lb
31 - const: iocfg_bl
32 - const: iocfg_tm
33 - const: iocfg_tl
34 - const: eint
35
36 gpio-controller: true
37
38 "#gpio-cells":
39 const: 2
40 description:
41 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
42 the amount of cells must be specified as 2. See the below mentioned gpio
43 binding representation for description of particular cells.
44
45 gpio-ranges:
46 minItems: 1
47 maxItems: 5
48 description: GPIO valid number range.
49
50 interrupt-controller: true
51
52 interrupts:
53 maxItems: 1
54
55 "#interrupt-cells":
56 const: 2
57
58allOf:
59 - $ref: pinctrl.yaml#
60
61required:
62 - compatible
63 - reg
64 - reg-names
65 - gpio-controller
66 - "#gpio-cells"
67
68patternProperties:
69 '-pins$':
70 type: object
71 additionalProperties: false
72
73 patternProperties:
74 '^.*mux.*$':
75 type: object
76 additionalProperties: false
77 description: |
78 pinmux configuration nodes.
79
80 The following table shows the effective values of "group", "function"
81 properties and chip pinout pins
82
83 groups function pins (in pin#)
84 ---------------------------------------------------------------------
85 "wa_aice1" "wa_aice" 0, 1
86 "wa_aice2" "wa_aice" 0, 1
87 "wm_uart_0" "uart" 0, 1
88 "dfd" "dfd" 0, 1, 4, 5
89 "watchdog" "watchdog" 2
90 "pcie_pereset" "pcie" 3
91 "jtag" "jtag" 4, 5, 6, 7, 8
92 "wm_jtag_0" "jtag" 4, 5, 6, 7, 8
93 "wo0_jtag_0" "jtag" 9, 10, 11, 12, 13
94 "uart2_0" "uart" 4, 5, 6, 7
95 "gbe_led0" "led" 8
96 "pta_ext_0" "pta" 4, 5, 6
97 "pwm2" "pwm" 7
98 "net_wo0_uart_txd_0" "uart" 8
99 "spi1_0" "spi" 4, 5, 6, 7
100 "i2c0_0" "i2c" 6, 7
101 "dfd_ntrst" "dfd" 8
102 "wm_aice1" "wa_aice" 9, 10
103 "pwm0_0" "pwm" 13
104 "pwm0_1" "pwm" 15
105 "pwm1_0" "pwm" 14
106 "pwm1_1" "pwm" 15
107 "net_wo0_uart_txd_1" "uart" 14
108 "net_wo0_uart_txd_2" "uart" 15
109 "gbe_led1" "led" 13
110 "pcm" "pcm" 9, 10, 11, 12, 13, 25
111 "watchdog1" "watchdog" 13
112 "udi" "udi" 9, 10, 11, 12, 13
113 "drv_vbus" "usb" 14
114 "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23,
115 24, 25
116
117 "snfi" "flash" 16, 17, 18, 19, 20, 21
118 "spi0" "spi" 16, 17, 18, 19
119 "spi0_wp_hold" "spi" 20, 21
120 "spi1_1" "spi" 22, 23, 24, 25
121 "spi2" "spi" 26, 27, 28, 29
122 "spi2_wp_hold" "spi" 30, 31
123 "uart1_0" "uart" 16, 17, 18, 19
124 "uart1_1" "uart" 26, 27, 28, 29
125 "uart2_1" "uart" 22, 23, 24, 25
126 "pta_ext_1" "pta" 22, 23, 24
127 "wm_aurt_1" "uart" 20, 21
128 "wm_aurt_2" "uart" 30, 31
129 "wm_jtag_1" "jtag" 20, 21, 22, 23, 24
130 "wo0_jtag_1" "jtag" 25, 26, 27, 28, 29
131 "wa_aice3" "wa_aice" 28, 20
132 "wm_aice2" "wa_aice" 30, 31
133 "i2c0_1" "i2c" 30, 31
134 "u2_phy_i2c" "i2c" 30, 31
135 "uart0" "uart" 32, 33
136 "sgmii1_phy_i2c" "i2c" 32, 33
137 "u3_phy_i2c" "i2c" 32, 33
138 "sgmii0_phy_i2c" "i2c" 32, 33
139 "pcie_clk" "pcie" 34
140 "pcie_wake" "pcie" 35
141 "i2c0_2" "i2c" 36, 37
142 "smi_mdc_mdio" "eth" 36, 37
143 "gbe_ext_mdc_mdio" "eth" 36, 37
144 "wf0_mode1" "eth" 40, 41, 42, 43, 44, 45, 46, 47, 48,
145 49, 50, 51, 52, 53, 54, 55, 56
146
147 "wf0_mode3" "eth" 45, 46, 47, 48, 49, 51
148 "wf2g_led0" "led" 30
149 "wf2g_led1" "led" 34
150 "wf5g_led0" "led" 31
151 "wf5g_led1" "led" 35
152 "mt7531_int" "eth" 38
153 "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22,
154 23, 24, 25, 34, 35
155
156 $ref: /schemas/pinctrl/pinmux-node.yaml
157 properties:
158 function:
159 description:
160 A string containing the name of the function to mux to the group.
161 enum: [wa_aice, dfd, jtag, pta, pcm, udi, usb, ant, eth, i2c, led,
162 pwm, spi, uart, watchdog, flash, pcie]
163 groups:
164 description:
165 An array of strings. Each string contains the name of a group.
166
167 required:
168 - function
169 - groups
170
171 allOf:
172 - if:
173 properties:
174 function:
175 const: wa_aice
176 then:
177 properties:
178 groups:
179 enum: [wa_aice1, wa_aice2, wm_aice1_1, wa_aice3, wm_aice1_2]
180 - if:
181 properties:
182 function:
183 const: dfd
184 then:
185 properties:
186 groups:
187 enum: [dfd, dfd_ntrst]
188 - if:
189 properties:
190 function:
191 const: jtag
192 then:
193 properties:
194 groups:
195 enum: [jtag, wm_jtag_0, wo0_jtag_0, wo0_jtag_1, wm_jtag_1]
196 - if:
197 properties:
198 function:
199 const: pta
200 then:
201 properties:
202 groups:
203 enum: [pta_ext_0, pta_ext_1]
204 - if:
205 properties:
206 function:
207 const: pcm
208 then:
209 properties:
210 groups:
211 enum: [pcm]
212 - if:
213 properties:
214 function:
215 const: udi
216 then:
217 properties:
218 groups:
219 enum: [udi]
220 - if:
221 properties:
222 function:
223 const: usb
224 then:
225 properties:
226 groups:
227 enum: [drv_vbus]
228 - if:
229 properties:
230 function:
231 const: ant
232 then:
233 properties:
234 groups:
235 enum: [ant_sel]
236 - if:
237 properties:
238 function:
239 const: eth
240 then:
241 properties:
242 groups:
243 enum: [smi_mdc_mdio, gbe_ext_mdc_mdio, wf0_mode1, wf0_mode3,
244 mt7531_int]
245 - if:
246 properties:
247 function:
248 const: i2c
249 then:
250 properties:
251 groups:
252 enum: [i2c0_0, i2c0_1, u2_phy_i2c, sgmii1_phy_i2c, u3_phy_i2c,
253 sgmii0_phy_i2c, i2c0_2]
254 - if:
255 properties:
256 function:
257 const: led
258 then:
259 properties:
260 groups:
261 enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0,
262 wf5g_led1]
263 - if:
264 properties:
265 function:
266 const: pwm
267 then:
268 properties:
269 groups:
270 items:
271 enum: [pwm2, pwm0_0, pwm0_1, pwm1_0, pwm1_1]
272 maxItems: 3
273 - if:
274 properties:
275 function:
276 const: spi
277 then:
278 properties:
279 groups:
280 items:
281 enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2,
282 spi2_wp_hold]
283 maxItems: 4
284 - if:
285 properties:
286 function:
287 const: uart
288 then:
289 properties:
290 groups:
291 items:
292 enum: [wm_uart_0, uart2_0, net_wo0_uart_txd_0,
293 net_wo0_uart_txd_1, net_wo0_uart_txd_2, uart1_0,
294 uart1_1, uart2_1, wm_aurt_1, wm_aurt_2, uart0]
295 - if:
296 properties:
297 function:
298 const: watchdog
299 then:
300 properties:
301 groups:
302 enum: [watchdog]
303 - if:
304 properties:
305 function:
306 const: flash
307 then:
308 properties:
309 groups:
310 items:
311 enum: [emmc_45, snfi]
312 maxItems: 1
313 - if:
314 properties:
315 function:
316 const: pcie
317 then:
318 properties:
319 groups:
320 items:
321 enum: [pcie_clk, pcie_wake, pcie_pereset]
322 maxItems: 3
323
324 '^.*conf.*$':
325 type: object
326 additionalProperties: false
327 description: pinconf configuration nodes.
328 $ref: /schemas/pinctrl/pincfg-node.yaml
329
330 properties:
331 pins:
332 description:
333 An array of strings. Each string contains the name of a pin.
334 items:
335 enum: [GPIO_WPS, GPIO_RESET, SYS_WATCHDOG, PCIE_PERESET_N,
336 JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N,
337 WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK,
338 WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI,
339 SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK,
340 SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI,
341 SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD,
342 UART0_TXD, PCIE_CLK_REQ, PCIE_WAKE_N, SMI_MDC, SMI_MDIO,
343 GBE_INT, GBE_RESET, WF_DIG_RESETB, WF_CBA_RESETB,
344 WF_XO_REQ, WF_TOP_CLK, WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3,
345 WF_HB4, WF_HB0, WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8,
346 WF_HB9, WF_HB10]
347 maxItems: 57
348
349 bias-disable: true
350
351 bias-pull-up:
352 oneOf:
353 - type: boolean
354 description: normal pull up.
355 - enum: [100, 101, 102, 103]
356 description:
357 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
358 dt-bindings/pinctrl/mt65xx.h.
359
360 bias-pull-down:
361 oneOf:
362 - type: boolean
363 description: normal pull down.
364 - enum: [100, 101, 102, 103]
365 description:
366 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
367 dt-bindings/pinctrl/mt65xx.h.
368
369 input-enable: true
370
371 input-disable: true
372
373 output-enable: true
374
375 output-low: true
376
377 output-high: true
378
379 input-schmitt-enable: true
380
381 input-schmitt-disable: true
382
383 drive-strength:
384 enum: [2, 4, 6, 8, 10, 12, 14, 16]
385
386 mediatek,pull-up-adv:
387 description: |
388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
389 Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
390 are described as below:
391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
393 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
394 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
395 $ref: /schemas/types.yaml#/definitions/uint32
396 enum: [0, 1, 2, 3]
397
398 mediatek,pull-down-adv:
399 description: |
400 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
401 Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
402 are described as below:
403 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
404 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
405 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
406 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
407 $ref: /schemas/types.yaml#/definitions/uint32
408 enum: [0, 1, 2, 3]
409
410 required:
411 - pins
412
413additionalProperties: false
414
415examples:
416 - |
417 #include <dt-bindings/interrupt-controller/irq.h>
418 #include <dt-bindings/interrupt-controller/arm-gic.h>
419 #include <dt-bindings/pinctrl/mt65xx.h>
420
421 soc {
422 #address-cells = <2>;
423 #size-cells = <2>;
424 pio: pinctrl@11d00000 {
425 compatible = "mediatek,mt7981-pinctrl";
426 reg = <0 0x11d00000 0 0x1000>,
427 <0 0x11c00000 0 0x1000>,
428 <0 0x11c10000 0 0x1000>,
429 <0 0x11d20000 0 0x1000>,
430 <0 0x11e00000 0 0x1000>,
431 <0 0x11e20000 0 0x1000>,
432 <0 0x11f00000 0 0x1000>,
433 <0 0x11f10000 0 0x1000>,
434 <0 0x1000b000 0 0x1000>;
435 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
436 "iocfg_rb", "iocfg_lb", "iocfg_bl",
437 "iocfg_tm", "iocfg_tl", "eint";
438 gpio-controller;
439 #gpio-cells = <2>;
440 gpio-ranges = <&pio 0 0 56>;
441 interrupt-controller;
442 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-parent = <&gic>;
444 #interrupt-cells = <2>;
445
446 mdio_pins: mdio-pins {
447 mux {
448 function = "eth";
449 groups = "smi_mdc_mdio";
450 };
451 };
452
453 spi0_flash_pins: spi0-pins {
454 mux {
455 function = "spi";
456 groups = "spi0", "spi0_wp_hold";
457 };
458
459 conf-pu {
460 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
461 drive-strength = <MTK_DRIVE_8mA>;
462 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
463 };
464
465 conf-pd {
466 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
467 drive-strength = <MTK_DRIVE_8mA>;
468 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
469 };
470 };
471
472 pcie_pins: pcie-pins {
473 mux {
474 function = "pcie";
475 groups = "pcie_clk", "pcie_wake", "pcie_pereset";
476 };
477 };
478
479 };
480 };