blob: b0fbe86219d105f1ae472181ca5b104e5810d32b [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DPU on SC7280
8
9maintainers:
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12$ref: /schemas/display/msm/dpu-common.yaml#
13
14properties:
15 compatible:
16 const: qcom,sc7280-dpu
17
18 reg:
19 items:
20 - description: Address offset and size for mdp register set
21 - description: Address offset and size for vbif register set
22
23 reg-names:
24 items:
25 - const: mdp
26 - const: vbif
27
28 clocks:
29 items:
30 - description: Display hf axi clock
31 - description: Display sf axi clock
32 - description: Display ahb clock
33 - description: Display lut clock
34 - description: Display core clock
35 - description: Display vsync clock
36
37 clock-names:
38 items:
39 - const: bus
40 - const: nrt_bus
41 - const: iface
42 - const: lut
43 - const: core
44 - const: vsync
45
46required:
47 - compatible
48 - reg
49 - reg-names
50 - clocks
51 - clock-names
52
53unevaluatedProperties: false
54
55examples:
56 - |
57 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
58 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
59 #include <dt-bindings/power/qcom-rpmpd.h>
60
61 display-controller@ae01000 {
62 compatible = "qcom,sc7280-dpu";
63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
65
66 reg-names = "mdp", "vbif";
67
68 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
69 <&gcc GCC_DISP_SF_AXI_CLK>,
70 <&dispcc DISP_CC_MDSS_AHB_CLK>,
71 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
72 <&dispcc DISP_CC_MDSS_MDP_CLK>,
73 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
74 clock-names = "bus",
75 "nrt_bus",
76 "iface",
77 "lut",
78 "core",
79 "vsync";
80
81 interrupt-parent = <&mdss>;
82 interrupts = <0>;
83 power-domains = <&rpmhpd SC7280_CX>;
84 operating-points-v2 = <&mdp_opp_table>;
85
86 ports {
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 port@0 {
91 reg = <0>;
92 endpoint {
93 remote-endpoint = <&dsi0_in>;
94 };
95 };
96
97 port@1 {
98 reg = <1>;
99 endpoint {
100 remote-endpoint = <&edp_in>;
101 };
102 };
103 };
104 };
105...