Blame - drivers/ram/k3-j721e/lpddr4_pi_macros.h - filogic/uboot

Kevin Scholz

521a4ef

2019-10-07 19:26:36 +0530

[diff] [blame]

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/* SPDX-License-Identifier: BSD-3-Clause */

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/**********************************************************************

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*

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* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT

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*

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**********************************************************************

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*/

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#ifndef REG_LPDDR4_PI_MACROS_H_

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#define REG_LPDDR4_PI_MACROS_H_

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#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U

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#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U

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#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U

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#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U

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#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U

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#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U

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#define LPDDR4__PI_START__REG DENALI_PI_0

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#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START

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#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U

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#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U

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#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U

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#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0

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#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS

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#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U

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#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U

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#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1

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#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0

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#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U

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#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U

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#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2

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#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1

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#define LPDDR4__DENALI_PI_3_READ_MASK 0x0000FFFFU

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#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0000FFFFU

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#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU

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#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U

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#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U

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#define LPDDR4__PI_ID__REG DENALI_PI_3

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#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID

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#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_SHIFT 0U

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#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_WIDTH 32U

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#define LPDDR4__DENALI_PI_UNUSED_REG_0__REG DENALI_PI_4

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#define LPDDR4__DENALI_PI_UNUSED_REG_0__FLD LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0

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#define LPDDR4__DENALI_PI_5_READ_MASK 0x00010101U

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#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x00010101U

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#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_SHIFT 0U

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#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WIDTH 1U

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#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOCLR 0U

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#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOSET 0U

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#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_5

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#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ

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#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_SHIFT 8U

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#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WIDTH 1U

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#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOCLR 0U

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#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOSET 0U

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#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_5

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#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN

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#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_SHIFT 16U

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#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WIDTH 1U

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#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOCLR 0U

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#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOSET 0U

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#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_5

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#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD

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#define LPDDR4__DENALI_PI_6_READ_MASK 0x00FFFFFFU

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#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00FFFFFFU

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#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_MASK 0x0000FFFFU

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#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_SHIFT 0U

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#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_WIDTH 16U

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#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_6

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#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_6__PI_TCMD_GAP

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#define LPDDR4__DENALI_PI_6__PI_RESERVED0_MASK 0x00FF0000U

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#define LPDDR4__DENALI_PI_6__PI_RESERVED0_SHIFT 16U

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#define LPDDR4__DENALI_PI_6__PI_RESERVED0_WIDTH 8U

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#define LPDDR4__PI_RESERVED0__REG DENALI_PI_6

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#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_6__PI_RESERVED0

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#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_SHIFT 24U

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#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U

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#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U

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#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U

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#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_6

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#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ

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#define LPDDR4__DENALI_PI_7_READ_MASK 0x01010301U

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#define LPDDR4__DENALI_PI_7_WRITE_MASK 0x01010301U

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#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_SHIFT 0U

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#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WIDTH 1U

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#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOCLR 0U

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#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOSET 0U

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#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_7

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#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_7__PI_DFI_VERSION

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_MASK 0x00000300U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_SHIFT 8U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_WIDTH 2U

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#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_7

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#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 16U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U

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#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_7

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#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 24U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U

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#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U

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#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_7

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#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R

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#define LPDDR4__DENALI_PI_8_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_8_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_SHIFT 0U

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#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_WIDTH 32U

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#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_8

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#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX

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#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_SHIFT 0U

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#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_WIDTH 20U

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#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_9

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#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP

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#define LPDDR4__DENALI_PI_10_READ_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_10_WRITE_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_SHIFT 0U

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#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_WIDTH 20U

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#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_10

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#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP

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#define LPDDR4__DENALI_PI_11_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_11_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_SHIFT 0U

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#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_WIDTH 32U

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#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_11

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#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX

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#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U

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#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U

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#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12

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#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP

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#define LPDDR4__DENALI_PI_13_READ_MASK 0x0101011FU

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#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x0101011FU

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#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_MASK 0x0000001FU

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#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_SHIFT 0U

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#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_WIDTH 5U

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#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_13

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#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ

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#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U

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#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U

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#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U

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#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOSET 0U

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#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_13

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#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 16U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U

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#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13

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#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 24U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U

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#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13

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#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1

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#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F0FU

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#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F0FU

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#define LPDDR4__DENALI_PI_14__PI_CS_MAP_MASK 0x0000000FU

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#define LPDDR4__DENALI_PI_14__PI_CS_MAP_SHIFT 0U

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#define LPDDR4__DENALI_PI_14__PI_CS_MAP_WIDTH 4U

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#define LPDDR4__PI_CS_MAP__REG DENALI_PI_14

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#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_14__PI_CS_MAP

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#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U

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#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U

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#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U

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#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14

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#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U

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#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14

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#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN

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#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U

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#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U

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#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U

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#define LPDDR4__PI_TMRR__REG DENALI_PI_14

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#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR

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#define LPDDR4__DENALI_PI_15_READ_MASK 0x00010103U

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#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x00010103U

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#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_MASK 0x00000003U

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#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_SHIFT 0U

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#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_WIDTH 2U

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#define LPDDR4__PI_PREAMBLE_SUPPORT__REG DENALI_PI_15

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#define LPDDR4__PI_PREAMBLE_SUPPORT__FLD LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 8U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U

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#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15

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#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 16U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U

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#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15

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#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2

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#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU

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#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU

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#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U

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#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U

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#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16

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#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL

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#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U

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#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U

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#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U

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#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U

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#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16

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#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS

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#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U

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#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U

283

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U

284

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U

285

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U

286

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U

287

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U

288

#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17

289

#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION

290

291

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U

292

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U

293

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U

294

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U

295

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U

296

#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17

297

#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD

298

299

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U

300

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U

301

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U

302

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U

303

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U

304

#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17

305

#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE

306

307

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U

308

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U

309

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U

310

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U

311

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U

312

#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17

313

#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0

314

315

#define LPDDR4__DENALI_PI_18_READ_MASK 0x03010101U

316

#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03010101U

317

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U

318

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U

319

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U

320

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U

321

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U

322

#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18

323

#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1

324

325

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK 0x00000100U

326

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT 8U

327

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH 1U

328

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR 0U

329

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET 0U

330

#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18

331

#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2

332

333

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK 0x00010000U

334

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT 16U

335

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH 1U

336

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR 0U

337

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET 0U

338

#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18

339

#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3

340

341

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x03000000U

342

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 24U

343

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U

344

#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18

345

#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0

346

347

#define LPDDR4__DENALI_PI_19_READ_MASK 0x03030303U

348

#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x03030303U

349

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK 0x00000003U

350

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT 0U

351

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH 2U

352

#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19

353

#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1

354

355

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK 0x00000300U

356

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT 8U

357

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH 2U

358

#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19

359

#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2

360

361

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK 0x00030000U

362

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT 16U

363

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH 2U

364

#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19

365

#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3

366

367

#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK 0x03000000U

368

#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT 24U

369

#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH 2U

370

#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19

371

#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0

372

373

#define LPDDR4__DENALI_PI_20_READ_MASK 0x00000007U

374

#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00000007U

375

#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK 0x00000007U

376

#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT 0U

377

#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH 3U

378

#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20

379

#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE

380

381

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK 0x00000100U

382

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT 8U

383

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH 1U

384

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR 0U

385

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET 0U

386

#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20

387

#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START

388

389

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK 0x00010000U

390

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT 16U

391

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH 1U

392

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR 0U

393

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET 0U

394

#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20

395

#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT

396

397

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U

398

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT 24U

399

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH 1U

400

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR 0U

401

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET 0U

402

#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20

403

#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0

404

405

#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U

406

#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U

407

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U

408

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT 0U

409

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH 1U

410

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR 0U

411

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET 0U

412

#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21

413

#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0

414

415

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U

416

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U

417

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U

418

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U

419

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U

420

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21

421

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0

422

423

#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U

424

#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT 16U

425

#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH 2U

426

#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21

427

#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0

428

429

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U

430

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT 24U

431

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH 1U

432

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR 0U

433

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET 0U

434

#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21

435

#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1

436

437

#define LPDDR4__DENALI_PI_22_READ_MASK 0x00030000U

438

#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x00030000U

439

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U

440

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT 0U

441

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH 1U

442

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR 0U

443

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET 0U

444

#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22

445

#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1

446

447

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U

448

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U

449

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U

450

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U

451

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U

452

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22

453

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1

454

455

#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U

456

#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT 16U

457

#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH 2U

458

#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22

459

#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1

460

461

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK 0x01000000U

462

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT 24U

463

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH 1U

464

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR 0U

465

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET 0U

466

#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22

467

#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2

468

469

#define LPDDR4__DENALI_PI_23_READ_MASK 0x00030000U

470

#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00030000U

471

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK 0x00000001U

472

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT 0U

473

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH 1U

474

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR 0U

475

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET 0U

476

#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23

477

#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2

478

479

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK 0x00000100U

480

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT 8U

481

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH 1U

482

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR 0U

483

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET 0U

484

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23

485

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2

486

487

#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK 0x00030000U

488

#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT 16U

489

#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH 2U

490

#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23

491

#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2

492

493

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK 0x01000000U

494

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT 24U

495

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH 1U

496

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR 0U

497

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET 0U

498

#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23

499

#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3

500

501

#define LPDDR4__DENALI_PI_24_READ_MASK 0x00030000U

502

#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x00030000U

503

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK 0x00000001U

504

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT 0U

505

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH 1U

506

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR 0U

507

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET 0U

508

#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24

509

#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3

510

511

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK 0x00000100U

512

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT 8U

513

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH 1U

514

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR 0U

515

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET 0U

516

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24

517

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3

518

519

#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK 0x00030000U

520

#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT 16U

521

#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH 2U

522

#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24

523

#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3

524

525

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK 0x01000000U

526

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT 24U

527

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH 1U

528

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR 0U

529

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET 0U

530

#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24

531

#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START

532

533

#define LPDDR4__DENALI_PI_25_READ_MASK 0x01000000U

534

#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x01000000U

535

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK 0x00000001U

536

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT 0U

537

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH 1U

538

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR 0U

539

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET 0U

540

#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25

541

#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR

542

543

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK 0x00000100U

544

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT 8U

545

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH 1U

546

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR 0U

547

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET 0U

548

#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25

549

#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD

550

551

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U

552

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U

553

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U

554

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U

555

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET 0U

556

#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25

557

#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ

558

559

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK 0x01000000U

560

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT 24U

561

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH 1U

562

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR 0U

563

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET 0U

564

#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25

565

#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN

566

567

#define LPDDR4__DENALI_PI_26_READ_MASK 0x00010101U

568

#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x00010101U

569

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK 0x00000001U

570

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT 0U

571

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH 1U

572

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR 0U

573

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET 0U

574

#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26

575

#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN

576

577

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK 0x00000100U

578

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT 8U

579

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH 1U

580

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR 0U

581

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET 0U

582

#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26

583

#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY

584

585

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK 0x00010000U

586

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT 16U

587

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH 1U

588

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR 0U

589

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET 0U

590

#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26

591

#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT

592

593

#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_MASK 0x01000000U

594

#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_SHIFT 24U

595

#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WIDTH 1U

596

#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOCLR 0U

597

#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOSET 0U

598

#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_26

599

#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_REQ

600

601

#define LPDDR4__DENALI_PI_27_READ_MASK 0x003F3F03U

602

#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x003F3F03U

603

#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK 0x00000003U

604

#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT 0U

605

#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH 2U

606

#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27

607

#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS

608

609

#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK 0x00003F00U

610

#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT 8U

611

#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH 6U

612

#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27

613

#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN

614

615

#define LPDDR4__DENALI_PI_27__PI_WLMRD_MASK 0x003F0000U

616

#define LPDDR4__DENALI_PI_27__PI_WLMRD_SHIFT 16U

617

#define LPDDR4__DENALI_PI_27__PI_WLMRD_WIDTH 6U

618

#define LPDDR4__PI_WLMRD__REG DENALI_PI_27

619

#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_27__PI_WLMRD

620

621

#define LPDDR4__DENALI_PI_28_READ_MASK 0x0101FFFFU

622

#define LPDDR4__DENALI_PI_28_WRITE_MASK 0x0101FFFFU

623

#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK 0x0000FFFFU

624

#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT 0U

625

#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH 16U

626

#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28

627

#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL

628

629

#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_MASK 0x00010000U

630

#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_SHIFT 16U

631

#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WIDTH 1U

632

#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOCLR 0U

633

#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOSET 0U

634

#define LPDDR4__PI_WRLVL_PERIODIC__REG DENALI_PI_28

635

#define LPDDR4__PI_WRLVL_PERIODIC__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC

636

637

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK 0x01000000U

638

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT 24U

639

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U

640

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U

641

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET 0U

642

#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28

643

#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT

644

645

#define LPDDR4__DENALI_PI_29_READ_MASK 0x0F010F01U

646

#define LPDDR4__DENALI_PI_29_WRITE_MASK 0x0F010F01U

647

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK 0x00000001U

648

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT 0U

649

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH 1U

650

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR 0U

651

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET 0U

652

#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29

653

#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS

654

655

#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK 0x00000F00U

656

#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT 8U

657

#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH 4U

658

#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29

659

#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK

660

661

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK 0x00010000U

662

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT 16U

663

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH 1U

664

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR 0U

665

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET 0U

666

#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29

667

#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE

668

669

#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK 0x0F000000U

670

#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT 24U

671

#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH 4U

672

#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29

673

#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP

674

675

#define LPDDR4__DENALI_PI_30_READ_MASK 0x0000FF01U

676

#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x0000FF01U

677

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK 0x00000001U

678

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT 0U

679

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH 1U

680

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR 0U

681

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET 0U

682

#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30

683

#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS

684

685

#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK 0x0000FF00U

686

#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT 8U

687

#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH 8U

688

#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30

689

#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN

690

691

#define LPDDR4__DENALI_PI_31_READ_MASK 0xFFFFFFFFU

692

#define LPDDR4__DENALI_PI_31_WRITE_MASK 0xFFFFFFFFU

693

#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU

694

#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT 0U

695

#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH 32U

696

#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31

697

#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP

698

699

#define LPDDR4__DENALI_PI_32_READ_MASK 0xFFFFFFFFU

700

#define LPDDR4__DENALI_PI_32_WRITE_MASK 0xFFFFFFFFU

701

#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU

702

#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT 0U

703

#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH 32U

704

#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32

705

#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX

706

707

#define LPDDR4__DENALI_PI_33_READ_MASK 0x0F0F0F1FU

708

#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x0F0F0F1FU

709

#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU

710

#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT 0U

711

#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH 5U

712

#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33

713

#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM

714

715

#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK 0x00000F00U

716

#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT 8U

717

#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH 4U

718

#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33

719

#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR

720

721

#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK 0x000F0000U

722

#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT 16U

723

#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH 4U

724

#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33

725

#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD

726

727

#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK 0x0F000000U

728

#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT 24U

729

#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH 4U

730

#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33

731

#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE

732

733

#define LPDDR4__DENALI_PI_34_READ_MASK 0x00030000U

734

#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x00030000U

735

#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_MASK 0x00000001U

736

#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_SHIFT 0U

737

#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WIDTH 1U

738

#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOCLR 0U

739

#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOSET 0U

740

#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_34

741

#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_REQ

742

743

#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_MASK 0x00000100U

744

#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_SHIFT 8U

745

#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WIDTH 1U

746

#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOCLR 0U

747

#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOSET 0U

748

#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_34

749

#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ

750

751

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK 0x00030000U

752

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT 16U

753

#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH 2U

754

#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34

755

#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS

756

757

#define LPDDR4__DENALI_PI_35_READ_MASK 0xFFFFFFFFU

758

#define LPDDR4__DENALI_PI_35_WRITE_MASK 0xFFFFFFFFU

759

#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU

760

#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT 0U

761

#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH 32U

762

#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35

763

#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0

764

765

#define LPDDR4__DENALI_PI_36_READ_MASK 0xFFFFFFFFU

766

#define LPDDR4__DENALI_PI_36_WRITE_MASK 0xFFFFFFFFU

767

#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU

768

#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT 0U

769

#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH 32U

770

#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36

771

#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1

772

773

#define LPDDR4__DENALI_PI_37_READ_MASK 0xFFFFFFFFU

774

#define LPDDR4__DENALI_PI_37_WRITE_MASK 0xFFFFFFFFU

775

#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU

776

#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT 0U

777

#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH 32U

778

#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37

779

#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2

780

781

#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU

782

#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU

783

#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU

784

#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT 0U

785

#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH 32U

786

#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38

787

#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3

788

789

#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU

790

#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU

791

#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU

792

#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT 0U

793

#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH 32U

794

#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39

795

#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4

796

797

#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU

798

#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU

799

#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU

800

#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT 0U

801

#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH 32U

802

#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40

803

#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5

804

805

#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU

806

#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU

807

#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU

808

#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT 0U

809

#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH 32U

810

#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41

811

#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6

812

813

#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU

814

#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU

815

#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU

816

#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT 0U

817

#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH 32U

818

#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42

819

#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7

820

821

#define LPDDR4__DENALI_PI_43_READ_MASK 0x0101010FU

822

#define LPDDR4__DENALI_PI_43_WRITE_MASK 0x0101010FU

823

#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK 0x0000000FU

824

#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT 0U

825

#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH 4U

826

#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43

827

#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN

828

829

#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_MASK 0x00000100U

830

#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_SHIFT 8U

831

#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WIDTH 1U

832

#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOCLR 0U

833

#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOSET 0U

834

#define LPDDR4__PI_RDLVL_PERIODIC__REG DENALI_PI_43

835

#define LPDDR4__PI_RDLVL_PERIODIC__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC

836

837

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK 0x00010000U

838

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT 16U

839

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U

840

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U

841

#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET 0U

842

#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43

843

#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT

844

845

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK 0x01000000U

846

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT 24U

847

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH 1U

848

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR 0U

849

#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET 0U

850

#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43

851

#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS

852

853

#define LPDDR4__DENALI_PI_44_READ_MASK 0x01010101U

854

#define LPDDR4__DENALI_PI_44_WRITE_MASK 0x01010101U

855

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_MASK 0x00000001U

856

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_SHIFT 0U

857

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WIDTH 1U

858

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOCLR 0U

859

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOSET 0U

860

#define LPDDR4__PI_RDLVL_GATE_PERIODIC__REG DENALI_PI_44

861

#define LPDDR4__PI_RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC

862

863

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000100U

864

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 8U

865

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U

866

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U

867

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U

868

#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_44

869

#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT

870

871

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00010000U

872

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 16U

873

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U

874

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U

875

#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U

876

#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44

877

#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS

878

879

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK 0x01000000U

880

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT 24U

881

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH 1U

882

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR 0U

883

#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET 0U

884

#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44

885

#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE

886

887

#define LPDDR4__DENALI_PI_45_READ_MASK 0x000F0F01U

888

#define LPDDR4__DENALI_PI_45_WRITE_MASK 0x000F0F01U

889

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U

890

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT 0U

891

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH 1U

892

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR 0U

893

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET 0U

894

#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45

895

#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE

896

897

#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK 0x00000F00U

898

#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT 8U

899

#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH 4U

900

#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45

901

#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP

902

903

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK 0x000F0000U

904

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT 16U

905

#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH 4U

906

#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45

907

#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP

908

909

#define LPDDR4__DENALI_PI_46_READ_MASK 0x000003FFU

910

#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x000003FFU

911

#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK 0x000003FFU

912

#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT 0U

913

#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH 10U

914

#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46

915

#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR

916

917

#define LPDDR4__DENALI_PI_47_READ_MASK 0xFFFFFFFFU

918

#define LPDDR4__DENALI_PI_47_WRITE_MASK 0xFFFFFFFFU

919

#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU

920

#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT 0U

921

#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH 32U

922

#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47

923

#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP

924

925

#define LPDDR4__DENALI_PI_48_READ_MASK 0x0000FF0FU

926

#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x0000FF0FU

927

#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK 0x0000000FU

928

#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT 0U

929

#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH 4U

930

#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48

931

#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK

932

933

#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U

934

#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT 8U

935

#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH 8U

936

#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48

937

#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN

938

939

#define LPDDR4__DENALI_PI_49_READ_MASK 0xFFFFFFFFU

940

#define LPDDR4__DENALI_PI_49_WRITE_MASK 0xFFFFFFFFU

941

#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU

942

#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT 0U

943

#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH 32U

944

#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49

945

#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX

946

947

#define LPDDR4__DENALI_PI_50_READ_MASK 0x00FFFF01U

948

#define LPDDR4__DENALI_PI_50_WRITE_MASK 0x00FFFF01U

949

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U

950

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT 0U

951

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH 1U

952

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR 0U

953

#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET 0U

954

#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50

955

#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS

956

957

#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U

958

#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT 8U

959

#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH 16U

960

#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50

961

#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL

962

963

#define LPDDR4__DENALI_PI_51_READ_MASK 0x0F0FFFFFU

964

#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0F0FFFFFU

965

#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU

966

#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT 0U

967

#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH 16U

968

#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51

969

#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL

970

971

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK 0x000F0000U

972

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT 16U

973

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH 4U

974

#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51

975

#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START

976

977

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U

978

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT 24U

979

#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH 4U

980

#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51

981

#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM

982

983

#define LPDDR4__DENALI_PI_52_READ_MASK 0x01011F1FU

984

#define LPDDR4__DENALI_PI_52_WRITE_MASK 0x01011F1FU

985

#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU

986

#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT 0U

987

#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH 5U

988

#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52

989

#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM

990

991

#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U

992

#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U

993

#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U

994

#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52

995

#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM

996

997

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U

998

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U

999

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U

1000

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U

1001

#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U

1002

#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52

1003

#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN

1004

1005

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK 0x01000000U

1006

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT 24U

1007

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH 1U

1008

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR 0U

1009

#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET 0U

1010

#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52

1011

#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE

1012

1013

#define LPDDR4__DENALI_PI_53_READ_MASK 0x03007F7FU

1014

#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x03007F7FU

1015

#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK 0x0000007FU

1016

#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT 0U

1017

#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH 7U

1018

#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53

1019

#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN

1020

1021

#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK 0x00007F00U

1022

#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT 8U

1023

#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH 7U

1024

#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53

1025

#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT

1026

1027

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK 0x00010000U

1028

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT 16U

1029

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH 1U

1030

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR 0U

1031

#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET 0U

1032

#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53

1033

#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ

1034

1035

#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_MASK 0x03000000U

1036

#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SHIFT 24U

1037

#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_WIDTH 2U

1038

#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_53

1039

#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS

1040

1041

#define LPDDR4__DENALI_PI_54_READ_MASK 0x01030F01U

1042

#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x01030F01U

1043

#define LPDDR4__DENALI_PI_54__PI_RESERVED3_MASK 0x00000001U

1044

#define LPDDR4__DENALI_PI_54__PI_RESERVED3_SHIFT 0U

1045

#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WIDTH 1U

1046

#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOCLR 0U

1047

#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOSET 0U

1048

#define LPDDR4__PI_RESERVED3__REG DENALI_PI_54

1049

#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_54__PI_RESERVED3

1050

1051

#define LPDDR4__DENALI_PI_54__PI_RESERVED4_MASK 0x00000F00U

1052

#define LPDDR4__DENALI_PI_54__PI_RESERVED4_SHIFT 8U

1053

#define LPDDR4__DENALI_PI_54__PI_RESERVED4_WIDTH 4U

1054

#define LPDDR4__PI_RESERVED4__REG DENALI_PI_54

1055

#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_54__PI_RESERVED4

1056

1057

#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK 0x00030000U

1058

#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT 16U

1059

#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH 2U

1060

#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54

1061

#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN

1062

1063

#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_MASK 0x01000000U

1064

#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_SHIFT 24U

1065

#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WIDTH 1U

1066

#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOCLR 0U

1067

#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOSET 0U

1068

#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_54

1069

#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC

1070

1071

#define LPDDR4__DENALI_PI_55_READ_MASK 0x0F010101U

1072

#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x0F010101U

1073

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK 0x00000001U

1074

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT 0U

1075

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH 1U

1076

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR 0U

1077

#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET 0U

1078

#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55

1079

#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT

1080

1081

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK 0x00000100U

1082

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT 8U

1083

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH 1U

1084

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR 0U

1085

#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET 0U

1086

#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55

1087

#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS

1088

1089

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK 0x00010000U

1090

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT 16U

1091

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH 1U

1092

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR 0U

1093

#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET 0U

1094

#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55

1095

#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE

1096

1097

#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_MASK 0x0F000000U

1098

#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_SHIFT 24U

1099

#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_WIDTH 4U

1100

#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_55

1101

#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP

1102

1103

#define LPDDR4__DENALI_PI_56_READ_MASK 0x000000FFU

1104

#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x000000FFU

1105

#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK 0x000000FFU

1106

#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT 0U

1107

#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH 8U

1108

#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56

1109

#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN

1110

1111

#define LPDDR4__DENALI_PI_57_READ_MASK 0xFFFFFFFFU

1112

#define LPDDR4__DENALI_PI_57_WRITE_MASK 0xFFFFFFFFU

1113

#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU

1114

#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT 0U

1115

#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH 32U

1116

#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57

1117

#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP

1118

1119

#define LPDDR4__DENALI_PI_58_READ_MASK 0xFFFFFFFFU

1120

#define LPDDR4__DENALI_PI_58_WRITE_MASK 0xFFFFFFFFU

1121

#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU

1122

#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT 0U

1123

#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH 32U

1124

#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58

1125

#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX

1126

1127

#define LPDDR4__DENALI_PI_59_READ_MASK 0xFFFF0301U

1128

#define LPDDR4__DENALI_PI_59_WRITE_MASK 0xFFFF0301U

1129

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK 0x00000001U

1130

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT 0U

1131

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH 1U

1132

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR 0U

1133

#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET 0U

1134

#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59

1135

#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK

1136

1137

#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK 0x00000300U

1138

#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT 8U

1139

#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH 2U

1140

#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59

1141

#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS

1142

1143

#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK 0xFFFF0000U

1144

#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT 16U

1145

#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH 16U

1146

#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59

1147

#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL

1148

1149

#define LPDDR4__DENALI_PI_60_READ_MASK 0x1F1F3F1FU

1150

#define LPDDR4__DENALI_PI_60_WRITE_MASK 0x1F1F3F1FU

1151

#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK 0x0000001FU

1152

#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT 0U

1153

#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH 5U

1154

#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60

1155

#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL

1156

1157

#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK 0x00003F00U

1158

#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT 8U

1159

#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH 6U

1160

#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60

1161

#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD

1162

1163

#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK 0x001F0000U

1164

#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT 16U

1165

#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH 5U

1166

#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60

1167

#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH

1168

1169

#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK 0x1F000000U

1170

#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT 24U

1171

#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH 5U

1172

#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60

1173

#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT

1174

1175

#define LPDDR4__DENALI_PI_61_READ_MASK 0xFF0F0F01U

1176

#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFF0F0F01U

1177

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U

1178

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT 0U

1179

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH 1U

1180

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR 0U

1181

#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET 0U

1182

#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61

1183

#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN

1184

1185

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U

1186

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U

1187

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U

1188

#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61

1189

#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE

1190

1191

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U

1192

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U

1193

#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U

1194

#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61

1195

#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE

1196

1197

#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U

1198

#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT 24U

1199

#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH 8U

1200

#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61

1201

#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN

1202

1203

#define LPDDR4__DENALI_PI_62_READ_MASK 0x7F1F0FFFU

1204

#define LPDDR4__DENALI_PI_62_WRITE_MASK 0x7F1F0FFFU

1205

#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_MASK 0x000000FFU

1206

#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 0U

1207

#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U

1208

#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_62

1209

#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN

1210

1211

#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK 0x00000F00U

1212

#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT 8U

1213

#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH 4U

1214

#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62

1215

#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH

1216

1217

#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK 0x001F0000U

1218

#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT 16U

1219

#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH 5U

1220

#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62

1221

#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM

1222

1223

#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK 0x7F000000U

1224

#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT 24U

1225

#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH 7U

1226

#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62

1227

#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF

1228

1229

#define LPDDR4__DENALI_PI_63_READ_MASK 0x0101FFFFU

1230

#define LPDDR4__DENALI_PI_63_WRITE_MASK 0x0101FFFFU

1231

#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU

1232

#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT 0U

1233

#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH 8U

1234

#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63

1235

#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START

1236

1237

#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U

1238

#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U

1239

#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U

1240

#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63

1241

#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE

1242

1243

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U

1244

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U

1245

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U

1246

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U

1247

#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U

1248

#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63

1249

#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL

1250

1251

#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U

1252

#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U

1253

#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U

1254

#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U

1255

#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U

1256

#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_63

1257

#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE

1258

1259

#define LPDDR4__DENALI_PI_64_READ_MASK 0x00FFFF01U

1260

#define LPDDR4__DENALI_PI_64_WRITE_MASK 0x00FFFF01U

1261

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x00000001U

1262

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 0U

1263

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U

1264

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U

1265

#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U

1266

#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64

1267

#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE

1268

1269

#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_MASK 0x00FFFF00U

1270

#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_SHIFT 8U

1271

#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_WIDTH 16U

1272

#define LPDDR4__PI_FSM_ERROR_INFO_MASK__REG DENALI_PI_64

1273

#define LPDDR4__PI_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK

1274

1275

#define LPDDR4__DENALI_PI_65_READ_MASK 0xFFFF0000U

1276

#define LPDDR4__DENALI_PI_65_WRITE_MASK 0xFFFF0000U

1277

#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_MASK 0x0000FFFFU

1278

#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_SHIFT 0U

1279

#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_WIDTH 16U

1280

#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__REG DENALI_PI_65

1281

#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR

1282

1283

#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_MASK 0xFFFF0000U

1284

#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_SHIFT 16U

1285

#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_WIDTH 16U

1286

#define LPDDR4__PI_FSM_ERROR_INFO__REG DENALI_PI_65

1287

#define LPDDR4__PI_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO

1288

1289

#define LPDDR4__DENALI_PI_66_READ_MASK 0x010F0701U

1290

#define LPDDR4__DENALI_PI_66_WRITE_MASK 0x010F0701U

1291

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_MASK 0x00000001U

1292

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_SHIFT 0U

1293

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WIDTH 1U

1294

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOCLR 0U

1295

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOSET 0U

1296

#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_66

1297

#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN

1298

1299

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_MASK 0x00000700U

1300

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_SHIFT 8U

1301

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_WIDTH 3U

1302

#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_66

1303

#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM

1304

1305

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_MASK 0x000F0000U

1306

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_SHIFT 16U

1307

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_WIDTH 4U

1308

#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_66

1309

#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK

1310

1311

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK 0x01000000U

1312

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT 24U

1313

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH 1U

1314

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR 0U

1315

#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET 0U

1316

#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66

1317

#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE

1318

1319

#define LPDDR4__DENALI_PI_67_READ_MASK 0x011F1F0FU

1320

#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x011F1F0FU

1321

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_MASK 0x0000000FU

1322

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_SHIFT 0U

1323

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_WIDTH 4U

1324

#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_67

1325

#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP

1326

1327

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x00001F00U

1328

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 8U

1329

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U

1330

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_67

1331

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE

1332

1333

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x001F0000U

1334

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 16U

1335

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U

1336

#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_67

1337

#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE

1338

1339

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK 0x01000000U

1340

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT 24U

1341

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH 1U

1342

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR 0U

1343

#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET 0U

1344

#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67

1345

#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC

1346

1347

#define LPDDR4__DENALI_PI_68_READ_MASK 0x00FF0300U

1348

#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x00FF0300U

1349

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_MASK 0x00000001U

1350

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_SHIFT 0U

1351

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WIDTH 1U

1352

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOCLR 0U

1353

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOSET 0U

1354

#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_68

1355

#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ

1356

1357

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_MASK 0x00000300U

1358

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_SHIFT 8U

1359

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_WIDTH 2U

1360

#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_68

1361

#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_CS

1362

1363

#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK 0x00FF0000U

1364

#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT 16U

1365

#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH 8U

1366

#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68

1367

#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN

1368

1369

#define LPDDR4__DENALI_PI_69_READ_MASK 0xFFFFFFFFU

1370

#define LPDDR4__DENALI_PI_69_WRITE_MASK 0xFFFFFFFFU

1371

#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU

1372

#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT 0U

1373

#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH 32U

1374

#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69

1375

#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP

1376

1377

#define LPDDR4__DENALI_PI_70_READ_MASK 0xFFFFFFFFU

1378

#define LPDDR4__DENALI_PI_70_WRITE_MASK 0xFFFFFFFFU

1379

#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU

1380

#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT 0U

1381

#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH 32U

1382

#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70

1383

#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX

1384

1385

#define LPDDR4__DENALI_PI_71_READ_MASK 0x0101FFFFU

1386

#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x0101FFFFU

1387

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU

1388

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT 0U

1389

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH 16U

1390

#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71

1391

#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL

1392

1393

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U

1394

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U

1395

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U

1396

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U

1397

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U

1398

#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71

1399

#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT

1400

1401

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_MASK 0x01000000U

1402

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_SHIFT 24U

1403

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WIDTH 1U

1404

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOCLR 0U

1405

#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOSET 0U

1406

#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_71

1407

#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS

1408

1409

#define LPDDR4__DENALI_PI_72_READ_MASK 0x01010103U

1410

#define LPDDR4__DENALI_PI_72_WRITE_MASK 0x01010103U

1411

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK 0x00000003U

1412

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT 0U

1413

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH 2U

1414

#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72

1415

#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS

1416

1417

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_MASK 0x00000100U

1418

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_SHIFT 8U

1419

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WIDTH 1U

1420

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOCLR 0U

1421

#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOSET 0U

1422

#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_72

1423

#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN

1424

1425

#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_MASK 0x00010000U

1426

#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_SHIFT 16U

1427

#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WIDTH 1U

1428

#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOCLR 0U

1429

#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOSET 0U

1430

#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_72

1431

#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN

1432

1433

#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_MASK 0x01000000U

1434

#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_SHIFT 24U

1435

#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WIDTH 1U

1436

#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOCLR 0U

1437

#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOSET 0U

1438

#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_72

1439

#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN

1440

1441

#define LPDDR4__DENALI_PI_73_READ_MASK 0x0F1F0703U

1442

#define LPDDR4__DENALI_PI_73_WRITE_MASK 0x0F1F0703U

1443

#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_MASK 0x00000003U

1444

#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_SHIFT 0U

1445

#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_WIDTH 2U

1446

#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_73

1447

#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_73__PI_BANK_DIFF

1448

1449

#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_MASK 0x00000700U

1450

#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_SHIFT 8U

1451

#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_WIDTH 3U

1452

#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_73

1453

#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_73__PI_ROW_DIFF

1454

1455

#define LPDDR4__DENALI_PI_73__PI_TCCD_MASK 0x001F0000U

1456

#define LPDDR4__DENALI_PI_73__PI_TCCD_SHIFT 16U

1457

#define LPDDR4__DENALI_PI_73__PI_TCCD_WIDTH 5U

1458

#define LPDDR4__PI_TCCD__REG DENALI_PI_73

1459

#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_73__PI_TCCD

1460

1461

#define LPDDR4__DENALI_PI_73__PI_RESERVED5_MASK 0x0F000000U

1462

#define LPDDR4__DENALI_PI_73__PI_RESERVED5_SHIFT 24U

1463

#define LPDDR4__DENALI_PI_73__PI_RESERVED5_WIDTH 4U

1464

#define LPDDR4__PI_RESERVED5__REG DENALI_PI_73

1465

#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_73__PI_RESERVED5

1466

1467

#define LPDDR4__DENALI_PI_74_READ_MASK 0x0F0F0F0FU

1468

#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x0F0F0F0FU

1469

#define LPDDR4__DENALI_PI_74__PI_RESERVED6_MASK 0x0000000FU

1470

#define LPDDR4__DENALI_PI_74__PI_RESERVED6_SHIFT 0U

1471

#define LPDDR4__DENALI_PI_74__PI_RESERVED6_WIDTH 4U

1472

#define LPDDR4__PI_RESERVED6__REG DENALI_PI_74

1473

#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_74__PI_RESERVED6

1474

1475

#define LPDDR4__DENALI_PI_74__PI_RESERVED7_MASK 0x00000F00U

1476

#define LPDDR4__DENALI_PI_74__PI_RESERVED7_SHIFT 8U

1477

#define LPDDR4__DENALI_PI_74__PI_RESERVED7_WIDTH 4U

1478

#define LPDDR4__PI_RESERVED7__REG DENALI_PI_74

1479

#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_74__PI_RESERVED7

1480

1481

#define LPDDR4__DENALI_PI_74__PI_RESERVED8_MASK 0x000F0000U

1482

#define LPDDR4__DENALI_PI_74__PI_RESERVED8_SHIFT 16U

1483

#define LPDDR4__DENALI_PI_74__PI_RESERVED8_WIDTH 4U

1484

#define LPDDR4__PI_RESERVED8__REG DENALI_PI_74

1485

#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_74__PI_RESERVED8

1486

1487

#define LPDDR4__DENALI_PI_74__PI_RESERVED9_MASK 0x0F000000U

1488

#define LPDDR4__DENALI_PI_74__PI_RESERVED9_SHIFT 24U

1489

#define LPDDR4__DENALI_PI_74__PI_RESERVED9_WIDTH 4U

1490

#define LPDDR4__PI_RESERVED9__REG DENALI_PI_74

1491

#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_74__PI_RESERVED9

1492

1493

#define LPDDR4__DENALI_PI_75_READ_MASK 0x0F0F0F0FU

1494

#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x0F0F0F0FU

1495

#define LPDDR4__DENALI_PI_75__PI_RESERVED10_MASK 0x0000000FU

1496

#define LPDDR4__DENALI_PI_75__PI_RESERVED10_SHIFT 0U

1497

#define LPDDR4__DENALI_PI_75__PI_RESERVED10_WIDTH 4U

1498

#define LPDDR4__PI_RESERVED10__REG DENALI_PI_75

1499

#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_75__PI_RESERVED10

1500

1501

#define LPDDR4__DENALI_PI_75__PI_RESERVED11_MASK 0x00000F00U

1502

#define LPDDR4__DENALI_PI_75__PI_RESERVED11_SHIFT 8U

1503

#define LPDDR4__DENALI_PI_75__PI_RESERVED11_WIDTH 4U

1504

#define LPDDR4__PI_RESERVED11__REG DENALI_PI_75

1505

#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_75__PI_RESERVED11

1506

1507

#define LPDDR4__DENALI_PI_75__PI_RESERVED12_MASK 0x000F0000U

1508

#define LPDDR4__DENALI_PI_75__PI_RESERVED12_SHIFT 16U

1509

#define LPDDR4__DENALI_PI_75__PI_RESERVED12_WIDTH 4U

1510

#define LPDDR4__PI_RESERVED12__REG DENALI_PI_75

1511

#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_75__PI_RESERVED12

1512

1513

#define LPDDR4__DENALI_PI_75__PI_RESERVED13_MASK 0x0F000000U

1514

#define LPDDR4__DENALI_PI_75__PI_RESERVED13_SHIFT 24U

1515

#define LPDDR4__DENALI_PI_75__PI_RESERVED13_WIDTH 4U

1516

#define LPDDR4__PI_RESERVED13__REG DENALI_PI_75

1517

#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_75__PI_RESERVED13

1518

1519

#define LPDDR4__DENALI_PI_76_READ_MASK 0x0F0F0F0FU

1520

#define LPDDR4__DENALI_PI_76_WRITE_MASK 0x0F0F0F0FU

1521

#define LPDDR4__DENALI_PI_76__PI_RESERVED14_MASK 0x0000000FU

1522

#define LPDDR4__DENALI_PI_76__PI_RESERVED14_SHIFT 0U

1523

#define LPDDR4__DENALI_PI_76__PI_RESERVED14_WIDTH 4U

1524

#define LPDDR4__PI_RESERVED14__REG DENALI_PI_76

1525

#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_76__PI_RESERVED14

1526

1527

#define LPDDR4__DENALI_PI_76__PI_RESERVED15_MASK 0x00000F00U

1528

#define LPDDR4__DENALI_PI_76__PI_RESERVED15_SHIFT 8U

1529

#define LPDDR4__DENALI_PI_76__PI_RESERVED15_WIDTH 4U

1530

#define LPDDR4__PI_RESERVED15__REG DENALI_PI_76

1531

#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_76__PI_RESERVED15

1532

1533

#define LPDDR4__DENALI_PI_76__PI_RESERVED16_MASK 0x000F0000U

1534

#define LPDDR4__DENALI_PI_76__PI_RESERVED16_SHIFT 16U

1535

#define LPDDR4__DENALI_PI_76__PI_RESERVED16_WIDTH 4U

1536

#define LPDDR4__PI_RESERVED16__REG DENALI_PI_76

1537

#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_76__PI_RESERVED16

1538

1539

#define LPDDR4__DENALI_PI_76__PI_RESERVED17_MASK 0x0F000000U

1540

#define LPDDR4__DENALI_PI_76__PI_RESERVED17_SHIFT 24U

1541

#define LPDDR4__DENALI_PI_76__PI_RESERVED17_WIDTH 4U

1542

#define LPDDR4__PI_RESERVED17__REG DENALI_PI_76

1543

#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_76__PI_RESERVED17

1544

1545

#define LPDDR4__DENALI_PI_77_READ_MASK 0x0F0F0F0FU

1546

#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x0F0F0F0FU

1547

#define LPDDR4__DENALI_PI_77__PI_RESERVED18_MASK 0x0000000FU

1548

#define LPDDR4__DENALI_PI_77__PI_RESERVED18_SHIFT 0U

1549

#define LPDDR4__DENALI_PI_77__PI_RESERVED18_WIDTH 4U

1550

#define LPDDR4__PI_RESERVED18__REG DENALI_PI_77

1551

#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_77__PI_RESERVED18

1552

1553

#define LPDDR4__DENALI_PI_77__PI_RESERVED19_MASK 0x00000F00U

1554

#define LPDDR4__DENALI_PI_77__PI_RESERVED19_SHIFT 8U

1555

#define LPDDR4__DENALI_PI_77__PI_RESERVED19_WIDTH 4U

1556

#define LPDDR4__PI_RESERVED19__REG DENALI_PI_77

1557

#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_77__PI_RESERVED19

1558

1559

#define LPDDR4__DENALI_PI_77__PI_RESERVED20_MASK 0x000F0000U

1560

#define LPDDR4__DENALI_PI_77__PI_RESERVED20_SHIFT 16U

1561

#define LPDDR4__DENALI_PI_77__PI_RESERVED20_WIDTH 4U

1562

#define LPDDR4__PI_RESERVED20__REG DENALI_PI_77

1563

#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_77__PI_RESERVED20

1564

1565

#define LPDDR4__DENALI_PI_77__PI_RESERVED21_MASK 0x0F000000U

1566

#define LPDDR4__DENALI_PI_77__PI_RESERVED21_SHIFT 24U

1567

#define LPDDR4__DENALI_PI_77__PI_RESERVED21_WIDTH 4U

1568

#define LPDDR4__PI_RESERVED21__REG DENALI_PI_77

1569

#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_77__PI_RESERVED21

1570

1571

#define LPDDR4__DENALI_PI_78_READ_MASK 0x000F0F0FU

1572

#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x000F0F0FU

1573

#define LPDDR4__DENALI_PI_78__PI_RESERVED22_MASK 0x0000000FU

1574

#define LPDDR4__DENALI_PI_78__PI_RESERVED22_SHIFT 0U

1575

#define LPDDR4__DENALI_PI_78__PI_RESERVED22_WIDTH 4U

1576

#define LPDDR4__PI_RESERVED22__REG DENALI_PI_78

1577

#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_78__PI_RESERVED22

1578

1579

#define LPDDR4__DENALI_PI_78__PI_RESERVED23_MASK 0x00000F00U

1580

#define LPDDR4__DENALI_PI_78__PI_RESERVED23_SHIFT 8U

1581

#define LPDDR4__DENALI_PI_78__PI_RESERVED23_WIDTH 4U

1582

#define LPDDR4__PI_RESERVED23__REG DENALI_PI_78

1583

#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_78__PI_RESERVED23

1584

1585

#define LPDDR4__DENALI_PI_78__PI_RESERVED24_MASK 0x000F0000U

1586

#define LPDDR4__DENALI_PI_78__PI_RESERVED24_SHIFT 16U

1587

#define LPDDR4__DENALI_PI_78__PI_RESERVED24_WIDTH 4U

1588

#define LPDDR4__PI_RESERVED24__REG DENALI_PI_78

1589

#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_78__PI_RESERVED24

1590

1591

#define LPDDR4__DENALI_PI_79_READ_MASK 0x0FFFFFFFU

1592

#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x0FFFFFFFU

1593

#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_MASK 0x0FFFFFFFU

1594

#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_SHIFT 0U

1595

#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_WIDTH 28U

1596

#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_79

1597

#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_79__PI_INT_STATUS

1598

1599

#define LPDDR4__DENALI_PI_80__PI_INT_ACK_MASK 0x07FFFFFFU

1600

#define LPDDR4__DENALI_PI_80__PI_INT_ACK_SHIFT 0U

1601

#define LPDDR4__DENALI_PI_80__PI_INT_ACK_WIDTH 27U

1602

#define LPDDR4__PI_INT_ACK__REG DENALI_PI_80

1603

#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_80__PI_INT_ACK

1604

1605

#define LPDDR4__DENALI_PI_81_READ_MASK 0x0FFFFFFFU

1606

#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0FFFFFFFU

1607

#define LPDDR4__DENALI_PI_81__PI_INT_MASK_MASK 0x0FFFFFFFU

1608

#define LPDDR4__DENALI_PI_81__PI_INT_MASK_SHIFT 0U

1609

#define LPDDR4__DENALI_PI_81__PI_INT_MASK_WIDTH 28U

1610

#define LPDDR4__PI_INT_MASK__REG DENALI_PI_81

1611

#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_81__PI_INT_MASK

1612

1613

#define LPDDR4__DENALI_PI_82_READ_MASK 0xFFFFFFFFU

1614

#define LPDDR4__DENALI_PI_82_WRITE_MASK 0xFFFFFFFFU

1615

#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU

1616

#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_SHIFT 0U

1617

#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_WIDTH 32U

1618

#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_82

1619

#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0

1620

1621

#define LPDDR4__DENALI_PI_83_READ_MASK 0xFFFFFFFFU

1622

#define LPDDR4__DENALI_PI_83_WRITE_MASK 0xFFFFFFFFU

1623

#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU

1624

#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_SHIFT 0U

1625

#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_WIDTH 32U

1626

#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_83

1627

#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1

1628

1629

#define LPDDR4__DENALI_PI_84_READ_MASK 0xFFFFFFFFU

1630

#define LPDDR4__DENALI_PI_84_WRITE_MASK 0xFFFFFFFFU

1631

#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_MASK 0xFFFFFFFFU

1632

#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_SHIFT 0U

1633

#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_WIDTH 32U

1634

#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_84

1635

#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2

1636

1637

#define LPDDR4__DENALI_PI_85_READ_MASK 0xFFFFFFFFU

1638

#define LPDDR4__DENALI_PI_85_WRITE_MASK 0xFFFFFFFFU

1639

#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_MASK 0xFFFFFFFFU

1640

#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_SHIFT 0U

1641

#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_WIDTH 32U

1642

#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_85

1643

#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3

1644

1645

#define LPDDR4__DENALI_PI_86_READ_MASK 0xFFFFFFFFU

1646

#define LPDDR4__DENALI_PI_86_WRITE_MASK 0xFFFFFFFFU

1647

#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU

1648

#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_SHIFT 0U

1649

#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_WIDTH 32U

1650

#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_86

1651

#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0

1652

1653

#define LPDDR4__DENALI_PI_87_READ_MASK 0xFFFFFFFFU

1654

#define LPDDR4__DENALI_PI_87_WRITE_MASK 0xFFFFFFFFU

1655

#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU

1656

#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_SHIFT 0U

1657

#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_WIDTH 32U

1658

#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_87

1659

#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1

1660

1661

#define LPDDR4__DENALI_PI_88_READ_MASK 0xFFFFFFFFU

1662

#define LPDDR4__DENALI_PI_88_WRITE_MASK 0xFFFFFFFFU

1663

#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU

1664

#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_SHIFT 0U

1665

#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_WIDTH 32U

1666

#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_88

1667

#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2

1668

1669

#define LPDDR4__DENALI_PI_89_READ_MASK 0xFFFFFFFFU

1670

#define LPDDR4__DENALI_PI_89_WRITE_MASK 0xFFFFFFFFU

1671

#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU

1672

#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_SHIFT 0U

1673

#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_WIDTH 32U

1674

#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_89

1675

#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3

1676

1677

#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU

1678

#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU

1679

#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU

1680

#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT 0U

1681

#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH 32U

1682

#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90

1683

#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0

1684

1685

#define LPDDR4__DENALI_PI_91_READ_MASK 0x011F1F07U

1686

#define LPDDR4__DENALI_PI_91_WRITE_MASK 0x011F1F07U

1687

#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK 0x00000007U

1688

#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT 0U

1689

#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH 3U

1690

#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91

1691

#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1

1692

1693

#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK 0x00001F00U

1694

#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT 8U

1695

#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH 5U

1696

#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91

1697

#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN

1698

1699

#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK 0x001F0000U

1700

#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT 16U

1701

#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH 5U

1702

#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91

1703

#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK

1704

1705

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK 0x01000000U

1706

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT 24U

1707

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH 1U

1708

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR 0U

1709

#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET 0U

1710

#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91

1711

#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN

1712

1713

#define LPDDR4__DENALI_PI_92_READ_MASK 0x03030301U

1714

#define LPDDR4__DENALI_PI_92_WRITE_MASK 0x03030301U

1715

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_MASK 0x00000001U

1716

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_SHIFT 0U

1717

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WIDTH 1U

1718

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOCLR 0U

1719

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOSET 0U

1720

#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_92

1721

#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN

1722

1723

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00000300U

1724

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 8U

1725

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 2U

1726

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_92

1727

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0

1728

1729

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x00030000U

1730

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 16U

1731

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 2U

1732

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_92

1733

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1

1734

1735

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_MASK 0x03000000U

1736

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_SHIFT 24U

1737

#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_WIDTH 2U

1738

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_92

1739

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2

1740

1741

#define LPDDR4__DENALI_PI_93_READ_MASK 0x03FF0103U

1742

#define LPDDR4__DENALI_PI_93_WRITE_MASK 0x03FF0103U

1743

#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_MASK 0x00000003U

1744

#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_SHIFT 0U

1745

#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_WIDTH 2U

1746

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_93

1747

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3

1748

1749

#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00000100U

1750

#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 8U

1751

#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U

1752

#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U

1753

#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U

1754

#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_93

1755

#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN

1756

1757

#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_MASK 0x00FF0000U

1758

#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_SHIFT 16U

1759

#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_WIDTH 8U

1760

#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_93

1761

#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN

1762

1763

#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_MASK 0x03000000U

1764

#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_SHIFT 24U

1765

#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_WIDTH 2U

1766

#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_93

1767

#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS

1768

1769

#define LPDDR4__DENALI_PI_94_READ_MASK 0x013F0301U

1770

#define LPDDR4__DENALI_PI_94_WRITE_MASK 0x013F0301U

1771

#define LPDDR4__DENALI_PI_94__PI_BIST_GO_MASK 0x00000001U

1772

#define LPDDR4__DENALI_PI_94__PI_BIST_GO_SHIFT 0U

1773

#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WIDTH 1U

1774

#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOCLR 0U

1775

#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOSET 0U

1776

#define LPDDR4__PI_BIST_GO__REG DENALI_PI_94

1777

#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_94__PI_BIST_GO

1778

1779

#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_MASK 0x00000300U

1780

#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_SHIFT 8U

1781

#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_WIDTH 2U

1782

#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_94

1783

#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_94__PI_BIST_RESULT

1784

1785

#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_MASK 0x003F0000U

1786

#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_SHIFT 16U

1787

#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_WIDTH 6U

1788

#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_94

1789

#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_94__PI_ADDR_SPACE

1790

1791

#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_MASK 0x01000000U

1792

#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_SHIFT 24U

1793

#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WIDTH 1U

1794

#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOCLR 0U

1795

#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOSET 0U

1796

#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_94

1797

#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK

1798

1799

#define LPDDR4__DENALI_PI_95_READ_MASK 0x00000001U

1800

#define LPDDR4__DENALI_PI_95_WRITE_MASK 0x00000001U

1801

#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_MASK 0x00000001U

1802

#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_SHIFT 0U

1803

#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WIDTH 1U

1804

#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOCLR 0U

1805

#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOSET 0U

1806

#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_95

1807

#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK

1808

1809

#define LPDDR4__DENALI_PI_96_READ_MASK 0xFFFFFFFFU

1810

#define LPDDR4__DENALI_PI_96_WRITE_MASK 0xFFFFFFFFU

1811

#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU

1812

#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_SHIFT 0U

1813

#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_WIDTH 32U

1814

#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_96

1815

#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0

1816

1817

#define LPDDR4__DENALI_PI_97_READ_MASK 0x0000FF07U

1818

#define LPDDR4__DENALI_PI_97_WRITE_MASK 0x0000FF07U

1819

#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_MASK 0x00000007U

1820

#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_SHIFT 0U

1821

#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_WIDTH 3U

1822

#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_97

1823

#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1

1824

1825

#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U

1826

#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_SHIFT 8U

1827

#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_WIDTH 8U

1828

#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_97

1829

#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN

1830

1831

#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU

1832

#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU

1833

#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_MASK 0xFFFFFFFFU

1834

#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_SHIFT 0U

1835

#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_WIDTH 32U

1836

#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_98

1837

#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0

1838

1839

#define LPDDR4__DENALI_PI_99_READ_MASK 0xFFFFFFFFU

1840

#define LPDDR4__DENALI_PI_99_WRITE_MASK 0xFFFFFFFFU

1841

#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_MASK 0xFFFFFFFFU

1842

#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_SHIFT 0U

1843

#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_WIDTH 32U

1844

#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_99

1845

#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1

1846

1847

#define LPDDR4__DENALI_PI_100_READ_MASK 0x0FFF0FFFU

1848

#define LPDDR4__DENALI_PI_100_WRITE_MASK 0x0FFF0FFFU

1849

#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_MASK 0x00000FFFU

1850

#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_SHIFT 0U

1851

#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_WIDTH 12U

1852

#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_100

1853

#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT

1854

1855

#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_MASK 0x0FFF0000U

1856

#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_SHIFT 16U

1857

#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_WIDTH 12U

1858

#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_100

1859

#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP

1860

1861

#define LPDDR4__DENALI_PI_101_READ_MASK 0xFFFFFFFFU

1862

#define LPDDR4__DENALI_PI_101_WRITE_MASK 0xFFFFFFFFU

1863

#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU

1864

#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_SHIFT 0U

1865

#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_WIDTH 32U

1866

#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_101

1867

#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0

1868

1869

#define LPDDR4__DENALI_PI_102_READ_MASK 0x0000000FU

1870

#define LPDDR4__DENALI_PI_102_WRITE_MASK 0x0000000FU

1871

#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_MASK 0x0000000FU

1872

#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_SHIFT 0U

1873

#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_WIDTH 4U

1874

#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_102

1875

#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1

1876

1877

#define LPDDR4__DENALI_PI_103_READ_MASK 0xFFFFFFFFU

1878

#define LPDDR4__DENALI_PI_103_WRITE_MASK 0xFFFFFFFFU

1879

#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU

1880

#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_SHIFT 0U

1881

#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_WIDTH 32U

1882

#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_103

1883

#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0

1884

1885

#define LPDDR4__DENALI_PI_104_READ_MASK 0x0000000FU

1886

#define LPDDR4__DENALI_PI_104_WRITE_MASK 0x0000000FU

1887

#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_MASK 0x0000000FU

1888

#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_SHIFT 0U

1889

#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_WIDTH 4U

1890

#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_104

1891

#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1

1892

1893

#define LPDDR4__DENALI_PI_105_READ_MASK 0xFFFFFFFFU

1894

#define LPDDR4__DENALI_PI_105_WRITE_MASK 0xFFFFFFFFU

1895

#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU

1896

#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_SHIFT 0U

1897

#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_WIDTH 32U

1898

#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_105

1899

#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0

1900

1901

#define LPDDR4__DENALI_PI_106_READ_MASK 0x0000000FU

1902

#define LPDDR4__DENALI_PI_106_WRITE_MASK 0x0000000FU

1903

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_MASK 0x0000000FU

1904

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_SHIFT 0U

1905

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_WIDTH 4U

1906

#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_106

1907

#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1

1908

1909

#define LPDDR4__DENALI_PI_107_READ_MASK 0xFFFFFFFFU

1910

#define LPDDR4__DENALI_PI_107_WRITE_MASK 0xFFFFFFFFU

1911

#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU

1912

#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_SHIFT 0U

1913

#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_WIDTH 32U

1914

#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_107

1915

#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0

1916

1917

#define LPDDR4__DENALI_PI_108_READ_MASK 0x0000000FU

1918

#define LPDDR4__DENALI_PI_108_WRITE_MASK 0x0000000FU

1919

#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_MASK 0x0000000FU

1920

#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_SHIFT 0U

1921

#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_WIDTH 4U

1922

#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_108

1923

#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1

1924

1925

#define LPDDR4__DENALI_PI_109_READ_MASK 0xFFFFFFFFU

1926

#define LPDDR4__DENALI_PI_109_WRITE_MASK 0xFFFFFFFFU

1927

#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU

1928

#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_SHIFT 0U

1929

#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_WIDTH 32U

1930

#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_109

1931

#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0

1932

1933

#define LPDDR4__DENALI_PI_110_READ_MASK 0x0000000FU

1934

#define LPDDR4__DENALI_PI_110_WRITE_MASK 0x0000000FU

1935

#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_MASK 0x0000000FU

1936

#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_SHIFT 0U

1937

#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_WIDTH 4U

1938

#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_110

1939

#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1

1940

1941

#define LPDDR4__DENALI_PI_111_READ_MASK 0xFFFFFFFFU

1942

#define LPDDR4__DENALI_PI_111_WRITE_MASK 0xFFFFFFFFU

1943

#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU

1944

#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_SHIFT 0U

1945

#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_WIDTH 32U

1946

#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_111

1947

#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0

1948

1949

#define LPDDR4__DENALI_PI_112_READ_MASK 0x0000000FU

1950

#define LPDDR4__DENALI_PI_112_WRITE_MASK 0x0000000FU

1951

#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_MASK 0x0000000FU

1952

#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_SHIFT 0U

1953

#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_WIDTH 4U

1954

#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_112

1955

#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1

1956

1957

#define LPDDR4__DENALI_PI_113_READ_MASK 0xFFFFFFFFU

1958

#define LPDDR4__DENALI_PI_113_WRITE_MASK 0xFFFFFFFFU

1959

#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU

1960

#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_SHIFT 0U

1961

#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_WIDTH 32U

1962

#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_113

1963

#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0

1964

1965

#define LPDDR4__DENALI_PI_114_READ_MASK 0x0000000FU

1966

#define LPDDR4__DENALI_PI_114_WRITE_MASK 0x0000000FU

1967

#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_MASK 0x0000000FU

1968

#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_SHIFT 0U

1969

#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_WIDTH 4U

1970

#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_114

1971

#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1

1972

1973

#define LPDDR4__DENALI_PI_115_READ_MASK 0xFFFFFFFFU

1974

#define LPDDR4__DENALI_PI_115_WRITE_MASK 0xFFFFFFFFU

1975

#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU

1976

#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_SHIFT 0U

1977

#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_WIDTH 32U

1978

#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_115

1979

#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0

1980

1981

#define LPDDR4__DENALI_PI_116_READ_MASK 0x0000000FU

1982

#define LPDDR4__DENALI_PI_116_WRITE_MASK 0x0000000FU

1983

#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_MASK 0x0000000FU

1984

#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_SHIFT 0U

1985

#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_WIDTH 4U

1986

#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_116

1987

#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1

1988

1989

#define LPDDR4__DENALI_PI_117_READ_MASK 0xFFFFFFFFU

1990

#define LPDDR4__DENALI_PI_117_WRITE_MASK 0xFFFFFFFFU

1991

#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU

1992

#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_SHIFT 0U

1993

#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_WIDTH 32U

1994

#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_117

1995

#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0

1996

1997

#define LPDDR4__DENALI_PI_118_READ_MASK 0x0000000FU

1998

#define LPDDR4__DENALI_PI_118_WRITE_MASK 0x0000000FU

1999

#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_MASK 0x0000000FU

2000

#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_SHIFT 0U

2001

#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_WIDTH 4U

2002

#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_118

2003

#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1

2004

2005

#define LPDDR4__DENALI_PI_119_READ_MASK 0xFFFFFFFFU

2006

#define LPDDR4__DENALI_PI_119_WRITE_MASK 0xFFFFFFFFU

2007

#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU

2008

#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_SHIFT 0U

2009

#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_WIDTH 32U

2010

#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_119

2011

#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0

2012

2013

#define LPDDR4__DENALI_PI_120_READ_MASK 0x0303070FU

2014

#define LPDDR4__DENALI_PI_120_WRITE_MASK 0x0303070FU

2015

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_MASK 0x0000000FU

2016

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_SHIFT 0U

2017

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_WIDTH 4U

2018

#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_120

2019

#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1

2020

2021

#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_MASK 0x00000700U

2022

#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_SHIFT 8U

2023

#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_WIDTH 3U

2024

#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_120

2025

#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_MODE

2026

2027

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_MASK 0x00030000U

2028

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_SHIFT 16U

2029

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_WIDTH 2U

2030

#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_120

2031

#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE

2032

2033

#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_MASK 0x03000000U

2034

#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_SHIFT 24U

2035

#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_WIDTH 2U

2036

#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_120

2037

#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE

2038

2039

#define LPDDR4__DENALI_PI_121_READ_MASK 0xFFFFFFFFU

2040

#define LPDDR4__DENALI_PI_121_WRITE_MASK 0xFFFFFFFFU

2041

#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU

2042

#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_SHIFT 0U

2043

#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_WIDTH 32U

2044

#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_121

2045

#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0

2046

2047

#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU

2048

#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU

2049

#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU

2050

#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_SHIFT 0U

2051

#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_WIDTH 32U

2052

#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_122

2053

#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1

2054

2055

#define LPDDR4__DENALI_PI_123_READ_MASK 0xFFFFFFFFU

2056

#define LPDDR4__DENALI_PI_123_WRITE_MASK 0xFFFFFFFFU

2057

#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_MASK 0xFFFFFFFFU

2058

#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_SHIFT 0U

2059

#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_WIDTH 32U

2060

#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_123

2061

#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2

2062

2063

#define LPDDR4__DENALI_PI_124_READ_MASK 0xFFFFFFFFU

2064

#define LPDDR4__DENALI_PI_124_WRITE_MASK 0xFFFFFFFFU

2065

#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_MASK 0xFFFFFFFFU

2066

#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_SHIFT 0U

2067

#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_WIDTH 32U

2068

#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_124

2069

#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3

2070

2071

#define LPDDR4__DENALI_PI_125_READ_MASK 0x0000000FU

2072

#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x0000000FU

2073

#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_MASK 0x0000000FU

2074

#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_SHIFT 0U

2075

#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_WIDTH 4U

2076

#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_125

2077

#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM

2078

2079

#define LPDDR4__DENALI_PI_126_READ_MASK 0x3FFFFFFFU

2080

#define LPDDR4__DENALI_PI_126_WRITE_MASK 0x3FFFFFFFU

2081

#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU

2082

#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_SHIFT 0U

2083

#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_WIDTH 30U

2084

#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_126

2085

#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0

2086

2087

#define LPDDR4__DENALI_PI_127_READ_MASK 0x3FFFFFFFU

2088

#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x3FFFFFFFU

2089

#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU

2090

#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_SHIFT 0U

2091

#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_WIDTH 30U

2092

#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_127

2093

#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1

2094

2095

#define LPDDR4__DENALI_PI_128_READ_MASK 0x3FFFFFFFU

2096

#define LPDDR4__DENALI_PI_128_WRITE_MASK 0x3FFFFFFFU

2097

#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU

2098

#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_SHIFT 0U

2099

#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_WIDTH 30U

2100

#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_128

2101

#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2

2102

2103

#define LPDDR4__DENALI_PI_129_READ_MASK 0x3FFFFFFFU

2104

#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x3FFFFFFFU

2105

#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU

2106

#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_SHIFT 0U

2107

#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_WIDTH 30U

2108

#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_129

2109

#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3

2110

2111

#define LPDDR4__DENALI_PI_130_READ_MASK 0x3FFFFFFFU

2112

#define LPDDR4__DENALI_PI_130_WRITE_MASK 0x3FFFFFFFU

2113

#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU

2114

#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_SHIFT 0U

2115

#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_WIDTH 30U

2116

#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_130

2117

#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4

2118

2119

#define LPDDR4__DENALI_PI_131_READ_MASK 0x3FFFFFFFU

2120

#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x3FFFFFFFU

2121

#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU

2122

#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_SHIFT 0U

2123

#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_WIDTH 30U

2124

#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_131

2125

#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5

2126

2127

#define LPDDR4__DENALI_PI_132_READ_MASK 0x3FFFFFFFU

2128

#define LPDDR4__DENALI_PI_132_WRITE_MASK 0x3FFFFFFFU

2129

#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU

2130

#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_SHIFT 0U

2131

#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_WIDTH 30U

2132

#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_132

2133

#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6

2134

2135

#define LPDDR4__DENALI_PI_133_READ_MASK 0x3FFFFFFFU

2136

#define LPDDR4__DENALI_PI_133_WRITE_MASK 0x3FFFFFFFU

2137

#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU

2138

#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_SHIFT 0U

2139

#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_WIDTH 30U

2140

#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_133

2141

#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7

2142

2143

#define LPDDR4__DENALI_PI_134_READ_MASK 0x0101010FU

2144

#define LPDDR4__DENALI_PI_134_WRITE_MASK 0x0101010FU

2145

#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_MASK 0x0000000FU

2146

#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_SHIFT 0U

2147

#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_WIDTH 4U

2148

#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_134

2149

#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_134__PI_COL_DIFF

2150

2151

#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_MASK 0x00000100U

2152

#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_SHIFT 8U

2153

#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WIDTH 1U

2154

#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOCLR 0U

2155

#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOSET 0U

2156

#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_134

2157

#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN

2158

2159

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK 0x00010000U

2160

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT 16U

2161

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U

2162

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U

2163

#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET 0U

2164

#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134

2165

#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT

2166

2167

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x01000000U

2168

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 24U

2169

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U

2170

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U

2171

#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U

2172

#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134

2173

#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH

2174

2175

#define LPDDR4__DENALI_PI_135_READ_MASK 0x01010100U

2176

#define LPDDR4__DENALI_PI_135_WRITE_MASK 0x01010100U

2177

#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_MASK 0x00000001U

2178

#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_SHIFT 0U

2179

#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WIDTH 1U

2180

#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOCLR 0U

2181

#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOSET 0U

2182

#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_135

2183

#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ

2184

2185

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK 0x00000100U

2186

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT 8U

2187

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH 1U

2188

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR 0U

2189

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET 0U

2190

#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135

2191

#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT

2192

2193

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK 0x00010000U

2194

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT 16U

2195

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH 1U

2196

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR 0U

2197

#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET 0U

2198

#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135

2199

#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT

2200

2201

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x01000000U

2202

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 24U

2203

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U

2204

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U

2205

#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U

2206

#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135

2207

#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT

2208

2209

#define LPDDR4__DENALI_PI_136_READ_MASK 0x00000001U

2210

#define LPDDR4__DENALI_PI_136_WRITE_MASK 0x00000001U

2211

#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_MASK 0x00000001U

2212

#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_SHIFT 0U

2213

#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WIDTH 1U

2214

#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOCLR 0U

2215

#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOSET 0U

2216

#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_136

2217

#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT

2218

2219

#define LPDDR4__DENALI_PI_137_READ_MASK 0xFFFFFFFFU

2220

#define LPDDR4__DENALI_PI_137_WRITE_MASK 0xFFFFFFFFU

2221

#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_MASK 0xFFFFFFFFU

2222

#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_SHIFT 0U

2223

#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_WIDTH 32U

2224

#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_137

2225

#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_137__PI_TRST_PWRON

2226

2227

#define LPDDR4__DENALI_PI_138_READ_MASK 0xFFFFFFFFU

2228

#define LPDDR4__DENALI_PI_138_WRITE_MASK 0xFFFFFFFFU

2229

#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU

2230

#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_SHIFT 0U

2231

#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_WIDTH 32U

2232

#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_138

2233

#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE

2234

2235

#define LPDDR4__DENALI_PI_139_READ_MASK 0xFFFF0101U

2236

#define LPDDR4__DENALI_PI_139_WRITE_MASK 0xFFFF0101U

2237

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_MASK 0x00000001U

2238

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_SHIFT 0U

2239

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WIDTH 1U

2240

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOCLR 0U

2241

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOSET 0U

2242

#define LPDDR4__PI_DLL_RST__REG DENALI_PI_139

2243

#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST

2244

2245

#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_MASK 0x00000100U

2246

#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_SHIFT 8U

2247

#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WIDTH 1U

2248

#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOCLR 0U

2249

#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOSET 0U

2250

#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_139

2251

#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN

2252

2253

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_MASK 0xFFFF0000U

2254

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_SHIFT 16U

2255

#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_WIDTH 16U

2256

#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_139

2257

#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY

2258

2259

#define LPDDR4__DENALI_PI_140_READ_MASK 0x000000FFU

2260

#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x000000FFU

2261

#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU

2262

#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_SHIFT 0U

2263

#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_WIDTH 8U

2264

#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_140

2265

#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY

2266

2267

#define LPDDR4__DENALI_PI_141_READ_MASK 0x03FFFFFFU

2268

#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x03FFFFFFU

2269

#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_MASK 0x03FFFFFFU

2270

#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_SHIFT 0U

2271

#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_WIDTH 26U

2272

#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_141

2273

#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG

2274

2275

#define LPDDR4__DENALI_PI_142_READ_MASK 0x01FFFFFFU

2276

#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x01FFFFFFU

2277

#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_MASK 0x000000FFU

2278

#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_SHIFT 0U

2279

#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_WIDTH 8U

2280

#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_142

2281

#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_142__PI_MRW_STATUS

2282

2283

#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK 0x01FFFF00U

2284

#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT 8U

2285

#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH 17U

2286

#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142

2287

#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG

2288

2289

#define LPDDR4__DENALI_PI_143_READ_MASK 0x01FFFFFFU

2290

#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x01FFFFFFU

2291

#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU

2292

#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U

2293

#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U

2294

#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143

2295

#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0

2296

2297

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK 0x01000000U

2298

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT 24U

2299

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH 1U

2300

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR 0U

2301

#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET 0U

2302

#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143

2303

#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT

2304

2305

#define LPDDR4__DENALI_PI_144_READ_MASK 0x0101000FU

2306

#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x0101000FU

2307

#define LPDDR4__DENALI_PI_144__PI_RESERVED25_MASK 0x0000000FU

2308

#define LPDDR4__DENALI_PI_144__PI_RESERVED25_SHIFT 0U

2309

#define LPDDR4__DENALI_PI_144__PI_RESERVED25_WIDTH 4U

2310

#define LPDDR4__PI_RESERVED25__REG DENALI_PI_144

2311

#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_144__PI_RESERVED25

2312

2313

#define LPDDR4__DENALI_PI_144__PI_RESERVED26_MASK 0x00000F00U

2314

#define LPDDR4__DENALI_PI_144__PI_RESERVED26_SHIFT 8U

2315

#define LPDDR4__DENALI_PI_144__PI_RESERVED26_WIDTH 4U

2316

#define LPDDR4__PI_RESERVED26__REG DENALI_PI_144

2317

#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_144__PI_RESERVED26

2318

2319

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK 0x00010000U

2320

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT 16U

2321

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH 1U

2322

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR 0U

2323

#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET 0U

2324

#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144

2325

#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING

2326

2327

#define LPDDR4__DENALI_PI_144__PI_RESERVED27_MASK 0x01000000U

2328

#define LPDDR4__DENALI_PI_144__PI_RESERVED27_SHIFT 24U

2329

#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WIDTH 1U

2330

#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOCLR 0U

2331

#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOSET 0U

2332

#define LPDDR4__PI_RESERVED27__REG DENALI_PI_144

2333

#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_144__PI_RESERVED27

2334

2335

#define LPDDR4__DENALI_PI_145_READ_MASK 0xFF010F07U

2336

#define LPDDR4__DENALI_PI_145_WRITE_MASK 0xFF010F07U

2337

#define LPDDR4__DENALI_PI_145__PI_RESERVED28_MASK 0x00000007U

2338

#define LPDDR4__DENALI_PI_145__PI_RESERVED28_SHIFT 0U

2339

#define LPDDR4__DENALI_PI_145__PI_RESERVED28_WIDTH 3U

2340

#define LPDDR4__PI_RESERVED28__REG DENALI_PI_145

2341

#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_145__PI_RESERVED28

2342

2343

#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U

2344

#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT 8U

2345

#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH 4U

2346

#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145

2347

#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0

2348

2349

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U

2350

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT 16U

2351

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH 1U

2352

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR 0U

2353

#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET 0U

2354

#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145

2355

#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0

2356

2357

#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK 0xFF000000U

2358

#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT 24U

2359

#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH 8U

2360

#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145

2361

#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0

2362

2363

#define LPDDR4__DENALI_PI_146_READ_MASK 0x0FFF010FU

2364

#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x0FFF010FU

2365

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU

2366

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT 0U

2367

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH 4U

2368

#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146

2369

#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1

2370

2371

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U

2372

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT 8U

2373

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH 1U

2374

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR 0U

2375

#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET 0U

2376

#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146

2377

#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1

2378

2379

#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK 0x00FF0000U

2380

#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT 16U

2381

#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH 8U

2382

#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146

2383

#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1

2384

2385

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U

2386

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT 24U

2387

#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH 4U

2388

#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146

2389

#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2

2390

2391

#define LPDDR4__DENALI_PI_147_READ_MASK 0x010FFF01U

2392

#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x010FFF01U

2393

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U

2394

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT 0U

2395

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH 1U

2396

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR 0U

2397

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET 0U

2398

#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147

2399

#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2

2400

2401

#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK 0x0000FF00U

2402

#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT 8U

2403

#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH 8U

2404

#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147

2405

#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2

2406

2407

#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U

2408

#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT 16U

2409

#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH 4U

2410

#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147

2411

#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3

2412

2413

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U

2414

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT 24U

2415

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH 1U

2416

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR 0U

2417

#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET 0U

2418

#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147

2419

#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3

2420

2421

#define LPDDR4__DENALI_PI_148_READ_MASK 0xFF010FFFU

2422

#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFF010FFFU

2423

#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK 0x000000FFU

2424

#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT 0U

2425

#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH 8U

2426

#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148

2427

#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3

2428

2429

#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U

2430

#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT 8U

2431

#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH 4U

2432

#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148

2433

#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4

2434

2435

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U

2436

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT 16U

2437

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH 1U

2438

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR 0U

2439

#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET 0U

2440

#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148

2441

#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4

2442

2443

#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK 0xFF000000U

2444

#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT 24U

2445

#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH 8U

2446

#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148

2447

#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4

2448

2449

#define LPDDR4__DENALI_PI_149_READ_MASK 0x0FFF010FU

2450

#define LPDDR4__DENALI_PI_149_WRITE_MASK 0x0FFF010FU

2451

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU

2452

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT 0U

2453

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH 4U

2454

#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149

2455

#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5

2456

2457

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U

2458

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT 8U

2459

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH 1U

2460

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR 0U

2461

#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET 0U

2462

#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149

2463

#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5

2464

2465

#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK 0x00FF0000U

2466

#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT 16U

2467

#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH 8U

2468

#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149

2469

#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5

2470

2471

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U

2472

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT 24U

2473

#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH 4U

2474

#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149

2475

#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6

2476

2477

#define LPDDR4__DENALI_PI_150_READ_MASK 0x010FFF01U

2478

#define LPDDR4__DENALI_PI_150_WRITE_MASK 0x010FFF01U

2479

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U

2480

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT 0U

2481

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH 1U

2482

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR 0U

2483

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET 0U

2484

#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150

2485

#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6

2486

2487

#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK 0x0000FF00U

2488

#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT 8U

2489

#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH 8U

2490

#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150

2491

#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6

2492

2493

#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U

2494

#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT 16U

2495

#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH 4U

2496

#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150

2497

#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7

2498

2499

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U

2500

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT 24U

2501

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH 1U

2502

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR 0U

2503

#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET 0U

2504

#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150

2505

#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7

2506

2507

#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU

2508

#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU

2509

#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK 0x000000FFU

2510

#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT 0U

2511

#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH 8U

2512

#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151

2513

#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7

2514

2515

#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK 0x000000FFU

2516

#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT 0U

2517

#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH 8U

2518

#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152

2519

#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE

2520

2521

#define LPDDR4__DENALI_PI_153_READ_MASK 0x011F1F01U

2522

#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x011F1F01U

2523

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK 0x00000001U

2524

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT 0U

2525

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH 1U

2526

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR 0U

2527

#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET 0U

2528

#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153

2529

#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK

2530

2531

#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U

2532

#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT 8U

2533

#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH 5U

2534

#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153

2535

#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS

2536

2537

#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U

2538

#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT 16U

2539

#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH 5U

2540

#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153

2541

#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM

2542

2543

#define LPDDR4__DENALI_PI_153__PI_RESERVED29_MASK 0x01000000U

2544

#define LPDDR4__DENALI_PI_153__PI_RESERVED29_SHIFT 24U

2545

#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WIDTH 1U

2546

#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOCLR 0U

2547

#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOSET 0U

2548

#define LPDDR4__PI_RESERVED29__REG DENALI_PI_153

2549

#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_153__PI_RESERVED29

2550

2551

#define LPDDR4__DENALI_PI_154_READ_MASK 0x01010103U

2552

#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x01010103U

2553

#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK 0x00000003U

2554

#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT 0U

2555

#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH 2U

2556

#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154

2557

#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE

2558

2559

#define LPDDR4__DENALI_PI_154__PI_RESERVED30_MASK 0x00000100U

2560

#define LPDDR4__DENALI_PI_154__PI_RESERVED30_SHIFT 8U

2561

#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WIDTH 1U

2562

#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOCLR 0U

2563

#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOSET 0U

2564

#define LPDDR4__PI_RESERVED30__REG DENALI_PI_154

2565

#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_154__PI_RESERVED30

2566

2567

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK 0x00010000U

2568

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT 16U

2569

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH 1U

2570

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR 0U

2571

#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET 0U

2572

#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154

2573

#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN

2574

2575

#define LPDDR4__DENALI_PI_154__PI_RESERVED31_MASK 0x01000000U

2576

#define LPDDR4__DENALI_PI_154__PI_RESERVED31_SHIFT 24U

2577

#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WIDTH 1U

2578

#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOCLR 0U

2579

#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOSET 0U

2580

#define LPDDR4__PI_RESERVED31__REG DENALI_PI_154

2581

#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_154__PI_RESERVED31

2582

2583

#define LPDDR4__DENALI_PI_155_READ_MASK 0x01010101U

2584

#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01010101U

2585

#define LPDDR4__DENALI_PI_155__PI_RESERVED32_MASK 0x00000001U

2586

#define LPDDR4__DENALI_PI_155__PI_RESERVED32_SHIFT 0U

2587

#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WIDTH 1U

2588

#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOCLR 0U

2589

#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOSET 0U

2590

#define LPDDR4__PI_RESERVED32__REG DENALI_PI_155

2591

#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_155__PI_RESERVED32

2592

2593

#define LPDDR4__DENALI_PI_155__PI_RESERVED33_MASK 0x00000100U

2594

#define LPDDR4__DENALI_PI_155__PI_RESERVED33_SHIFT 8U

2595

#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WIDTH 1U

2596

#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOCLR 0U

2597

#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOSET 0U

2598

#define LPDDR4__PI_RESERVED33__REG DENALI_PI_155

2599

#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_155__PI_RESERVED33

2600

2601

#define LPDDR4__DENALI_PI_155__PI_RESERVED34_MASK 0x00010000U

2602

#define LPDDR4__DENALI_PI_155__PI_RESERVED34_SHIFT 16U

2603

#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WIDTH 1U

2604

#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOCLR 0U

2605

#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOSET 0U

2606

#define LPDDR4__PI_RESERVED34__REG DENALI_PI_155

2607

#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_155__PI_RESERVED34

2608

2609

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK 0x01000000U

2610

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT 24U

2611

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH 1U

2612

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR 0U

2613

#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET 0U

2614

#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155

2615

#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35

2616

2617

#define LPDDR4__DENALI_PI_156_READ_MASK 0x01010101U

2618

#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x01010101U

2619

#define LPDDR4__DENALI_PI_156__PI_RESERVED36_MASK 0x00000001U

2620

#define LPDDR4__DENALI_PI_156__PI_RESERVED36_SHIFT 0U

2621

#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WIDTH 1U

2622

#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOCLR 0U

2623

#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOSET 0U

2624

#define LPDDR4__PI_RESERVED36__REG DENALI_PI_156

2625

#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_156__PI_RESERVED36

2626

2627

#define LPDDR4__DENALI_PI_156__PI_RESERVED37_MASK 0x00000100U

2628

#define LPDDR4__DENALI_PI_156__PI_RESERVED37_SHIFT 8U

2629

#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WIDTH 1U

2630

#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOCLR 0U

2631

#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOSET 0U

2632

#define LPDDR4__PI_RESERVED37__REG DENALI_PI_156

2633

#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_156__PI_RESERVED37

2634

2635

#define LPDDR4__DENALI_PI_156__PI_RESERVED38_MASK 0x00010000U

2636

#define LPDDR4__DENALI_PI_156__PI_RESERVED38_SHIFT 16U

2637

#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WIDTH 1U

2638

#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOCLR 0U

2639

#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOSET 0U

2640

#define LPDDR4__PI_RESERVED38__REG DENALI_PI_156

2641

#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_156__PI_RESERVED38

2642

2643

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK 0x01000000U

2644

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT 24U

2645

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH 1U

2646

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR 0U

2647

#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET 0U

2648

#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156

2649

#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39

2650

2651

#define LPDDR4__DENALI_PI_157_READ_MASK 0x01010101U

2652

#define LPDDR4__DENALI_PI_157_WRITE_MASK 0x01010101U

2653

#define LPDDR4__DENALI_PI_157__PI_RESERVED40_MASK 0x00000001U

2654

#define LPDDR4__DENALI_PI_157__PI_RESERVED40_SHIFT 0U

2655

#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WIDTH 1U

2656

#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOCLR 0U

2657

#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOSET 0U

2658

#define LPDDR4__PI_RESERVED40__REG DENALI_PI_157

2659

#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_157__PI_RESERVED40

2660

2661

#define LPDDR4__DENALI_PI_157__PI_RESERVED41_MASK 0x00000100U

2662

#define LPDDR4__DENALI_PI_157__PI_RESERVED41_SHIFT 8U

2663

#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WIDTH 1U

2664

#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOCLR 0U

2665

#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOSET 0U

2666

#define LPDDR4__PI_RESERVED41__REG DENALI_PI_157

2667

#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_157__PI_RESERVED41

2668

2669

#define LPDDR4__DENALI_PI_157__PI_RESERVED42_MASK 0x00010000U

2670

#define LPDDR4__DENALI_PI_157__PI_RESERVED42_SHIFT 16U

2671

#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WIDTH 1U

2672

#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOCLR 0U

2673

#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOSET 0U

2674

#define LPDDR4__PI_RESERVED42__REG DENALI_PI_157

2675

#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_157__PI_RESERVED42

2676

2677

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK 0x01000000U

2678

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT 24U

2679

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH 1U

2680

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR 0U

2681

#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET 0U

2682

#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157

2683

#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43

2684

2685

#define LPDDR4__DENALI_PI_158_READ_MASK 0x01010101U

2686

#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x01010101U

2687

#define LPDDR4__DENALI_PI_158__PI_RESERVED44_MASK 0x00000001U

2688

#define LPDDR4__DENALI_PI_158__PI_RESERVED44_SHIFT 0U

2689

#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WIDTH 1U

2690

#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOCLR 0U

2691

#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOSET 0U

2692

#define LPDDR4__PI_RESERVED44__REG DENALI_PI_158

2693

#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_158__PI_RESERVED44

2694

2695

#define LPDDR4__DENALI_PI_158__PI_RESERVED45_MASK 0x00000100U

2696

#define LPDDR4__DENALI_PI_158__PI_RESERVED45_SHIFT 8U

2697

#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WIDTH 1U

2698

#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOCLR 0U

2699

#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOSET 0U

2700

#define LPDDR4__PI_RESERVED45__REG DENALI_PI_158

2701

#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_158__PI_RESERVED45

2702

2703

#define LPDDR4__DENALI_PI_158__PI_RESERVED46_MASK 0x00010000U

2704

#define LPDDR4__DENALI_PI_158__PI_RESERVED46_SHIFT 16U

2705

#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WIDTH 1U

2706

#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOCLR 0U

2707

#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOSET 0U

2708

#define LPDDR4__PI_RESERVED46__REG DENALI_PI_158

2709

#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_158__PI_RESERVED46

2710

2711

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK 0x01000000U

2712

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT 24U

2713

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH 1U

2714

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR 0U

2715

#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET 0U

2716

#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158

2717

#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47

2718

2719

#define LPDDR4__DENALI_PI_159_READ_MASK 0x0001FFFFU

2720

#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x0001FFFFU

2721

#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK 0x000000FFU

2722

#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT 0U

2723

#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U

2724

#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159

2725

#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND

2726

2727

#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_MASK 0x0001FF00U

2728

#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_SHIFT 8U

2729

#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_WIDTH 9U

2730

#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_159

2731

#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_159__PI_TREFBW_THR

2732

2733

#define LPDDR4__DENALI_PI_160_READ_MASK 0x0000001FU

2734

#define LPDDR4__DENALI_PI_160_WRITE_MASK 0x0000001FU

2735

#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU

2736

#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U

2737

#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U

2738

#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_160

2739

#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY

2740

2741

#define LPDDR4__DENALI_PI_161_READ_MASK 0x0F011F01U

2742

#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0F011F01U

2743

#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U

2744

#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U

2745

#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U

2746

#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U

2747

#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOSET 0U

2748

#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_161

2749

#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF

2750

2751

#define LPDDR4__DENALI_PI_161__PI_RESERVED48_MASK 0x00001F00U

2752

#define LPDDR4__DENALI_PI_161__PI_RESERVED48_SHIFT 8U

2753

#define LPDDR4__DENALI_PI_161__PI_RESERVED48_WIDTH 5U

2754

#define LPDDR4__PI_RESERVED48__REG DENALI_PI_161

2755

#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_161__PI_RESERVED48

2756

2757

#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_MASK 0x00010000U

2758

#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_SHIFT 16U

2759

#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WIDTH 1U

2760

#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOCLR 0U

2761

#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOSET 0U

2762

#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_161

2763

#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN

2764

2765

#define LPDDR4__DENALI_PI_161__PI_CATR_MASK 0x0F000000U

2766

#define LPDDR4__DENALI_PI_161__PI_CATR_SHIFT 24U

2767

#define LPDDR4__DENALI_PI_161__PI_CATR_WIDTH 4U

2768

#define LPDDR4__PI_CATR__REG DENALI_PI_161

2769

#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_161__PI_CATR

2770

2771

#define LPDDR4__DENALI_PI_162_READ_MASK 0x01010101U

2772

#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x01010101U

2773

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK 0x00000001U

2774

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT 0U

2775

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH 1U

2776

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR 0U

2777

#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET 0U

2778

#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162

2779

#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ

2780

2781

#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_MASK 0x00000100U

2782

#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_SHIFT 8U

2783

#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WIDTH 1U

2784

#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOCLR 0U

2785

#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOSET 0U

2786

#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_162

2787

#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE

2788

2789

#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_MASK 0x00010000U

2790

#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_SHIFT 16U

2791

#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WIDTH 1U

2792

#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOCLR 0U

2793

#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOSET 0U

2794

#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_162

2795

#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC

2796

2797

#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_MASK 0x01000000U

2798

#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_SHIFT 24U

2799

#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WIDTH 1U

2800

#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOCLR 0U

2801

#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOSET 0U

2802

#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_162

2803

#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START

2804

2805

#define LPDDR4__DENALI_PI_163_READ_MASK 0xFFFFFF01U

2806

#define LPDDR4__DENALI_PI_163_WRITE_MASK 0xFFFFFF01U

2807

#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_MASK 0x00000001U

2808

#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_SHIFT 0U

2809

#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WIDTH 1U

2810

#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOCLR 0U

2811

#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOSET 0U

2812

#define LPDDR4__PI_TRACE_MC_MR13__REG DENALI_PI_163

2813

#define LPDDR4__PI_TRACE_MC_MR13__FLD LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13

2814

2815

#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_MASK 0x0000FF00U

2816

#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_SHIFT 8U

2817

#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_WIDTH 8U

2818

#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_163

2819

#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F0

2820

2821

#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_MASK 0x00FF0000U

2822

#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_SHIFT 16U

2823

#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_WIDTH 8U

2824

#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_163

2825

#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F1

2826

2827

#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_MASK 0xFF000000U

2828

#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_SHIFT 24U

2829

#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_WIDTH 8U

2830

#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_163

2831

#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F2

2832

2833

#define LPDDR4__DENALI_PI_164_READ_MASK 0x000000FFU

2834

#define LPDDR4__DENALI_PI_164_WRITE_MASK 0x000000FFU

2835

#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU

2836

#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U

2837

#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U

2838

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_164

2839

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0

2840

2841

#define LPDDR4__DENALI_PI_165_READ_MASK 0x000000FFU

2842

#define LPDDR4__DENALI_PI_165_WRITE_MASK 0x000000FFU

2843

#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU

2844

#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U

2845

#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U

2846

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_165

2847

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1

2848

2849

#define LPDDR4__DENALI_PI_166_READ_MASK 0x000FFFFFU

2850

#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x000FFFFFU

2851

#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU

2852

#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U

2853

#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U

2854

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_166

2855

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2

2856

2857

#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_MASK 0x000FFF00U

2858

#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_SHIFT 8U

2859

#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_WIDTH 12U

2860

#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_166

2861

#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_166__PI_ZQINIT_F0

2862

2863

#define LPDDR4__DENALI_PI_167_READ_MASK 0x0FFF0FFFU

2864

#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x0FFF0FFFU

2865

#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_MASK 0x00000FFFU

2866

#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_SHIFT 0U

2867

#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_WIDTH 12U

2868

#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_167

2869

#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F1

2870

2871

#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_MASK 0x0FFF0000U

2872

#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_SHIFT 16U

2873

#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_WIDTH 12U

2874

#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_167

2875

#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F2

2876

2877

#define LPDDR4__DENALI_PI_168_READ_MASK 0x7F7F7F7FU

2878

#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x7F7F7F7FU

2879

#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_MASK 0x0000007FU

2880

#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_SHIFT 0U

2881

#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_WIDTH 7U

2882

#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_168

2883

#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F0

2884

2885

#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_MASK 0x00007F00U

2886

#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_SHIFT 8U

2887

#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_WIDTH 7U

2888

#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_168

2889

#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0

2890

2891

#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_MASK 0x007F0000U

2892

#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_SHIFT 16U

2893

#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_WIDTH 7U

2894

#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_168

2895

#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F1

2896

2897

#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_MASK 0x7F000000U

2898

#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_SHIFT 24U

2899

#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_WIDTH 7U

2900

#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_168

2901

#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1

2902

2903

#define LPDDR4__DENALI_PI_169_READ_MASK 0x03FF7F7FU

2904

#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x03FF7F7FU

2905

#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_MASK 0x0000007FU

2906

#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_SHIFT 0U

2907

#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_WIDTH 7U

2908

#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_169

2909

#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_169__PI_WRLAT_F2

2910

2911

#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_MASK 0x00007F00U

2912

#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_SHIFT 8U

2913

#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_WIDTH 7U

2914

#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_169

2915

#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2

2916

2917

#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_MASK 0x03FF0000U

2918

#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_SHIFT 16U

2919

#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_WIDTH 10U

2920

#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_169

2921

#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_169__PI_TRFC_F0

2922

2923

#define LPDDR4__DENALI_PI_170_READ_MASK 0x000FFFFFU

2924

#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x000FFFFFU

2925

#define LPDDR4__DENALI_PI_170__PI_TREF_F0_MASK 0x000FFFFFU

2926

#define LPDDR4__DENALI_PI_170__PI_TREF_F0_SHIFT 0U

2927

#define LPDDR4__DENALI_PI_170__PI_TREF_F0_WIDTH 20U

2928

#define LPDDR4__PI_TREF_F0__REG DENALI_PI_170

2929

#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_170__PI_TREF_F0

2930

2931

#define LPDDR4__DENALI_PI_171_READ_MASK 0x000003FFU

2932

#define LPDDR4__DENALI_PI_171_WRITE_MASK 0x000003FFU

2933

#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_MASK 0x000003FFU

2934

#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_SHIFT 0U

2935

#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_WIDTH 10U

2936

#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_171

2937

#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_171__PI_TRFC_F1

2938

2939

#define LPDDR4__DENALI_PI_172_READ_MASK 0x000FFFFFU

2940

#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x000FFFFFU

2941

#define LPDDR4__DENALI_PI_172__PI_TREF_F1_MASK 0x000FFFFFU

2942

#define LPDDR4__DENALI_PI_172__PI_TREF_F1_SHIFT 0U

2943

#define LPDDR4__DENALI_PI_172__PI_TREF_F1_WIDTH 20U

2944

#define LPDDR4__PI_TREF_F1__REG DENALI_PI_172

2945

#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_172__PI_TREF_F1

2946

2947

#define LPDDR4__DENALI_PI_173_READ_MASK 0x000003FFU

2948

#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x000003FFU

2949

#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_MASK 0x000003FFU

2950

#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_SHIFT 0U

2951

#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_WIDTH 10U

2952

#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_173

2953

#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_173__PI_TRFC_F2

2954

2955

#define LPDDR4__DENALI_PI_174_READ_MASK 0x0F0FFFFFU

2956

#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x0F0FFFFFU

2957

#define LPDDR4__DENALI_PI_174__PI_TREF_F2_MASK 0x000FFFFFU

2958

#define LPDDR4__DENALI_PI_174__PI_TREF_F2_SHIFT 0U

2959

#define LPDDR4__DENALI_PI_174__PI_TREF_F2_WIDTH 20U

2960

#define LPDDR4__PI_TREF_F2__REG DENALI_PI_174

2961

#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_174__PI_TREF_F2

2962

2963

#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U

2964

#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U

2965

#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U

2966

#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_174

2967

#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0

2968

2969

#define LPDDR4__DENALI_PI_175_READ_MASK 0x03030F0FU

2970

#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x03030F0FU

2971

#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU

2972

#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U

2973

#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U

2974

#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_175

2975

#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1

2976

2977

#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U

2978

#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U

2979

#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U

2980

#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_175

2981

#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2

2982

2983

#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_MASK 0x00030000U

2984

#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_SHIFT 16U

2985

#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_WIDTH 2U

2986

#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_175

2987

#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0

2988

2989

#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_MASK 0x03000000U

2990

#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_SHIFT 24U

2991

#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_WIDTH 2U

2992

#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_175

2993

#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1

2994

2995

#define LPDDR4__DENALI_PI_176_READ_MASK 0x0003FF03U

2996

#define LPDDR4__DENALI_PI_176_WRITE_MASK 0x0003FF03U

2997

#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_MASK 0x00000003U

2998

#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_SHIFT 0U

2999

#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_WIDTH 2U

3000

#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_176

3001

#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2

3002

3003

#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U

3004

#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_SHIFT 8U

3005

#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_WIDTH 10U

3006

#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_176

3007

#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0

3008

3009

#define LPDDR4__DENALI_PI_177_READ_MASK 0x03FF03FFU

3010

#define LPDDR4__DENALI_PI_177_WRITE_MASK 0x03FF03FFU

3011

#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU

3012

#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_SHIFT 0U

3013

#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_WIDTH 10U

3014

#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_177

3015

#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1

3016

3017

#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U

3018

#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_SHIFT 16U

3019

#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_WIDTH 10U

3020

#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_177

3021

#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2

3022

3023

#define LPDDR4__DENALI_PI_178_READ_MASK 0x01FF01FFU

3024

#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x01FF01FFU

3025

#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_MASK 0x000000FFU

3026

#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_SHIFT 0U

3027

#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_WIDTH 8U

3028

#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_178

3029

#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0

3030

3031

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_MASK 0x00000100U

3032

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_SHIFT 8U

3033

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WIDTH 1U

3034

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOCLR 0U

3035

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOSET 0U

3036

#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_178

3037

#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F0

3038

3039

#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_MASK 0x00FF0000U

3040

#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_SHIFT 16U

3041

#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_WIDTH 8U

3042

#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_178

3043

#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1

3044

3045

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_MASK 0x01000000U

3046

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_SHIFT 24U

3047

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WIDTH 1U

3048

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOCLR 0U

3049

#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOSET 0U

3050

#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_178

3051

#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F1

3052

3053

#define LPDDR4__DENALI_PI_179_READ_MASK 0x0F0F01FFU

3054

#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x0F0F01FFU

3055

#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_MASK 0x000000FFU

3056

#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_SHIFT 0U

3057

#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_WIDTH 8U

3058

#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_179

3059

#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2

3060

3061

#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_MASK 0x00000100U

3062

#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_SHIFT 8U

3063

#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WIDTH 1U

3064

#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOCLR 0U

3065

#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOSET 0U

3066

#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_179

3067

#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_179__PI_ODT_EN_F2

3068

3069

#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_MASK 0x000F0000U

3070

#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_SHIFT 16U

3071

#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_WIDTH 4U

3072

#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_179

3073

#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_179__PI_ODTLON_F0

3074

3075

#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_MASK 0x0F000000U

3076

#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_SHIFT 24U

3077

#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_WIDTH 4U

3078

#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_179

3079

#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0

3080

3081

#define LPDDR4__DENALI_PI_180_READ_MASK 0x0F0F0F0FU

3082

#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x0F0F0F0FU

3083

#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_MASK 0x0000000FU

3084

#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_SHIFT 0U

3085

#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_WIDTH 4U

3086

#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_180

3087

#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F1

3088

3089

#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_MASK 0x00000F00U

3090

#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_SHIFT 8U

3091

#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_WIDTH 4U

3092

#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_180

3093

#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1

3094

3095

#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_MASK 0x000F0000U

3096

#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_SHIFT 16U

3097

#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_WIDTH 4U

3098

#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_180

3099

#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F2

3100

3101

#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_MASK 0x0F000000U

3102

#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_SHIFT 24U

3103

#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_WIDTH 4U

3104

#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_180

3105

#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2

3106

3107

#define LPDDR4__DENALI_PI_181_READ_MASK 0x03030303U

3108

#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x03030303U

3109

#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_MASK 0x00000003U

3110

#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_SHIFT 0U

3111

#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_WIDTH 2U

3112

#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_181

3113

#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0

3114

3115

#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_MASK 0x00000300U

3116

#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_SHIFT 8U

3117

#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_WIDTH 2U

3118

#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_181

3119

#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0

3120

3121

#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_MASK 0x00030000U

3122

#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_SHIFT 16U

3123

#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_WIDTH 2U

3124

#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_181

3125

#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1

3126

3127

#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_MASK 0x03000000U

3128

#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_SHIFT 24U

3129

#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_WIDTH 2U

3130

#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_181

3131

#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1

3132

3133

#define LPDDR4__DENALI_PI_182_READ_MASK 0x03030303U

3134

#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x03030303U

3135

#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_MASK 0x00000003U

3136

#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_SHIFT 0U

3137

#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_WIDTH 2U

3138

#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_182

3139

#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2

3140

3141

#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_MASK 0x00000300U

3142

#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_SHIFT 8U

3143

#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_WIDTH 2U

3144

#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_182

3145

#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2

3146

3147

#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_MASK 0x00030000U

3148

#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_SHIFT 16U

3149

#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_WIDTH 2U

3150

#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_182

3151

#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0

3152

3153

#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_MASK 0x03000000U

3154

#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_SHIFT 24U

3155

#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U

3156

#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_182

3157

#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0

3158

3159

#define LPDDR4__DENALI_PI_183_READ_MASK 0x03030303U

3160

#define LPDDR4__DENALI_PI_183_WRITE_MASK 0x03030303U

3161

#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_MASK 0x00000003U

3162

#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_SHIFT 0U

3163

#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_WIDTH 2U

3164

#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_183

3165

#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0

3166

3167

#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_MASK 0x00000300U

3168

#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_SHIFT 8U

3169

#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_WIDTH 2U

3170

#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_183

3171

#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0

3172

3173

#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_MASK 0x00030000U

3174

#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_SHIFT 16U

3175

#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_WIDTH 2U

3176

#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_183

3177

#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1

3178

3179

#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_MASK 0x03000000U

3180

#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_SHIFT 24U

3181

#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U

3182

#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_183

3183

#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1

3184

3185

#define LPDDR4__DENALI_PI_184_READ_MASK 0x03030303U

3186

#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x03030303U

3187

#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_MASK 0x00000003U

3188

#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_SHIFT 0U

3189

#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_WIDTH 2U

3190

#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_184

3191

#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1

3192

3193

#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_MASK 0x00000300U

3194

#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_SHIFT 8U

3195

#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_WIDTH 2U

3196

#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_184

3197

#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1

3198

3199

#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_MASK 0x00030000U

3200

#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_SHIFT 16U

3201

#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_WIDTH 2U

3202

#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_184

3203

#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2

3204

3205

#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_MASK 0x03000000U

3206

#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_SHIFT 24U

3207

#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U

3208

#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_184

3209

#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2

3210

3211

#define LPDDR4__DENALI_PI_185_READ_MASK 0x7F7F0303U

3212

#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x7F7F0303U

3213

#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_MASK 0x00000003U

3214

#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_SHIFT 0U

3215

#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_WIDTH 2U

3216

#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_185

3217

#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2

3218

3219

#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_MASK 0x00000300U

3220

#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_SHIFT 8U

3221

#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_WIDTH 2U

3222

#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_185

3223

#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2

3224

3225

#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_MASK 0x007F0000U

3226

#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_SHIFT 16U

3227

#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_WIDTH 7U

3228

#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_185

3229

#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0

3230

3231

#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_MASK 0x7F000000U

3232

#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_SHIFT 24U

3233

#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_WIDTH 7U

3234

#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_185

3235

#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1

3236

3237

#define LPDDR4__DENALI_PI_186_READ_MASK 0x7F7F7F7FU

3238

#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x7F7F7F7FU

3239

#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_MASK 0x0000007FU

3240

#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_SHIFT 0U

3241

#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_WIDTH 7U

3242

#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_186

3243

#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2

3244

3245

#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_MASK 0x00007F00U

3246

#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_SHIFT 8U

3247

#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_WIDTH 7U

3248

#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_186

3249

#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0

3250

3251

#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_MASK 0x007F0000U

3252

#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_SHIFT 16U

3253

#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_WIDTH 7U

3254

#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_186

3255

#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1

3256

3257

#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_MASK 0x7F000000U

3258

#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_SHIFT 24U

3259

#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_WIDTH 7U

3260

#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_186

3261

#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2

3262

3263

#define LPDDR4__DENALI_PI_187_READ_MASK 0x00070707U

3264

#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x00070707U

3265

#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000007U

3266

#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_SHIFT 0U

3267

#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U

3268

#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_187

3269

#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0

3270

3271

#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_MASK 0x00000700U

3272

#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_SHIFT 8U

3273

#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U

3274

#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_187

3275

#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1

3276

3277

#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_MASK 0x00070000U

3278

#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_SHIFT 16U

3279

#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U

3280

#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_187

3281

#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2

3282

3283

#define LPDDR4__DENALI_PI_188_READ_MASK 0x03FF03FFU

3284

#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x03FF03FFU

3285

#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU

3286

#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_SHIFT 0U

3287

#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_WIDTH 10U

3288

#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_188

3289

#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0

3290

3291

#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U

3292

#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U

3293

#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U

3294

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_188

3295

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0

3296

3297

#define LPDDR4__DENALI_PI_189_READ_MASK 0x03FF03FFU

3298

#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x03FF03FFU

3299

#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU

3300

#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_SHIFT 0U

3301

#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_WIDTH 10U

3302

#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_189

3303

#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1

3304

3305

#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U

3306

#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U

3307

#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U

3308

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_189

3309

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1

3310

3311

#define LPDDR4__DENALI_PI_190_READ_MASK 0x03FF03FFU

3312

#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x03FF03FFU

3313

#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU

3314

#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_SHIFT 0U

3315

#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_WIDTH 10U

3316

#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_190

3317

#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2

3318

3319

#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U

3320

#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U

3321

#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U

3322

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_190

3323

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2

3324

3325

#define LPDDR4__DENALI_PI_191_READ_MASK 0x1F030303U

3326

#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x1F030303U

3327

#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_MASK 0x00000003U

3328

#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_SHIFT 0U

3329

#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_WIDTH 2U

3330

#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_191

3331

#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0

3332

3333

#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_MASK 0x00000300U

3334

#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_SHIFT 8U

3335

#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_WIDTH 2U

3336

#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_191

3337

#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1

3338

3339

#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_MASK 0x00030000U

3340

#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_SHIFT 16U

3341

#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_WIDTH 2U

3342

#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_191

3343

#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2

3344

3345

#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_MASK 0x1F000000U

3346

#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_SHIFT 24U

3347

#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_WIDTH 5U

3348

#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_191

3349

#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_191__PI_TMRZ_F0

3350

3351

#define LPDDR4__DENALI_PI_192_READ_MASK 0x001F3FFFU

3352

#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x001F3FFFU

3353

#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_MASK 0x00003FFFU

3354

#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_SHIFT 0U

3355

#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_WIDTH 14U

3356

#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_192

3357

#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_192__PI_TCAENT_F0

3358

3359

#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_MASK 0x001F0000U

3360

#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_SHIFT 16U

3361

#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_WIDTH 5U

3362

#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_192

3363

#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_192__PI_TMRZ_F1

3364

3365

#define LPDDR4__DENALI_PI_193_READ_MASK 0x001F3FFFU

3366

#define LPDDR4__DENALI_PI_193_WRITE_MASK 0x001F3FFFU

3367

#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_MASK 0x00003FFFU

3368

#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_SHIFT 0U

3369

#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_WIDTH 14U

3370

#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_193

3371

#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_193__PI_TCAENT_F1

3372

3373

#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_MASK 0x001F0000U

3374

#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_SHIFT 16U

3375

#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_WIDTH 5U

3376

#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_193

3377

#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_193__PI_TMRZ_F2

3378

3379

#define LPDDR4__DENALI_PI_194_READ_MASK 0x1F1F3FFFU

3380

#define LPDDR4__DENALI_PI_194_WRITE_MASK 0x1F1F3FFFU

3381

#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_MASK 0x00003FFFU

3382

#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_SHIFT 0U

3383

#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_WIDTH 14U

3384

#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_194

3385

#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_194__PI_TCAENT_F2

3386

3387

#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_MASK 0x001F0000U

3388

#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_SHIFT 16U

3389

#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_WIDTH 5U

3390

#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_194

3391

#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0

3392

3393

#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_MASK 0x1F000000U

3394

#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_SHIFT 24U

3395

#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_WIDTH 5U

3396

#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_194

3397

#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0

3398

3399

#define LPDDR4__DENALI_PI_195_READ_MASK 0x03FF03FFU

3400

#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x03FF03FFU

3401

#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_MASK 0x000003FFU

3402

#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_SHIFT 0U

3403

#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_WIDTH 10U

3404

#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_195

3405

#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0

3406

3407

#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_MASK 0x03FF0000U

3408

#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_SHIFT 16U

3409

#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_WIDTH 10U

3410

#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_195

3411

#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0

3412

3413

#define LPDDR4__DENALI_PI_196_READ_MASK 0x03FF1F1FU

3414

#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x03FF1F1FU

3415

#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_MASK 0x0000001FU

3416

#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_SHIFT 0U

3417

#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_WIDTH 5U

3418

#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_196

3419

#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1

3420

3421

#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_MASK 0x00001F00U

3422

#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_SHIFT 8U

3423

#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_WIDTH 5U

3424

#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_196

3425

#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1

3426

3427

#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_MASK 0x03FF0000U

3428

#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_SHIFT 16U

3429

#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_WIDTH 10U

3430

#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_196

3431

#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1

3432

3433

#define LPDDR4__DENALI_PI_197_READ_MASK 0x1F1F03FFU

3434

#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x1F1F03FFU

3435

#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_MASK 0x000003FFU

3436

#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_SHIFT 0U

3437

#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_WIDTH 10U

3438

#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_197

3439

#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1

3440

3441

#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_MASK 0x001F0000U

3442

#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_SHIFT 16U

3443

#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_WIDTH 5U

3444

#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_197

3445

#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2

3446

3447

#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_MASK 0x1F000000U

3448

#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_SHIFT 24U

3449

#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_WIDTH 5U

3450

#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_197

3451

#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2

3452

3453

#define LPDDR4__DENALI_PI_198_READ_MASK 0x03FF03FFU

3454

#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x03FF03FFU

3455

#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_MASK 0x000003FFU

3456

#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_SHIFT 0U

3457

#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_WIDTH 10U

3458

#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_198

3459

#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2

3460

3461

#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_MASK 0x03FF0000U

3462

#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_SHIFT 16U

3463

#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_WIDTH 10U

3464

#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_198

3465

#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2

3466

3467

#define LPDDR4__DENALI_PI_199_READ_MASK 0x7F7F7F7FU

3468

#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x7F7F7F7FU

3469

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU

3470

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U

3471

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U

3472

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_199

3473

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0

3474

3475

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U

3476

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U

3477

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U

3478

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_199

3479

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0

3480

3481

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U

3482

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U

3483

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U

3484

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_199

3485

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1

3486

3487

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U

3488

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U

3489

#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U

3490

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_199

3491

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1

3492

3493

#define LPDDR4__DENALI_PI_200_READ_MASK 0x0F0F7F7FU

3494

#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x0F0F7F7FU

3495

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU

3496

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U

3497

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U

3498

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_200

3499

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2

3500

3501

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U

3502

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U

3503

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U

3504

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_200

3505

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2

3506

3507

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U

3508

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_SHIFT 16U

3509

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_WIDTH 4U

3510

#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_200

3511

#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0

3512

3513

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U

3514

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_SHIFT 24U

3515

#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_WIDTH 4U

3516

#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_200

3517

#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1

3518

3519

#define LPDDR4__DENALI_PI_201_READ_MASK 0xFF1F0F0FU

3520

#define LPDDR4__DENALI_PI_201_WRITE_MASK 0xFF1F0F0FU

3521

#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU

3522

#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_SHIFT 0U

3523

#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_WIDTH 4U

3524

#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_201

3525

#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2

3526

3527

#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U

3528

#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U

3529

#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U

3530

#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_201

3531

#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0

3532

3533

#define LPDDR4__DENALI_PI_201__PI_TXP_F0_MASK 0x001F0000U

3534

#define LPDDR4__DENALI_PI_201__PI_TXP_F0_SHIFT 16U

3535

#define LPDDR4__DENALI_PI_201__PI_TXP_F0_WIDTH 5U

3536

#define LPDDR4__PI_TXP_F0__REG DENALI_PI_201

3537

#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_201__PI_TXP_F0

3538

3539

#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_MASK 0xFF000000U

3540

#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_SHIFT 24U

3541

#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_WIDTH 8U

3542

#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_201

3543

#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0

3544

3545

#define LPDDR4__DENALI_PI_202_READ_MASK 0xFF1F0F1FU

3546

#define LPDDR4__DENALI_PI_202_WRITE_MASK 0xFF1F0F1FU

3547

#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_MASK 0x0000001FU

3548

#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_SHIFT 0U

3549

#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_WIDTH 5U

3550

#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_202

3551

#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_202__PI_TCKELCK_F0

3552

3553

#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U

3554

#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U

3555

#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U

3556

#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_202

3557

#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1

3558

3559

#define LPDDR4__DENALI_PI_202__PI_TXP_F1_MASK 0x001F0000U

3560

#define LPDDR4__DENALI_PI_202__PI_TXP_F1_SHIFT 16U

3561

#define LPDDR4__DENALI_PI_202__PI_TXP_F1_WIDTH 5U

3562

#define LPDDR4__PI_TXP_F1__REG DENALI_PI_202

3563

#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_202__PI_TXP_F1

3564

3565

#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_MASK 0xFF000000U

3566

#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_SHIFT 24U

3567

#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_WIDTH 8U

3568

#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_202

3569

#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1

3570

3571

#define LPDDR4__DENALI_PI_203_READ_MASK 0xFF1F0F1FU

3572

#define LPDDR4__DENALI_PI_203_WRITE_MASK 0xFF1F0F1FU

3573

#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_MASK 0x0000001FU

3574

#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_SHIFT 0U

3575

#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_WIDTH 5U

3576

#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_203

3577

#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_203__PI_TCKELCK_F1

3578

3579

#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U

3580

#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U

3581

#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U

3582

#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_203

3583

#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2

3584

3585

#define LPDDR4__DENALI_PI_203__PI_TXP_F2_MASK 0x001F0000U

3586

#define LPDDR4__DENALI_PI_203__PI_TXP_F2_SHIFT 16U

3587

#define LPDDR4__DENALI_PI_203__PI_TXP_F2_WIDTH 5U

3588

#define LPDDR4__PI_TXP_F2__REG DENALI_PI_203

3589

#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_203__PI_TXP_F2

3590

3591

#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_MASK 0xFF000000U

3592

#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_SHIFT 24U

3593

#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_WIDTH 8U

3594

#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_203

3595

#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2

3596

3597

#define LPDDR4__DENALI_PI_204_READ_MASK 0x0003FF1FU

3598

#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x0003FF1FU

3599

#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_MASK 0x0000001FU

3600

#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_SHIFT 0U

3601

#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_WIDTH 5U

3602

#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_204

3603

#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_204__PI_TCKELCK_F2

3604

3605

#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_MASK 0x0003FF00U

3606

#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_SHIFT 8U

3607

#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_WIDTH 10U

3608

#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_204

3609

#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0

3610

3611

#define LPDDR4__DENALI_PI_205_READ_MASK 0x03FFFFFFU

3612

#define LPDDR4__DENALI_PI_205_WRITE_MASK 0x03FFFFFFU

3613

#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_MASK 0x0000FFFFU

3614

#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U

3615

#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_WIDTH 16U

3616

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_205

3617

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0

3618

3619

#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_MASK 0x03FF0000U

3620

#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_SHIFT 16U

3621

#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_WIDTH 10U

3622

#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_205

3623

#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1

3624

3625

#define LPDDR4__DENALI_PI_206_READ_MASK 0x03FFFFFFU

3626

#define LPDDR4__DENALI_PI_206_WRITE_MASK 0x03FFFFFFU

3627

#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_MASK 0x0000FFFFU

3628

#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U

3629

#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_WIDTH 16U

3630

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_206

3631

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1

3632

3633

#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_MASK 0x03FF0000U

3634

#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_SHIFT 16U

3635

#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_WIDTH 10U

3636

#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_206

3637

#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2

3638

3639

#define LPDDR4__DENALI_PI_207_READ_MASK 0x003FFFFFU

3640

#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x003FFFFFU

3641

#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_MASK 0x0000FFFFU

3642

#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U

3643

#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_WIDTH 16U

3644

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_207

3645

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2

3646

3647

#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_MASK 0x003F0000U

3648

#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_SHIFT 16U

3649

#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_WIDTH 6U

3650

#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_207

3651

#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0

3652

3653

#define LPDDR4__DENALI_PI_208_READ_MASK 0x003F03FFU

3654

#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x003F03FFU

3655

#define LPDDR4__DENALI_PI_208__PI_TFC_F0_MASK 0x000003FFU

3656

#define LPDDR4__DENALI_PI_208__PI_TFC_F0_SHIFT 0U

3657

#define LPDDR4__DENALI_PI_208__PI_TFC_F0_WIDTH 10U

3658

#define LPDDR4__PI_TFC_F0__REG DENALI_PI_208

3659

#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_208__PI_TFC_F0

3660

3661

#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_MASK 0x003F0000U

3662

#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_SHIFT 16U

3663

#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_WIDTH 6U

3664

#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_208

3665

#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1

3666

3667

#define LPDDR4__DENALI_PI_209_READ_MASK 0x003F03FFU

3668

#define LPDDR4__DENALI_PI_209_WRITE_MASK 0x003F03FFU

3669

#define LPDDR4__DENALI_PI_209__PI_TFC_F1_MASK 0x000003FFU

3670

#define LPDDR4__DENALI_PI_209__PI_TFC_F1_SHIFT 0U

3671

#define LPDDR4__DENALI_PI_209__PI_TFC_F1_WIDTH 10U

3672

#define LPDDR4__PI_TFC_F1__REG DENALI_PI_209

3673

#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_209__PI_TFC_F1

3674

3675

#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_MASK 0x003F0000U

3676

#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_SHIFT 16U

3677

#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_WIDTH 6U

3678

#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_209

3679

#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2

3680

3681

#define LPDDR4__DENALI_PI_210_READ_MASK 0x03FF03FFU

3682

#define LPDDR4__DENALI_PI_210_WRITE_MASK 0x03FF03FFU

3683

#define LPDDR4__DENALI_PI_210__PI_TFC_F2_MASK 0x000003FFU

3684

#define LPDDR4__DENALI_PI_210__PI_TFC_F2_SHIFT 0U

3685

#define LPDDR4__DENALI_PI_210__PI_TFC_F2_WIDTH 10U

3686

#define LPDDR4__PI_TFC_F2__REG DENALI_PI_210

3687

#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_210__PI_TFC_F2

3688

3689

#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_MASK 0x03FF0000U

3690

#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_SHIFT 16U

3691

#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U

3692

#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_210

3693

#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0

3694

3695

#define LPDDR4__DENALI_PI_211_READ_MASK 0x7F7F03FFU

3696

#define LPDDR4__DENALI_PI_211_WRITE_MASK 0x7F7F03FFU

3697

#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU

3698

#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U

3699

#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U

3700

#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_211

3701

#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0

3702

3703

#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U

3704

#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U

3705

#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U

3706

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_211

3707

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0

3708

3709

#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U

3710

#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U

3711

#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U

3712

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_211

3713

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0

3714

3715

#define LPDDR4__DENALI_PI_212_READ_MASK 0x0003030FU

3716

#define LPDDR4__DENALI_PI_212_WRITE_MASK 0x0003030FU

3717

#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU

3718

#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U

3719

#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U

3720

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_212

3721

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0

3722

3723

#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_MASK 0x00000300U

3724

#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_SHIFT 8U

3725

#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_WIDTH 2U

3726

#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_212

3727

#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0

3728

3729

#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U

3730

#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_SHIFT 16U

3731

#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_WIDTH 2U

3732

#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_212

3733

#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0

3734

3735

#define LPDDR4__DENALI_PI_213_READ_MASK 0x03FF03FFU

3736

#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x03FF03FFU

3737

#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_MASK 0x000003FFU

3738

#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_SHIFT 0U

3739

#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U

3740

#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_213

3741

#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1

3742

3743

#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_MASK 0x03FF0000U

3744

#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_SHIFT 16U

3745

#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U

3746

#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_213

3747

#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1

3748

3749

#define LPDDR4__DENALI_PI_214_READ_MASK 0x030F7F7FU

3750

#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x030F7F7FU

3751

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x0000007FU

3752

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 0U

3753

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U

3754

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_214

3755

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1

3756

3757

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x00007F00U

3758

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 8U

3759

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U

3760

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_214

3761

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1

3762

3763

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_MASK 0x000F0000U

3764

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_SHIFT 16U

3765

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U

3766

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_214

3767

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1

3768

3769

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_MASK 0x03000000U

3770

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_SHIFT 24U

3771

#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_WIDTH 2U

3772

#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_214

3773

#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1

3774

3775

#define LPDDR4__DENALI_PI_215_READ_MASK 0x0003FF03U

3776

#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x0003FF03U

3777

#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_MASK 0x00000003U

3778

#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_SHIFT 0U

3779

#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_WIDTH 2U

3780

#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_215

3781

#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1

3782

3783

#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_MASK 0x0003FF00U

3784

#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_SHIFT 8U

3785

#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U

3786

#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_215

3787

#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2

3788

3789

#define LPDDR4__DENALI_PI_216_READ_MASK 0x7F7F03FFU

3790

#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x7F7F03FFU

3791

#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU

3792

#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U

3793

#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U

3794

#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_216

3795

#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2

3796

3797

#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U

3798

#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U

3799

#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U

3800

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_216

3801

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2

3802

3803

#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U

3804

#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U

3805

#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U

3806

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_216

3807

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2

3808

3809

#define LPDDR4__DENALI_PI_217_READ_MASK 0xFF03030FU

3810

#define LPDDR4__DENALI_PI_217_WRITE_MASK 0xFF03030FU

3811

#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU

3812

#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U

3813

#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U

3814

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_217

3815

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2

3816

3817

#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_MASK 0x00000300U

3818

#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_SHIFT 8U

3819

#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_WIDTH 2U

3820

#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_217

3821

#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2

3822

3823

#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U

3824

#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_SHIFT 16U

3825

#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_WIDTH 2U

3826

#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_217

3827

#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2

3828

3829

#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_MASK 0xFF000000U

3830

#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_SHIFT 24U

3831

#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_WIDTH 8U

3832

#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_217

3833

#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_217__PI_TRTP_F0

3834

3835

#define LPDDR4__DENALI_PI_218_READ_MASK 0xFF3FFFFFU

3836

#define LPDDR4__DENALI_PI_218_WRITE_MASK 0xFF3FFFFFU

3837

#define LPDDR4__DENALI_PI_218__PI_TRP_F0_MASK 0x000000FFU

3838

#define LPDDR4__DENALI_PI_218__PI_TRP_F0_SHIFT 0U

3839

#define LPDDR4__DENALI_PI_218__PI_TRP_F0_WIDTH 8U

3840

#define LPDDR4__PI_TRP_F0__REG DENALI_PI_218

3841

#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_218__PI_TRP_F0

3842

3843

#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_MASK 0x0000FF00U

3844

#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_SHIFT 8U

3845

#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_WIDTH 8U

3846

#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_218

3847

#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_218__PI_TRCD_F0

3848

3849

#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_MASK 0x003F0000U

3850

#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_SHIFT 16U

3851

#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_WIDTH 6U

3852

#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_218

3853

#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWTR_F0

3854

3855

#define LPDDR4__DENALI_PI_218__PI_TWR_F0_MASK 0xFF000000U

3856

#define LPDDR4__DENALI_PI_218__PI_TWR_F0_SHIFT 24U

3857

#define LPDDR4__DENALI_PI_218__PI_TWR_F0_WIDTH 8U

3858

#define LPDDR4__PI_TWR_F0__REG DENALI_PI_218

3859

#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWR_F0

3860

3861

#define LPDDR4__DENALI_PI_219_READ_MASK 0xFF01FFFFU

3862

#define LPDDR4__DENALI_PI_219_WRITE_MASK 0xFF01FFFFU

3863

#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_MASK 0x0001FFFFU

3864

#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_SHIFT 0U

3865

#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_WIDTH 17U

3866

#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_219

3867

#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0

3868

3869

#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_MASK 0xFF000000U

3870

#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_SHIFT 24U

3871

#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_WIDTH 8U

3872

#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_219

3873

#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0

3874

3875

#define LPDDR4__DENALI_PI_220_READ_MASK 0xFFFF3F0FU

3876

#define LPDDR4__DENALI_PI_220_WRITE_MASK 0xFFFF3F0FU

3877

#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_MASK 0x0000000FU

3878

#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_SHIFT 0U

3879

#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_WIDTH 4U

3880

#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_220

3881

#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0

3882

3883

#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_MASK 0x00003F00U

3884

#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_SHIFT 8U

3885

#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_WIDTH 6U

3886

#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_220

3887

#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_220__PI_TCCDMW_F0

3888

3889

#define LPDDR4__DENALI_PI_220__PI_TSR_F0_MASK 0x00FF0000U

3890

#define LPDDR4__DENALI_PI_220__PI_TSR_F0_SHIFT 16U

3891

#define LPDDR4__DENALI_PI_220__PI_TSR_F0_WIDTH 8U

3892

#define LPDDR4__PI_TSR_F0__REG DENALI_PI_220

3893

#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_220__PI_TSR_F0

3894

3895

#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_MASK 0xFF000000U

3896

#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_SHIFT 24U

3897

#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_WIDTH 8U

3898

#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_220

3899

#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_220__PI_TMRD_F0

3900

3901

#define LPDDR4__DENALI_PI_221_READ_MASK 0xFFFFFFFFU

3902

#define LPDDR4__DENALI_PI_221_WRITE_MASK 0xFFFFFFFFU

3903

#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_MASK 0x000000FFU

3904

#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_SHIFT 0U

3905

#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_WIDTH 8U

3906

#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_221

3907

#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRW_F0

3908

3909

#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_MASK 0x0000FF00U

3910

#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_SHIFT 8U

3911

#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_WIDTH 8U

3912

#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_221

3913

#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRTP_F1

3914

3915

#define LPDDR4__DENALI_PI_221__PI_TRP_F1_MASK 0x00FF0000U

3916

#define LPDDR4__DENALI_PI_221__PI_TRP_F1_SHIFT 16U

3917

#define LPDDR4__DENALI_PI_221__PI_TRP_F1_WIDTH 8U

3918

#define LPDDR4__PI_TRP_F1__REG DENALI_PI_221

3919

#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRP_F1

3920

3921

#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_MASK 0xFF000000U

3922

#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_SHIFT 24U

3923

#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_WIDTH 8U

3924

#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_221

3925

#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_221__PI_TRCD_F1

3926

3927

#define LPDDR4__DENALI_PI_222_READ_MASK 0x0000FF3FU

3928

#define LPDDR4__DENALI_PI_222_WRITE_MASK 0x0000FF3FU

3929

#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_MASK 0x0000003FU

3930

#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_SHIFT 0U

3931

#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_WIDTH 6U

3932

#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_222

3933

#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWTR_F1

3934

3935

#define LPDDR4__DENALI_PI_222__PI_TWR_F1_MASK 0x0000FF00U

3936

#define LPDDR4__DENALI_PI_222__PI_TWR_F1_SHIFT 8U

3937

#define LPDDR4__DENALI_PI_222__PI_TWR_F1_WIDTH 8U

3938

#define LPDDR4__PI_TWR_F1__REG DENALI_PI_222

3939

#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWR_F1

3940

3941

#define LPDDR4__DENALI_PI_223_READ_MASK 0xFF01FFFFU

3942

#define LPDDR4__DENALI_PI_223_WRITE_MASK 0xFF01FFFFU

3943

#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_MASK 0x0001FFFFU

3944

#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_SHIFT 0U

3945

#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_WIDTH 17U

3946

#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_223

3947

#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1

3948

3949

#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_MASK 0xFF000000U

3950

#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_SHIFT 24U

3951

#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_WIDTH 8U

3952

#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_223

3953

#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1

3954

3955

#define LPDDR4__DENALI_PI_224_READ_MASK 0xFFFF3F0FU

3956

#define LPDDR4__DENALI_PI_224_WRITE_MASK 0xFFFF3F0FU

3957

#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_MASK 0x0000000FU

3958

#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_SHIFT 0U

3959

#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_WIDTH 4U

3960

#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_224

3961

#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1

3962

3963

#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_MASK 0x00003F00U

3964

#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_SHIFT 8U

3965

#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_WIDTH 6U

3966

#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_224

3967

#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_224__PI_TCCDMW_F1

3968

3969

#define LPDDR4__DENALI_PI_224__PI_TSR_F1_MASK 0x00FF0000U

3970

#define LPDDR4__DENALI_PI_224__PI_TSR_F1_SHIFT 16U

3971

#define LPDDR4__DENALI_PI_224__PI_TSR_F1_WIDTH 8U

3972

#define LPDDR4__PI_TSR_F1__REG DENALI_PI_224

3973

#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_224__PI_TSR_F1

3974

3975

#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_MASK 0xFF000000U

3976

#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_SHIFT 24U

3977

#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_WIDTH 8U

3978

#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_224

3979

#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_224__PI_TMRD_F1

3980

3981

#define LPDDR4__DENALI_PI_225_READ_MASK 0xFFFFFFFFU

3982

#define LPDDR4__DENALI_PI_225_WRITE_MASK 0xFFFFFFFFU

3983

#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_MASK 0x000000FFU

3984

#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_SHIFT 0U

3985

#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_WIDTH 8U

3986

#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_225

3987

#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_225__PI_TMRW_F1

3988

3989

#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_MASK 0x0000FF00U

3990

#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_SHIFT 8U

3991

#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_WIDTH 8U

3992

#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_225

3993

#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRTP_F2

3994

3995

#define LPDDR4__DENALI_PI_225__PI_TRP_F2_MASK 0x00FF0000U

3996

#define LPDDR4__DENALI_PI_225__PI_TRP_F2_SHIFT 16U

3997

#define LPDDR4__DENALI_PI_225__PI_TRP_F2_WIDTH 8U

3998

#define LPDDR4__PI_TRP_F2__REG DENALI_PI_225

3999

#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRP_F2

4000

4001

#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_MASK 0xFF000000U

4002

#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_SHIFT 24U

4003

#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_WIDTH 8U

4004

#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_225

4005

#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_225__PI_TRCD_F2

4006

4007

#define LPDDR4__DENALI_PI_226_READ_MASK 0x0000FF3FU

4008

#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x0000FF3FU

4009

#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_MASK 0x0000003FU

4010

#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_SHIFT 0U

4011

#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_WIDTH 6U

4012

#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_226

4013

#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWTR_F2

4014

4015

#define LPDDR4__DENALI_PI_226__PI_TWR_F2_MASK 0x0000FF00U

4016

#define LPDDR4__DENALI_PI_226__PI_TWR_F2_SHIFT 8U

4017

#define LPDDR4__DENALI_PI_226__PI_TWR_F2_WIDTH 8U

4018

#define LPDDR4__PI_TWR_F2__REG DENALI_PI_226

4019

#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWR_F2

4020

4021

#define LPDDR4__DENALI_PI_227_READ_MASK 0xFF01FFFFU

4022

#define LPDDR4__DENALI_PI_227_WRITE_MASK 0xFF01FFFFU

4023

#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_MASK 0x0001FFFFU

4024

#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_SHIFT 0U

4025

#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_WIDTH 17U

4026

#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_227

4027

#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2

4028

4029

#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_MASK 0xFF000000U

4030

#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_SHIFT 24U

4031

#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_WIDTH 8U

4032

#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_227

4033

#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2

4034

4035

#define LPDDR4__DENALI_PI_228_READ_MASK 0xFFFF3F0FU

4036

#define LPDDR4__DENALI_PI_228_WRITE_MASK 0xFFFF3F0FU

4037

#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_MASK 0x0000000FU

4038

#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_SHIFT 0U

4039

#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_WIDTH 4U

4040

#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_228

4041

#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2

4042

4043

#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_MASK 0x00003F00U

4044

#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_SHIFT 8U

4045

#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_WIDTH 6U

4046

#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_228

4047

#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_228__PI_TCCDMW_F2

4048

4049

#define LPDDR4__DENALI_PI_228__PI_TSR_F2_MASK 0x00FF0000U

4050

#define LPDDR4__DENALI_PI_228__PI_TSR_F2_SHIFT 16U

4051

#define LPDDR4__DENALI_PI_228__PI_TSR_F2_WIDTH 8U

4052

#define LPDDR4__PI_TSR_F2__REG DENALI_PI_228

4053

#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_228__PI_TSR_F2

4054

4055

#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_MASK 0xFF000000U

4056

#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_SHIFT 24U

4057

#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_WIDTH 8U

4058

#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_228

4059

#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_228__PI_TMRD_F2

4060

4061

#define LPDDR4__DENALI_PI_229_READ_MASK 0x1FFFFFFFU

4062

#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x1FFFFFFFU

4063

#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_MASK 0x000000FFU

4064

#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_SHIFT 0U

4065

#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_WIDTH 8U

4066

#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_229

4067

#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_229__PI_TMRW_F2

4068

4069

#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x1FFFFF00U

4070

#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 8U

4071

#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U

4072

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_229

4073

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0

4074

4075

#define LPDDR4__DENALI_PI_230_READ_MASK 0xFFFFFFFFU

4076

#define LPDDR4__DENALI_PI_230_WRITE_MASK 0xFFFFFFFFU

4077

#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU

4078

#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U

4079

#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U

4080

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_230

4081

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0

4082

4083

#define LPDDR4__DENALI_PI_231_READ_MASK 0x001FFFFFU

4084

#define LPDDR4__DENALI_PI_231_WRITE_MASK 0x001FFFFFU

4085

#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU

4086

#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U

4087

#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U

4088

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_231

4089

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1

4090

4091

#define LPDDR4__DENALI_PI_232_READ_MASK 0xFFFFFFFFU

4092

#define LPDDR4__DENALI_PI_232_WRITE_MASK 0xFFFFFFFFU

4093

#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU

4094

#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U

4095

#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U

4096

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_232

4097

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1

4098

4099

#define LPDDR4__DENALI_PI_233_READ_MASK 0x001FFFFFU

4100

#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x001FFFFFU

4101

#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU

4102

#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U

4103

#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U

4104

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_233

4105

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2

4106

4107

#define LPDDR4__DENALI_PI_234_READ_MASK 0xFFFFFFFFU

4108

#define LPDDR4__DENALI_PI_234_WRITE_MASK 0xFFFFFFFFU

4109

#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU

4110

#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U

4111

#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U

4112

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_234

4113

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2

4114

4115

#define LPDDR4__DENALI_PI_235_READ_MASK 0xFFFFFFFFU

4116

#define LPDDR4__DENALI_PI_235_WRITE_MASK 0xFFFFFFFFU

4117

#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_MASK 0x0000FFFFU

4118

#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_SHIFT 0U

4119

#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_WIDTH 16U

4120

#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_235

4121

#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F0

4122

4123

#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_MASK 0xFFFF0000U

4124

#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_SHIFT 16U

4125

#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_WIDTH 16U

4126

#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_235

4127

#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F1

4128

4129

#define LPDDR4__DENALI_PI_236_READ_MASK 0x3F3FFFFFU

4130

#define LPDDR4__DENALI_PI_236_WRITE_MASK 0x3F3FFFFFU

4131

#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_MASK 0x0000FFFFU

4132

#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_SHIFT 0U

4133

#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_WIDTH 16U

4134

#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_236

4135

#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_236__PI_TXSR_F2

4136

4137

#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_MASK 0x003F0000U

4138

#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_SHIFT 16U

4139

#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_WIDTH 6U

4140

#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_236

4141

#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F0

4142

4143

#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_MASK 0x3F000000U

4144

#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_SHIFT 24U

4145

#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_WIDTH 6U

4146

#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_236

4147

#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F1

4148

4149

#define LPDDR4__DENALI_PI_237_READ_MASK 0xFFFFFF3FU

4150

#define LPDDR4__DENALI_PI_237_WRITE_MASK 0xFFFFFF3FU

4151

#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_MASK 0x0000003FU

4152

#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_SHIFT 0U

4153

#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_WIDTH 6U

4154

#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_237

4155

#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_237__PI_TEXCKE_F2

4156

4157

#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_MASK 0xFFFFFF00U

4158

#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_SHIFT 8U

4159

#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_WIDTH 24U

4160

#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_237

4161

#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_237__PI_TINIT_F0

4162

4163

#define LPDDR4__DENALI_PI_238_READ_MASK 0x00FFFFFFU

4164

#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x00FFFFFFU

4165

#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_MASK 0x00FFFFFFU

4166

#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_SHIFT 0U

4167

#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_WIDTH 24U

4168

#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_238

4169

#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_238__PI_TINIT3_F0

4170

4171

#define LPDDR4__DENALI_PI_239_READ_MASK 0x00FFFFFFU

4172

#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x00FFFFFFU

4173

#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_MASK 0x00FFFFFFU

4174

#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_SHIFT 0U

4175

#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_WIDTH 24U

4176

#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_239

4177

#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_239__PI_TINIT4_F0

4178

4179

#define LPDDR4__DENALI_PI_240_READ_MASK 0x00FFFFFFU

4180

#define LPDDR4__DENALI_PI_240_WRITE_MASK 0x00FFFFFFU

4181

#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_MASK 0x00FFFFFFU

4182

#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_SHIFT 0U

4183

#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_WIDTH 24U

4184

#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_240

4185

#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_240__PI_TINIT5_F0

4186

4187

#define LPDDR4__DENALI_PI_241_READ_MASK 0x0000FFFFU

4188

#define LPDDR4__DENALI_PI_241_WRITE_MASK 0x0000FFFFU

4189

#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_MASK 0x0000FFFFU

4190

#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_SHIFT 0U

4191

#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_WIDTH 16U

4192

#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_241

4193

#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_241__PI_TXSNR_F0

4194

4195

#define LPDDR4__DENALI_PI_242_READ_MASK 0x00FFFFFFU

4196

#define LPDDR4__DENALI_PI_242_WRITE_MASK 0x00FFFFFFU

4197

#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_MASK 0x00FFFFFFU

4198

#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_SHIFT 0U

4199

#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_WIDTH 24U

4200

#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_242

4201

#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_242__PI_TINIT_F1

4202

4203

#define LPDDR4__DENALI_PI_243_READ_MASK 0x00FFFFFFU

4204

#define LPDDR4__DENALI_PI_243_WRITE_MASK 0x00FFFFFFU

4205

#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_MASK 0x00FFFFFFU

4206

#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_SHIFT 0U

4207

#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_WIDTH 24U

4208

#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_243

4209

#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_243__PI_TINIT3_F1

4210

4211

#define LPDDR4__DENALI_PI_244_READ_MASK 0x00FFFFFFU

4212

#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x00FFFFFFU

4213

#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_MASK 0x00FFFFFFU

4214

#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_SHIFT 0U

4215

#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_WIDTH 24U

4216

#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_244

4217

#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_244__PI_TINIT4_F1

4218

4219

#define LPDDR4__DENALI_PI_245_READ_MASK 0x00FFFFFFU

4220

#define LPDDR4__DENALI_PI_245_WRITE_MASK 0x00FFFFFFU

4221

#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_MASK 0x00FFFFFFU

4222

#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_SHIFT 0U

4223

#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_WIDTH 24U

4224

#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_245

4225

#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_245__PI_TINIT5_F1

4226

4227

#define LPDDR4__DENALI_PI_246_READ_MASK 0x0000FFFFU

4228

#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x0000FFFFU

4229

#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_MASK 0x0000FFFFU

4230

#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_SHIFT 0U

4231

#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_WIDTH 16U

4232

#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_246

4233

#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_246__PI_TXSNR_F1

4234

4235

#define LPDDR4__DENALI_PI_247_READ_MASK 0x00FFFFFFU

4236

#define LPDDR4__DENALI_PI_247_WRITE_MASK 0x00FFFFFFU

4237

#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_MASK 0x00FFFFFFU

4238

#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_SHIFT 0U

4239

#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_WIDTH 24U

4240

#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_247

4241

#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_247__PI_TINIT_F2

4242

4243

#define LPDDR4__DENALI_PI_248_READ_MASK 0x00FFFFFFU

4244

#define LPDDR4__DENALI_PI_248_WRITE_MASK 0x00FFFFFFU

4245

#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_MASK 0x00FFFFFFU

4246

#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_SHIFT 0U

4247

#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_WIDTH 24U

4248

#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_248

4249

#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_248__PI_TINIT3_F2

4250

4251

#define LPDDR4__DENALI_PI_249_READ_MASK 0x00FFFFFFU

4252

#define LPDDR4__DENALI_PI_249_WRITE_MASK 0x00FFFFFFU

4253

#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_MASK 0x00FFFFFFU

4254

#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_SHIFT 0U

4255

#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_WIDTH 24U

4256

#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_249

4257

#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_249__PI_TINIT4_F2

4258

4259

#define LPDDR4__DENALI_PI_250_READ_MASK 0x00FFFFFFU

4260

#define LPDDR4__DENALI_PI_250_WRITE_MASK 0x00FFFFFFU

4261

#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_MASK 0x00FFFFFFU

4262

#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_SHIFT 0U

4263

#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_WIDTH 24U

4264

#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_250

4265

#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_250__PI_TINIT5_F2

4266

4267

#define LPDDR4__DENALI_PI_251_READ_MASK 0x0FFFFFFFU

4268

#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x0FFFFFFFU

4269

#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_MASK 0x0000FFFFU

4270

#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_SHIFT 0U

4271

#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_WIDTH 16U

4272

#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_251

4273

#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_251__PI_TXSNR_F2

4274

4275

#define LPDDR4__DENALI_PI_251__PI_RESERVED49_MASK 0x0FFF0000U

4276

#define LPDDR4__DENALI_PI_251__PI_RESERVED49_SHIFT 16U

4277

#define LPDDR4__DENALI_PI_251__PI_RESERVED49_WIDTH 12U

4278

#define LPDDR4__PI_RESERVED49__REG DENALI_PI_251

4279

#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_251__PI_RESERVED49

4280

4281

#define LPDDR4__DENALI_PI_252_READ_MASK 0x0FFF0FFFU

4282

#define LPDDR4__DENALI_PI_252_WRITE_MASK 0x0FFF0FFFU

4283

#define LPDDR4__DENALI_PI_252__PI_RESERVED50_MASK 0x00000FFFU

4284

#define LPDDR4__DENALI_PI_252__PI_RESERVED50_SHIFT 0U

4285

#define LPDDR4__DENALI_PI_252__PI_RESERVED50_WIDTH 12U

4286

#define LPDDR4__PI_RESERVED50__REG DENALI_PI_252

4287

#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_252__PI_RESERVED50

4288

4289

#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_MASK 0x0FFF0000U

4290

#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_SHIFT 16U

4291

#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_WIDTH 12U

4292

#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_252

4293

#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_252__PI_TZQCAL_F0

4294

4295

#define LPDDR4__DENALI_PI_253_READ_MASK 0x000FFF7FU

4296

#define LPDDR4__DENALI_PI_253_WRITE_MASK 0x000FFF7FU

4297

#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_MASK 0x0000007FU

4298

#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_SHIFT 0U

4299

#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_WIDTH 7U

4300

#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_253

4301

#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_253__PI_TZQLAT_F0

4302

4303

#define LPDDR4__DENALI_PI_253__PI_RESERVED51_MASK 0x000FFF00U

4304

#define LPDDR4__DENALI_PI_253__PI_RESERVED51_SHIFT 8U

4305

#define LPDDR4__DENALI_PI_253__PI_RESERVED51_WIDTH 12U

4306

#define LPDDR4__PI_RESERVED51__REG DENALI_PI_253

4307

#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_253__PI_RESERVED51

4308

4309

#define LPDDR4__DENALI_PI_254_READ_MASK 0x0FFF0FFFU

4310

#define LPDDR4__DENALI_PI_254_WRITE_MASK 0x0FFF0FFFU

4311

#define LPDDR4__DENALI_PI_254__PI_RESERVED52_MASK 0x00000FFFU

4312

#define LPDDR4__DENALI_PI_254__PI_RESERVED52_SHIFT 0U

4313

#define LPDDR4__DENALI_PI_254__PI_RESERVED52_WIDTH 12U

4314

#define LPDDR4__PI_RESERVED52__REG DENALI_PI_254

4315

#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_254__PI_RESERVED52

4316

4317

#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_MASK 0x0FFF0000U

4318

#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_SHIFT 16U

4319

#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_WIDTH 12U

4320

#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_254

4321

#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_254__PI_TZQCAL_F1

4322

4323

#define LPDDR4__DENALI_PI_255_READ_MASK 0x000FFF7FU

4324

#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x000FFF7FU

4325

#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_MASK 0x0000007FU

4326

#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_SHIFT 0U

4327

#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_WIDTH 7U

4328

#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_255

4329

#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_255__PI_TZQLAT_F1

4330

4331

#define LPDDR4__DENALI_PI_255__PI_RESERVED53_MASK 0x000FFF00U

4332

#define LPDDR4__DENALI_PI_255__PI_RESERVED53_SHIFT 8U

4333

#define LPDDR4__DENALI_PI_255__PI_RESERVED53_WIDTH 12U

4334

#define LPDDR4__PI_RESERVED53__REG DENALI_PI_255

4335

#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_255__PI_RESERVED53

4336

4337

#define LPDDR4__DENALI_PI_256_READ_MASK 0x0FFF0FFFU

4338

#define LPDDR4__DENALI_PI_256_WRITE_MASK 0x0FFF0FFFU

4339

#define LPDDR4__DENALI_PI_256__PI_RESERVED54_MASK 0x00000FFFU

4340

#define LPDDR4__DENALI_PI_256__PI_RESERVED54_SHIFT 0U

4341

#define LPDDR4__DENALI_PI_256__PI_RESERVED54_WIDTH 12U

4342

#define LPDDR4__PI_RESERVED54__REG DENALI_PI_256

4343

#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_256__PI_RESERVED54

4344

4345

#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_MASK 0x0FFF0000U

4346

#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_SHIFT 16U

4347

#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_WIDTH 12U

4348

#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_256

4349

#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_256__PI_TZQCAL_F2

4350

4351

#define LPDDR4__DENALI_PI_257_READ_MASK 0x000FFF7FU

4352

#define LPDDR4__DENALI_PI_257_WRITE_MASK 0x000FFF7FU

4353

#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_MASK 0x0000007FU

4354

#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_SHIFT 0U

4355

#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_WIDTH 7U

4356

#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_257

4357

#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_257__PI_TZQLAT_F2

4358

4359

#define LPDDR4__DENALI_PI_257__PI_RESERVED55_MASK 0x000FFF00U

4360

#define LPDDR4__DENALI_PI_257__PI_RESERVED55_SHIFT 8U

4361

#define LPDDR4__DENALI_PI_257__PI_RESERVED55_WIDTH 12U

4362

#define LPDDR4__PI_RESERVED55__REG DENALI_PI_257

4363

#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_257__PI_RESERVED55

4364

4365

#define LPDDR4__DENALI_PI_258_READ_MASK 0x0FFF0FFFU

4366

#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0FFF0FFFU

4367

#define LPDDR4__DENALI_PI_258__PI_RESERVED56_MASK 0x00000FFFU

4368

#define LPDDR4__DENALI_PI_258__PI_RESERVED56_SHIFT 0U

4369

#define LPDDR4__DENALI_PI_258__PI_RESERVED56_WIDTH 12U

4370

#define LPDDR4__PI_RESERVED56__REG DENALI_PI_258

4371

#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_258__PI_RESERVED56

4372

4373

#define LPDDR4__DENALI_PI_258__PI_RESERVED57_MASK 0x0FFF0000U

4374

#define LPDDR4__DENALI_PI_258__PI_RESERVED57_SHIFT 16U

4375

#define LPDDR4__DENALI_PI_258__PI_RESERVED57_WIDTH 12U

4376

#define LPDDR4__PI_RESERVED57__REG DENALI_PI_258

4377

#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_258__PI_RESERVED57

4378

4379

#define LPDDR4__DENALI_PI_259_READ_MASK 0xFF0F0F0FU

4380

#define LPDDR4__DENALI_PI_259_WRITE_MASK 0xFF0F0F0FU

4381

#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU

4382

#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U

4383

#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U

4384

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_259

4385

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0

4386

4387

#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U

4388

#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U

4389

#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U

4390

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_259

4391

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1

4392

4393

#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U

4394

#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U

4395

#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U

4396

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_259

4397

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2

4398

4399

#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_MASK 0xFF000000U

4400

#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_SHIFT 24U

4401

#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_WIDTH 8U

4402

#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_259

4403

#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_259__PI_MR13_DATA_0

4404

4405

#define LPDDR4__DENALI_PI_260_READ_MASK 0xFFFFFFFFU

4406

#define LPDDR4__DENALI_PI_260_WRITE_MASK 0xFFFFFFFFU

4407

#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_MASK 0x000000FFU

4408

#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_SHIFT 0U

4409

#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_WIDTH 8U

4410

#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_260

4411

#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR15_DATA_0

4412

4413

#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_MASK 0x0000FF00U

4414

#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_SHIFT 8U

4415

#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_WIDTH 8U

4416

#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_260

4417

#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR16_DATA_0

4418

4419

#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_MASK 0x00FF0000U

4420

#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_SHIFT 16U

4421

#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_WIDTH 8U

4422

#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_260

4423

#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR17_DATA_0

4424

4425

#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_MASK 0xFF000000U

4426

#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_SHIFT 24U

4427

#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_WIDTH 8U

4428

#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_260

4429

#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR20_DATA_0

4430

4431

#define LPDDR4__DENALI_PI_261_READ_MASK 0xFFFFFFFFU

4432

#define LPDDR4__DENALI_PI_261_WRITE_MASK 0xFFFFFFFFU

4433

#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_MASK 0x000000FFU

4434

#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_SHIFT 0U

4435

#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_WIDTH 8U

4436

#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_261

4437

#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR32_DATA_0

4438

4439

#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_MASK 0x0000FF00U

4440

#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_SHIFT 8U

4441

#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_WIDTH 8U

4442

#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_261

4443

#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR40_DATA_0

4444

4445

#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_MASK 0x00FF0000U

4446

#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_SHIFT 16U

4447

#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_WIDTH 8U

4448

#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_261

4449

#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR13_DATA_1

4450

4451

#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_MASK 0xFF000000U

4452

#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_SHIFT 24U

4453

#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_WIDTH 8U

4454

#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_261

4455

#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR15_DATA_1

4456

4457

#define LPDDR4__DENALI_PI_262_READ_MASK 0xFFFFFFFFU

4458

#define LPDDR4__DENALI_PI_262_WRITE_MASK 0xFFFFFFFFU

4459

#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_MASK 0x000000FFU

4460

#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_SHIFT 0U

4461

#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_WIDTH 8U

4462

#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_262

4463

#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR16_DATA_1

4464

4465

#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_MASK 0x0000FF00U

4466

#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_SHIFT 8U

4467

#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_WIDTH 8U

4468

#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_262

4469

#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR17_DATA_1

4470

4471

#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_MASK 0x00FF0000U

4472

#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_SHIFT 16U

4473

#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_WIDTH 8U

4474

#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_262

4475

#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR20_DATA_1

4476

4477

#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_MASK 0xFF000000U

4478

#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_SHIFT 24U

4479

#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_WIDTH 8U

4480

#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_262

4481

#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR32_DATA_1

4482

4483

#define LPDDR4__DENALI_PI_263_READ_MASK 0xFFFFFFFFU

4484

#define LPDDR4__DENALI_PI_263_WRITE_MASK 0xFFFFFFFFU

4485

#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_MASK 0x000000FFU

4486

#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_SHIFT 0U

4487

#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_WIDTH 8U

4488

#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_263

4489

#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_263__PI_MR40_DATA_1

4490

4491

#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_MASK 0x0000FF00U

4492

#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_SHIFT 8U

4493

#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_WIDTH 8U

4494

#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_263

4495

#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR13_DATA_2

4496

4497

#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_MASK 0x00FF0000U

4498

#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_SHIFT 16U

4499

#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_WIDTH 8U

4500

#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_263

4501

#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR15_DATA_2

4502

4503

#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_MASK 0xFF000000U

4504

#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_SHIFT 24U

4505

#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_WIDTH 8U

4506

#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_263

4507

#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR16_DATA_2

4508

4509

#define LPDDR4__DENALI_PI_264_READ_MASK 0xFFFFFFFFU

4510

#define LPDDR4__DENALI_PI_264_WRITE_MASK 0xFFFFFFFFU

4511

#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_MASK 0x000000FFU

4512

#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_SHIFT 0U

4513

#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_WIDTH 8U

4514

#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_264

4515

#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR17_DATA_2

4516

4517

#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_MASK 0x0000FF00U

4518

#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_SHIFT 8U

4519

#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_WIDTH 8U

4520

#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_264

4521

#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR20_DATA_2

4522

4523

#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_MASK 0x00FF0000U

4524

#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_SHIFT 16U

4525

#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_WIDTH 8U

4526

#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_264

4527

#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR32_DATA_2

4528

4529

#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_MASK 0xFF000000U

4530

#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_SHIFT 24U

4531

#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_WIDTH 8U

4532

#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_264

4533

#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR40_DATA_2

4534

4535

#define LPDDR4__DENALI_PI_265_READ_MASK 0xFFFFFFFFU

4536

#define LPDDR4__DENALI_PI_265_WRITE_MASK 0xFFFFFFFFU

4537

#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_MASK 0x000000FFU

4538

#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_SHIFT 0U

4539

#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_WIDTH 8U

4540

#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_265

4541

#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR13_DATA_3

4542

4543

#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_MASK 0x0000FF00U

4544

#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_SHIFT 8U

4545

#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_WIDTH 8U

4546

#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_265

4547

#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR15_DATA_3

4548

4549

#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_MASK 0x00FF0000U

4550

#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_SHIFT 16U

4551

#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_WIDTH 8U

4552

#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_265

4553

#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR16_DATA_3

4554

4555

#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_MASK 0xFF000000U

4556

#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_SHIFT 24U

4557

#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_WIDTH 8U

4558

#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_265

4559

#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR17_DATA_3

4560

4561

#define LPDDR4__DENALI_PI_266_READ_MASK 0x0FFFFFFFU

4562

#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x0FFFFFFFU

4563

#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_MASK 0x000000FFU

4564

#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_SHIFT 0U

4565

#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_WIDTH 8U

4566

#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_266

4567

#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR20_DATA_3

4568

4569

#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_MASK 0x0000FF00U

4570

#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_SHIFT 8U

4571

#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_WIDTH 8U

4572

#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_266

4573

#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR32_DATA_3

4574

4575

#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_MASK 0x00FF0000U

4576

#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_SHIFT 16U

4577

#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_WIDTH 8U

4578

#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_266

4579

#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR40_DATA_3

4580

4581

#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_MASK 0x0F000000U

4582

#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_SHIFT 24U

4583

#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_WIDTH 4U

4584

#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_266

4585

#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_266__PI_CKE_MUX_0

4586

4587

#define LPDDR4__DENALI_PI_267_READ_MASK 0x0F0F0F0FU

4588

#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x0F0F0F0FU

4589

#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_MASK 0x0000000FU

4590

#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_SHIFT 0U

4591

#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_WIDTH 4U

4592

#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_267

4593

#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_1

4594

4595

#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_MASK 0x00000F00U

4596

#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_SHIFT 8U

4597

#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_WIDTH 4U

4598

#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_267

4599

#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_2

4600

4601

#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_MASK 0x000F0000U

4602

#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_SHIFT 16U

4603

#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_WIDTH 4U

4604

#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_267

4605

#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_3

4606

4607

#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_MASK 0x0F000000U

4608

#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_SHIFT 24U

4609

#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_WIDTH 4U

4610

#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_267

4611

#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_267__PI_CS_MUX_0

4612

4613

#define LPDDR4__DENALI_PI_268_READ_MASK 0x0F0F0F0FU

4614

#define LPDDR4__DENALI_PI_268_WRITE_MASK 0x0F0F0F0FU

4615

#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_MASK 0x0000000FU

4616

#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_SHIFT 0U

4617

#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_WIDTH 4U

4618

#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_268

4619

#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_1

4620

4621

#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_MASK 0x00000F00U

4622

#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_SHIFT 8U

4623

#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_WIDTH 4U

4624

#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_268

4625

#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_2

4626

4627

#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_MASK 0x000F0000U

4628

#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_SHIFT 16U

4629

#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_WIDTH 4U

4630

#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_268

4631

#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_3

4632

4633

#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_MASK 0x0F000000U

4634

#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_SHIFT 24U

4635

#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_WIDTH 4U

4636

#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_268

4637

#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0

4638

4639

#define LPDDR4__DENALI_PI_269_READ_MASK 0xFF0F0F0FU

4640

#define LPDDR4__DENALI_PI_269_WRITE_MASK 0xFF0F0F0FU

4641

#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_MASK 0x0000000FU

4642

#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_SHIFT 0U

4643

#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_WIDTH 4U

4644

#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_269

4645

#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1

4646

4647

#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_MASK 0x00000F00U

4648

#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_SHIFT 8U

4649

#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_WIDTH 4U

4650

#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_269

4651

#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2

4652

4653

#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_MASK 0x000F0000U

4654

#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_SHIFT 16U

4655

#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_WIDTH 4U

4656

#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_269

4657

#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3

4658

4659

#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_MASK 0xFF000000U

4660

#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_SHIFT 24U

4661

#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_WIDTH 8U

4662

#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_269

4663

#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0

4664

4665

#define LPDDR4__DENALI_PI_270_READ_MASK 0x0FFFFFFFU

4666

#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x0FFFFFFFU

4667

#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_MASK 0x000000FFU

4668

#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_SHIFT 0U

4669

#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_WIDTH 8U

4670

#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_270

4671

#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1

4672

4673

#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_MASK 0x0000FF00U

4674

#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_SHIFT 8U

4675

#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_WIDTH 8U

4676

#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_270

4677

#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2

4678

4679

#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_MASK 0x00FF0000U

4680

#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_SHIFT 16U

4681

#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_WIDTH 8U

4682

#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_270

4683

#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3

4684

4685

#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_MASK 0x0F000000U

4686

#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_SHIFT 24U

4687

#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_WIDTH 4U

4688

#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_270

4689

#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0

4690

4691

#define LPDDR4__DENALI_PI_271_READ_MASK 0x0F0F0F0FU

4692

#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x0F0F0F0FU

4693

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x0000000FU

4694

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U

4695

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 4U

4696

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_271

4697

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0

4698

4699

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_MASK 0x00000F00U

4700

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_SHIFT 8U

4701

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_WIDTH 4U

4702

#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_271

4703

#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1

4704

4705

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x000F0000U

4706

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U

4707

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 4U

4708

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_271

4709

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1

4710

4711

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_MASK 0x0F000000U

4712

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_SHIFT 24U

4713

#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_WIDTH 4U

4714

#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_271

4715

#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2

4716

4717

#define LPDDR4__DENALI_PI_272_READ_MASK 0x000F0F0FU

4718

#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x000F0F0FU

4719

#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_MASK 0x0000000FU

4720

#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_SHIFT 0U

4721

#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_WIDTH 4U

4722

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_272

4723

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2

4724

4725

#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_MASK 0x00000F00U

4726

#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_SHIFT 8U

4727

#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_WIDTH 4U

4728

#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_272

4729

#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3

4730

4731

#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_MASK 0x000F0000U

4732

#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_SHIFT 16U

4733

#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_WIDTH 4U

4734

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_272

4735

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3

4736

4737

#define LPDDR4__DENALI_PI_273_READ_MASK 0xFFFFFFFFU

4738

#define LPDDR4__DENALI_PI_273_WRITE_MASK 0xFFFFFFFFU

4739

#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU

4740

#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U

4741

#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U

4742

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_273

4743

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0

4744

4745

#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_MASK 0xFFFF0000U

4746

#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT 16U

4747

#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH 16U

4748

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_273

4749

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0

4750

4751

#define LPDDR4__DENALI_PI_274_READ_MASK 0xFFFFFFFFU

4752

#define LPDDR4__DENALI_PI_274_WRITE_MASK 0xFFFFFFFFU

4753

#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0x0000FFFFU

4754

#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 0U

4755

#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U

4756

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_274

4757

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1

4758

4759

#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_MASK 0xFFFF0000U

4760

#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT 16U

4761

#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH 16U

4762

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_274

4763

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1

4764

4765

#define LPDDR4__DENALI_PI_275_READ_MASK 0xFFFFFFFFU

4766

#define LPDDR4__DENALI_PI_275_WRITE_MASK 0xFFFFFFFFU

4767

#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_MASK 0x000000FFU

4768

#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_SHIFT 0U

4769

#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_WIDTH 8U

4770

#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_275

4771

#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0

4772

4773

#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_MASK 0x0000FF00U

4774

#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_SHIFT 8U

4775

#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_WIDTH 8U

4776

#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_275

4777

#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0

4778

4779

#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_MASK 0x00FF0000U

4780

#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_SHIFT 16U

4781

#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_WIDTH 8U

4782

#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_275

4783

#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0

4784

4785

#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_MASK 0xFF000000U

4786

#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_SHIFT 24U

4787

#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_WIDTH 8U

4788

#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_275

4789

#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0

4790

4791

#define LPDDR4__DENALI_PI_276_READ_MASK 0xFFFFFFFFU

4792

#define LPDDR4__DENALI_PI_276_WRITE_MASK 0xFFFFFFFFU

4793

#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_MASK 0x000000FFU

4794

#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_SHIFT 0U

4795

#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_WIDTH 8U

4796

#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_276

4797

#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0

4798

4799

#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_MASK 0x0000FF00U

4800

#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_SHIFT 8U

4801

#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_WIDTH 8U

4802

#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_276

4803

#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0

4804

4805

#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_MASK 0x00FF0000U

4806

#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_SHIFT 16U

4807

#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_WIDTH 8U

4808

#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_276

4809

#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0

4810

4811

#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_MASK 0xFF000000U

4812

#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_SHIFT 24U

4813

#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_WIDTH 8U

4814

#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_276

4815

#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0

4816

4817

#define LPDDR4__DENALI_PI_277_READ_MASK 0xFFFFFFFFU

4818

#define LPDDR4__DENALI_PI_277_WRITE_MASK 0xFFFFFFFFU

4819

#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_MASK 0x000000FFU

4820

#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_SHIFT 0U

4821

#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_WIDTH 8U

4822

#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_277

4823

#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0

4824

4825

#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_MASK 0x0000FF00U

4826

#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_SHIFT 8U

4827

#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_WIDTH 8U

4828

#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_277

4829

#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0

4830

4831

#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_MASK 0x00FF0000U

4832

#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_SHIFT 16U

4833

#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_WIDTH 8U

4834

#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_277

4835

#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0

4836

4837

#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_MASK 0xFF000000U

4838

#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_SHIFT 24U

4839

#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_WIDTH 8U

4840

#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_277

4841

#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0

4842

4843

#define LPDDR4__DENALI_PI_278_READ_MASK 0xFFFFFFFFU

4844

#define LPDDR4__DENALI_PI_278_WRITE_MASK 0xFFFFFFFFU

4845

#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_MASK 0x000000FFU

4846

#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_SHIFT 0U

4847

#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_WIDTH 8U

4848

#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_278

4849

#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0

4850

4851

#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_MASK 0x0000FF00U

4852

#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_SHIFT 8U

4853

#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_WIDTH 8U

4854

#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_278

4855

#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0

4856

4857

#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_MASK 0x00FF0000U

4858

#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_SHIFT 16U

4859

#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_WIDTH 8U

4860

#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_278

4861

#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0

4862

4863

#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_MASK 0xFF000000U

4864

#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_SHIFT 24U

4865

#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_WIDTH 8U

4866

#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_278

4867

#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0

4868

4869

#define LPDDR4__DENALI_PI_279_READ_MASK 0xFFFFFFFFU

4870

#define LPDDR4__DENALI_PI_279_WRITE_MASK 0xFFFFFFFFU

4871

#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_MASK 0x000000FFU

4872

#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_SHIFT 0U

4873

#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_WIDTH 8U

4874

#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_279

4875

#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0

4876

4877

#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_MASK 0x0000FF00U

4878

#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_SHIFT 8U

4879

#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_WIDTH 8U

4880

#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_279

4881

#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0

4882

4883

#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_MASK 0x00FF0000U

4884

#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_SHIFT 16U

4885

#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_WIDTH 8U

4886

#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_279

4887

#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0

4888

4889

#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_MASK 0xFF000000U

4890

#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_SHIFT 24U

4891

#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_WIDTH 8U

4892

#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_279

4893

#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0

4894

4895

#define LPDDR4__DENALI_PI_280_READ_MASK 0xFFFFFFFFU

4896

#define LPDDR4__DENALI_PI_280_WRITE_MASK 0xFFFFFFFFU

4897

#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_MASK 0x000000FFU

4898

#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_SHIFT 0U

4899

#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_WIDTH 8U

4900

#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_280

4901

#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0

4902

4903

#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_MASK 0x0000FF00U

4904

#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_SHIFT 8U

4905

#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_WIDTH 8U

4906

#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_280

4907

#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0

4908

4909

#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_MASK 0x00FF0000U

4910

#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_SHIFT 16U

4911

#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_WIDTH 8U

4912

#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_280

4913

#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0

4914

4915

#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_MASK 0xFF000000U

4916

#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_SHIFT 24U

4917

#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_WIDTH 8U

4918

#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_280

4919

#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0

4920

4921

#define LPDDR4__DENALI_PI_281_READ_MASK 0xFFFFFFFFU

4922

#define LPDDR4__DENALI_PI_281_WRITE_MASK 0xFFFFFFFFU

4923

#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_MASK 0x000000FFU

4924

#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_SHIFT 0U

4925

#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_WIDTH 8U

4926

#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_281

4927

#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1

4928

4929

#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_MASK 0x0000FF00U

4930

#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_SHIFT 8U

4931

#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_WIDTH 8U

4932

#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_281

4933

#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1

4934

4935

#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_MASK 0x00FF0000U

4936

#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_SHIFT 16U

4937

#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_WIDTH 8U

4938

#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_281

4939

#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1

4940

4941

#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_MASK 0xFF000000U

4942

#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_SHIFT 24U

4943

#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_WIDTH 8U

4944

#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_281

4945

#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1

4946

4947

#define LPDDR4__DENALI_PI_282_READ_MASK 0xFFFFFFFFU

4948

#define LPDDR4__DENALI_PI_282_WRITE_MASK 0xFFFFFFFFU

4949

#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_MASK 0x000000FFU

4950

#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_SHIFT 0U

4951

#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_WIDTH 8U

4952

#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_282

4953

#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1

4954

4955

#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_MASK 0x0000FF00U

4956

#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_SHIFT 8U

4957

#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_WIDTH 8U

4958

#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_282

4959

#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1

4960

4961

#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_MASK 0x00FF0000U

4962

#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_SHIFT 16U

4963

#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_WIDTH 8U

4964

#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_282

4965

#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1

4966

4967

#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_MASK 0xFF000000U

4968

#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_SHIFT 24U

4969

#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_WIDTH 8U

4970

#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_282

4971

#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1

4972

4973

#define LPDDR4__DENALI_PI_283_READ_MASK 0xFFFFFFFFU

4974

#define LPDDR4__DENALI_PI_283_WRITE_MASK 0xFFFFFFFFU

4975

#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_MASK 0x000000FFU

4976

#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_SHIFT 0U

4977

#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_WIDTH 8U

4978

#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_283

4979

#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1

4980

4981

#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_MASK 0x0000FF00U

4982

#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_SHIFT 8U

4983

#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_WIDTH 8U

4984

#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_283

4985

#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1

4986

4987

#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_MASK 0x00FF0000U

4988

#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_SHIFT 16U

4989

#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_WIDTH 8U

4990

#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_283

4991

#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1

4992

4993

#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_MASK 0xFF000000U

4994

#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_SHIFT 24U

4995

#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_WIDTH 8U

4996

#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_283

4997

#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1

4998

4999

#define LPDDR4__DENALI_PI_284_READ_MASK 0xFFFFFFFFU

5000

#define LPDDR4__DENALI_PI_284_WRITE_MASK 0xFFFFFFFFU

5001

#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_MASK 0x000000FFU

5002

#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_SHIFT 0U

5003

#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_WIDTH 8U

5004

#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_284

5005

#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1

5006

5007

#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_MASK 0x0000FF00U

5008

#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_SHIFT 8U

5009

#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_WIDTH 8U

5010

#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_284

5011

#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1

5012

5013

#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_MASK 0x00FF0000U

5014

#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_SHIFT 16U

5015

#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_WIDTH 8U

5016

#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_284

5017

#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1

5018

5019

#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_MASK 0xFF000000U

5020

#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_SHIFT 24U

5021

#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_WIDTH 8U

5022

#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_284

5023

#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1

5024

5025

#define LPDDR4__DENALI_PI_285_READ_MASK 0xFFFFFFFFU

5026

#define LPDDR4__DENALI_PI_285_WRITE_MASK 0xFFFFFFFFU

5027

#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_MASK 0x000000FFU

5028

#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_SHIFT 0U

5029

#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_WIDTH 8U

5030

#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_285

5031

#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1

5032

5033

#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_MASK 0x0000FF00U

5034

#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_SHIFT 8U

5035

#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_WIDTH 8U

5036

#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_285

5037

#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1

5038

5039

#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_MASK 0x00FF0000U

5040

#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_SHIFT 16U

5041

#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_WIDTH 8U

5042

#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_285

5043

#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1

5044

5045

#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_MASK 0xFF000000U

5046

#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_SHIFT 24U

5047

#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_WIDTH 8U

5048

#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_285

5049

#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1

5050

5051

#define LPDDR4__DENALI_PI_286_READ_MASK 0xFFFFFFFFU

5052

#define LPDDR4__DENALI_PI_286_WRITE_MASK 0xFFFFFFFFU

5053

#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_MASK 0x000000FFU

5054

#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_SHIFT 0U

5055

#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_WIDTH 8U

5056

#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_286

5057

#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1

5058

5059

#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_MASK 0x0000FF00U

5060

#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_SHIFT 8U

5061

#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_WIDTH 8U

5062

#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_286

5063

#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1

5064

5065

#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_MASK 0x00FF0000U

5066

#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_SHIFT 16U

5067

#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_WIDTH 8U

5068

#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_286

5069

#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1

5070

5071

#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_MASK 0xFF000000U

5072

#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_SHIFT 24U

5073

#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_WIDTH 8U

5074

#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_286

5075

#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1

5076

5077

#define LPDDR4__DENALI_PI_287_READ_MASK 0xFFFFFFFFU

5078

#define LPDDR4__DENALI_PI_287_WRITE_MASK 0xFFFFFFFFU

5079

#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_MASK 0x000000FFU

5080

#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_SHIFT 0U

5081

#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_WIDTH 8U

5082

#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_287

5083

#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2

5084

5085

#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_MASK 0x0000FF00U

5086

#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_SHIFT 8U

5087

#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_WIDTH 8U

5088

#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_287

5089

#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2

5090

5091

#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_MASK 0x00FF0000U

5092

#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_SHIFT 16U

5093

#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_WIDTH 8U

5094

#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_287

5095

#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2

5096

5097

#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_MASK 0xFF000000U

5098

#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_SHIFT 24U

5099

#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_WIDTH 8U

5100

#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_287

5101

#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2

5102

5103

#define LPDDR4__DENALI_PI_288_READ_MASK 0xFFFFFFFFU

5104

#define LPDDR4__DENALI_PI_288_WRITE_MASK 0xFFFFFFFFU

5105

#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_MASK 0x000000FFU

5106

#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_SHIFT 0U

5107

#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_WIDTH 8U

5108

#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_288

5109

#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2

5110

5111

#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_MASK 0x0000FF00U

5112

#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_SHIFT 8U

5113

#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_WIDTH 8U

5114

#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_288

5115

#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2

5116

5117

#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_MASK 0x00FF0000U

5118

#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_SHIFT 16U

5119

#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_WIDTH 8U

5120

#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_288

5121

#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2

5122

5123

#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_MASK 0xFF000000U

5124

#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_SHIFT 24U

5125

#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_WIDTH 8U

5126

#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_288

5127

#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2

5128

5129

#define LPDDR4__DENALI_PI_289_READ_MASK 0xFFFFFFFFU

5130

#define LPDDR4__DENALI_PI_289_WRITE_MASK 0xFFFFFFFFU

5131

#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_MASK 0x000000FFU

5132

#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_SHIFT 0U

5133

#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_WIDTH 8U

5134

#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_289

5135

#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2

5136

5137

#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_MASK 0x0000FF00U

5138

#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_SHIFT 8U

5139

#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_WIDTH 8U

5140

#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_289

5141

#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2

5142

5143

#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_MASK 0x00FF0000U

5144

#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_SHIFT 16U

5145

#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_WIDTH 8U

5146

#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_289

5147

#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2

5148

5149

#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_MASK 0xFF000000U

5150

#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_SHIFT 24U

5151

#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_WIDTH 8U

5152

#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_289

5153

#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2

5154

5155

#define LPDDR4__DENALI_PI_290_READ_MASK 0xFFFFFFFFU

5156

#define LPDDR4__DENALI_PI_290_WRITE_MASK 0xFFFFFFFFU

5157

#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_MASK 0x000000FFU

5158

#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_SHIFT 0U

5159

#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_WIDTH 8U

5160

#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_290

5161

#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2

5162

5163

#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_MASK 0x0000FF00U

5164

#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_SHIFT 8U

5165

#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_WIDTH 8U

5166

#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_290

5167

#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2

5168

5169

#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_MASK 0x00FF0000U

5170

#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_SHIFT 16U

5171

#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_WIDTH 8U

5172

#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_290

5173

#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2

5174

5175

#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_MASK 0xFF000000U

5176

#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_SHIFT 24U

5177

#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_WIDTH 8U

5178

#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_290

5179

#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2

5180

5181

#define LPDDR4__DENALI_PI_291_READ_MASK 0xFFFFFFFFU

5182

#define LPDDR4__DENALI_PI_291_WRITE_MASK 0xFFFFFFFFU

5183

#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_MASK 0x000000FFU

5184

#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_SHIFT 0U

5185

#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_WIDTH 8U

5186

#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_291

5187

#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2

5188

5189

#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_MASK 0x0000FF00U

5190

#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_SHIFT 8U

5191

#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_WIDTH 8U

5192

#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_291

5193

#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2

5194

5195

#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_MASK 0x00FF0000U

5196

#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_SHIFT 16U

5197

#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_WIDTH 8U

5198

#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_291

5199

#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2

5200

5201

#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_MASK 0xFF000000U

5202

#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_SHIFT 24U

5203

#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_WIDTH 8U

5204

#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_291

5205

#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2

5206

5207

#define LPDDR4__DENALI_PI_292_READ_MASK 0xFFFFFFFFU

5208

#define LPDDR4__DENALI_PI_292_WRITE_MASK 0xFFFFFFFFU

5209

#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_MASK 0x000000FFU

5210

#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_SHIFT 0U

5211

#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_WIDTH 8U

5212

#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_292

5213

#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2

5214

5215

#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_MASK 0x0000FF00U

5216

#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_SHIFT 8U

5217

#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_WIDTH 8U

5218

#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_292

5219

#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2

5220

5221

#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_MASK 0x00FF0000U

5222

#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_SHIFT 16U

5223

#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_WIDTH 8U

5224

#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_292

5225

#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2

5226

5227

#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_MASK 0xFF000000U

5228

#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_SHIFT 24U

5229

#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_WIDTH 8U

5230

#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_292

5231

#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2

5232

5233

#define LPDDR4__DENALI_PI_293_READ_MASK 0xFFFFFFFFU

5234

#define LPDDR4__DENALI_PI_293_WRITE_MASK 0xFFFFFFFFU

5235

#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_MASK 0x000000FFU

5236

#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_SHIFT 0U

5237

#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_WIDTH 8U

5238

#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_293

5239

#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3

5240

5241

#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_MASK 0x0000FF00U

5242

#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_SHIFT 8U

5243

#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_WIDTH 8U

5244

#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_293

5245

#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3

5246

5247

#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_MASK 0x00FF0000U

5248

#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_SHIFT 16U

5249

#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_WIDTH 8U

5250

#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_293

5251

#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3

5252

5253

#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_MASK 0xFF000000U

5254

#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_SHIFT 24U

5255

#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_WIDTH 8U

5256

#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_293

5257

#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3

5258

5259

#define LPDDR4__DENALI_PI_294_READ_MASK 0xFFFFFFFFU

5260

#define LPDDR4__DENALI_PI_294_WRITE_MASK 0xFFFFFFFFU

5261

#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_MASK 0x000000FFU

5262

#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_SHIFT 0U

5263

#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_WIDTH 8U

5264

#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_294

5265

#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3

5266

5267

#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_MASK 0x0000FF00U

5268

#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_SHIFT 8U

5269

#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_WIDTH 8U

5270

#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_294

5271

#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3

5272

5273

#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_MASK 0x00FF0000U

5274

#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_SHIFT 16U

5275

#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_WIDTH 8U

5276

#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_294

5277

#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3

5278

5279

#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_MASK 0xFF000000U

5280

#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_SHIFT 24U

5281

#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_WIDTH 8U

5282

#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_294

5283

#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3

5284

5285

#define LPDDR4__DENALI_PI_295_READ_MASK 0xFFFFFFFFU

5286

#define LPDDR4__DENALI_PI_295_WRITE_MASK 0xFFFFFFFFU

5287

#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_MASK 0x000000FFU

5288

#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_SHIFT 0U

5289

#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_WIDTH 8U

5290

#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_295

5291

#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3

5292

5293

#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_MASK 0x0000FF00U

5294

#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_SHIFT 8U

5295

#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_WIDTH 8U

5296

#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_295

5297

#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3

5298

5299

#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_MASK 0x00FF0000U

5300

#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_SHIFT 16U

5301

#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_WIDTH 8U

5302

#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_295

5303

#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3

5304

5305

#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_MASK 0xFF000000U

5306

#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_SHIFT 24U

5307

#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_WIDTH 8U

5308

#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_295

5309

#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3

5310

5311

#define LPDDR4__DENALI_PI_296_READ_MASK 0xFFFFFFFFU

5312

#define LPDDR4__DENALI_PI_296_WRITE_MASK 0xFFFFFFFFU

5313

#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_MASK 0x000000FFU

5314

#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_SHIFT 0U

5315

#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_WIDTH 8U

5316

#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_296

5317

#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3

5318

5319

#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_MASK 0x0000FF00U

5320

#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_SHIFT 8U

5321

#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_WIDTH 8U

5322

#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_296

5323

#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3

5324

5325

#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_MASK 0x00FF0000U

5326

#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_SHIFT 16U

5327

#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_WIDTH 8U

5328

#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_296

5329

#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3

5330

5331

#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_MASK 0xFF000000U

5332

#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_SHIFT 24U

5333

#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_WIDTH 8U

5334

#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_296

5335

#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3

5336

5337

#define LPDDR4__DENALI_PI_297_READ_MASK 0xFFFFFFFFU

5338

#define LPDDR4__DENALI_PI_297_WRITE_MASK 0xFFFFFFFFU

5339

#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_MASK 0x000000FFU

5340

#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_SHIFT 0U

5341

#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_WIDTH 8U

5342

#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_297

5343

#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3

5344

5345

#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_MASK 0x0000FF00U

5346

#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_SHIFT 8U

5347

#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_WIDTH 8U

5348

#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_297

5349

#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3

5350

5351

#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_MASK 0x00FF0000U

5352

#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_SHIFT 16U

5353

#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_WIDTH 8U

5354

#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_297

5355

#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3

5356

5357

#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_MASK 0xFF000000U

5358

#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_SHIFT 24U

5359

#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_WIDTH 8U

5360

#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_297

5361

#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3

5362

5363

#define LPDDR4__DENALI_PI_298_READ_MASK 0xFFFFFFFFU

5364

#define LPDDR4__DENALI_PI_298_WRITE_MASK 0xFFFFFFFFU

5365

#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_MASK 0x000000FFU

5366

#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_SHIFT 0U

5367

#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_WIDTH 8U

5368

#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_298

5369

#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3

5370

5371

#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_MASK 0x0000FF00U

5372

#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_SHIFT 8U

5373

#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_WIDTH 8U

5374

#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_298

5375

#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3

5376

5377

#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_MASK 0x00FF0000U

5378

#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_SHIFT 16U

5379

#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_WIDTH 8U

5380

#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_298

5381

#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3

5382

5383

#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_MASK 0xFF000000U

5384

#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_SHIFT 24U

5385

#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_WIDTH 8U

5386

#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_298

5387

#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3

5388

5389

#define LPDDR4__DENALI_PI_299_READ_MASK 0x000007FFU

5390

#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x000007FFU

5391

#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_MASK 0x000007FFU

5392

#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_SHIFT 0U

5393

#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_WIDTH 11U

5394

#define LPDDR4__PI_PARITY_ERROR_REGIF__REG DENALI_PI_299

5395

#define LPDDR4__PI_PARITY_ERROR_REGIF__FLD LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF

5396

5397

#endif /* REG_LPDDR4_PI_MACROS_H_ */