Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | |
Bin Meng | 497c516 | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 8 | #include <asm/arch-baytrail/fsp/fsp_configs.h> |
Gabriel Huau | f813548 | 2015-05-25 22:27:37 -0700 | [diff] [blame] | 9 | #include <dt-bindings/gpio/x86-gpio.h> |
Simon Glass | 7133c39 | 2015-08-13 10:36:16 -0600 | [diff] [blame] | 10 | #include <dt-bindings/interrupt-router/intel-irq.h> |
Gabriel Huau | f813548 | 2015-05-25 22:27:37 -0700 | [diff] [blame] | 11 | |
Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 12 | /include/ "skeleton.dtsi" |
| 13 | /include/ "serial.dtsi" |
Bin Meng | af5b8d2 | 2018-07-19 03:07:33 -0700 | [diff] [blame] | 14 | /include/ "reset.dtsi" |
Bin Meng | 770fd33 | 2015-07-15 16:23:39 +0800 | [diff] [blame] | 15 | /include/ "rtc.dtsi" |
Bin Meng | 38de020 | 2015-11-13 00:11:22 -0800 | [diff] [blame] | 16 | /include/ "tsc_timer.dtsi" |
Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 17 | |
| 18 | / { |
| 19 | model = "Intel Minnowboard Max"; |
| 20 | compatible = "intel,minnowmax", "intel,baytrail"; |
| 21 | |
| 22 | aliases { |
| 23 | serial0 = &serial; |
Bin Meng | 4f8d4e9 | 2016-01-27 00:56:34 -0800 | [diff] [blame] | 24 | spi0 = &spi; |
Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 25 | }; |
| 26 | |
| 27 | config { |
| 28 | silent_console = <0>; |
| 29 | }; |
| 30 | |
Gabriel Huau | f813548 | 2015-05-25 22:27:37 -0700 | [diff] [blame] | 31 | pch_pinctrl { |
| 32 | compatible = "intel,x86-pinctrl"; |
Bin Meng | de6d198 | 2016-06-08 05:07:33 -0700 | [diff] [blame] | 33 | reg = <0 0>; |
Gabriel Huau | f813548 | 2015-05-25 22:27:37 -0700 | [diff] [blame] | 34 | |
Simon Glass | 1b46485 | 2015-08-22 15:58:53 -0600 | [diff] [blame] | 35 | /* GPIO E0 */ |
| 36 | soc_gpio_s5_0@0 { |
| 37 | gpio-offset = <0x80 0>; |
Simon Glass | 1b46485 | 2015-08-22 15:58:53 -0600 | [diff] [blame] | 38 | mode-gpio; |
| 39 | output-value = <0>; |
| 40 | direction = <PIN_OUTPUT>; |
| 41 | }; |
| 42 | |
| 43 | /* GPIO E1 */ |
| 44 | soc_gpio_s5_1@0 { |
| 45 | gpio-offset = <0x80 1>; |
Simon Glass | 1b46485 | 2015-08-22 15:58:53 -0600 | [diff] [blame] | 46 | mode-gpio; |
| 47 | output-value = <0>; |
| 48 | direction = <PIN_OUTPUT>; |
| 49 | }; |
| 50 | |
| 51 | /* GPIO E2 */ |
| 52 | soc_gpio_s5_2@0 { |
| 53 | gpio-offset = <0x80 2>; |
Simon Glass | 1b46485 | 2015-08-22 15:58:53 -0600 | [diff] [blame] | 54 | mode-gpio; |
| 55 | output-value = <0>; |
| 56 | direction = <PIN_OUTPUT>; |
| 57 | }; |
| 58 | |
Gabriel Huau | f813548 | 2015-05-25 22:27:37 -0700 | [diff] [blame] | 59 | pin_usb_host_en0@0 { |
| 60 | gpio-offset = <0x80 8>; |
Gabriel Huau | f813548 | 2015-05-25 22:27:37 -0700 | [diff] [blame] | 61 | mode-gpio; |
| 62 | output-value = <1>; |
| 63 | direction = <PIN_OUTPUT>; |
| 64 | }; |
| 65 | |
| 66 | pin_usb_host_en1@0 { |
| 67 | gpio-offset = <0x80 9>; |
Gabriel Huau | f813548 | 2015-05-25 22:27:37 -0700 | [diff] [blame] | 68 | mode-gpio; |
| 69 | output-value = <1>; |
| 70 | direction = <PIN_OUTPUT>; |
| 71 | }; |
Bin Meng | e4d977f | 2016-06-08 05:07:35 -0700 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * As of today, the latest version FSP (gold4) for BayTrail |
| 75 | * misses the PAD configuration of the SD controller's Card |
| 76 | * Detect signal. The default PAD value for the CD pin sets |
| 77 | * the pin to work in GPIO mode, which causes card detect |
| 78 | * status cannot be reflected by the Present State register |
| 79 | * in the SD controller (bit 16 & bit 18 are always zero). |
| 80 | * |
| 81 | * Configure this pin to function 1 (SD controller). |
| 82 | */ |
| 83 | sdmmc3_cd@0 { |
| 84 | pad-offset = <0x3a0>; |
| 85 | mode-func = <1>; |
| 86 | }; |
Gabriel Huau | f813548 | 2015-05-25 22:27:37 -0700 | [diff] [blame] | 87 | }; |
| 88 | |
Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 89 | chosen { |
| 90 | stdout-path = "/serial"; |
| 91 | }; |
| 92 | |
Simon Glass | 1eaaf6c | 2015-04-29 22:26:03 -0600 | [diff] [blame] | 93 | cpus { |
| 94 | #address-cells = <1>; |
| 95 | #size-cells = <0>; |
| 96 | |
| 97 | cpu@0 { |
| 98 | device_type = "cpu"; |
| 99 | compatible = "intel,baytrail-cpu"; |
| 100 | reg = <0>; |
| 101 | intel,apic-id = <0>; |
| 102 | }; |
| 103 | |
| 104 | cpu@1 { |
| 105 | device_type = "cpu"; |
| 106 | compatible = "intel,baytrail-cpu"; |
| 107 | reg = <1>; |
| 108 | intel,apic-id = <4>; |
| 109 | }; |
| 110 | |
| 111 | }; |
| 112 | |
Simon Glass | 0e87edc | 2015-07-03 18:28:26 -0600 | [diff] [blame] | 113 | pci { |
| 114 | compatible = "intel,pci-baytrail", "pci-x86"; |
| 115 | #address-cells = <3>; |
| 116 | #size-cells = <2>; |
| 117 | u-boot,dm-pre-reloc; |
Simon Glass | 7133c39 | 2015-08-13 10:36:16 -0600 | [diff] [blame] | 118 | ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 |
| 119 | 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 |
| 120 | 0x01000000 0x0 0x2000 0x2000 0 0xe000>; |
| 121 | |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 122 | pch@1f,0 { |
Simon Glass | 7133c39 | 2015-08-13 10:36:16 -0600 | [diff] [blame] | 123 | reg = <0x0000f800 0 0 0 0>; |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 124 | compatible = "pci8086,0f1c", "intel,pch9"; |
Bin Meng | 6e916cc | 2016-02-01 01:40:47 -0800 | [diff] [blame] | 125 | #address-cells = <1>; |
| 126 | #size-cells = <1>; |
Simon Glass | 7133c39 | 2015-08-13 10:36:16 -0600 | [diff] [blame] | 127 | |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 128 | irq-router { |
| 129 | compatible = "intel,irq-router"; |
| 130 | intel,pirq-config = "ibase"; |
| 131 | intel,ibase-offset = <0x50>; |
Bin Meng | 0651f62 | 2016-05-07 07:46:15 -0700 | [diff] [blame] | 132 | intel,actl-addr = <0>; |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 133 | intel,pirq-link = <8 8>; |
| 134 | intel,pirq-mask = <0xdee0>; |
| 135 | intel,pirq-routing = < |
| 136 | /* BayTrail PCI devices */ |
| 137 | PCI_BDF(0, 2, 0) INTA PIRQA |
| 138 | PCI_BDF(0, 3, 0) INTA PIRQA |
| 139 | PCI_BDF(0, 16, 0) INTA PIRQA |
| 140 | PCI_BDF(0, 17, 0) INTA PIRQA |
| 141 | PCI_BDF(0, 18, 0) INTA PIRQA |
| 142 | PCI_BDF(0, 19, 0) INTA PIRQA |
| 143 | PCI_BDF(0, 20, 0) INTA PIRQA |
| 144 | PCI_BDF(0, 21, 0) INTA PIRQA |
| 145 | PCI_BDF(0, 22, 0) INTA PIRQA |
| 146 | PCI_BDF(0, 23, 0) INTA PIRQA |
| 147 | PCI_BDF(0, 24, 0) INTA PIRQA |
| 148 | PCI_BDF(0, 24, 1) INTC PIRQC |
| 149 | PCI_BDF(0, 24, 2) INTD PIRQD |
| 150 | PCI_BDF(0, 24, 3) INTB PIRQB |
| 151 | PCI_BDF(0, 24, 4) INTA PIRQA |
| 152 | PCI_BDF(0, 24, 5) INTC PIRQC |
| 153 | PCI_BDF(0, 24, 6) INTD PIRQD |
| 154 | PCI_BDF(0, 24, 7) INTB PIRQB |
| 155 | PCI_BDF(0, 26, 0) INTA PIRQA |
| 156 | PCI_BDF(0, 27, 0) INTA PIRQA |
| 157 | PCI_BDF(0, 28, 0) INTA PIRQA |
| 158 | PCI_BDF(0, 28, 1) INTB PIRQB |
| 159 | PCI_BDF(0, 28, 2) INTC PIRQC |
| 160 | PCI_BDF(0, 28, 3) INTD PIRQD |
| 161 | PCI_BDF(0, 29, 0) INTA PIRQA |
| 162 | PCI_BDF(0, 30, 0) INTA PIRQA |
| 163 | PCI_BDF(0, 30, 1) INTD PIRQD |
| 164 | PCI_BDF(0, 30, 2) INTB PIRQB |
| 165 | PCI_BDF(0, 30, 3) INTC PIRQC |
| 166 | PCI_BDF(0, 30, 4) INTD PIRQD |
| 167 | PCI_BDF(0, 30, 5) INTB PIRQB |
| 168 | PCI_BDF(0, 31, 3) INTB PIRQB |
| 169 | |
| 170 | /* |
| 171 | * PCIe root ports downstream |
| 172 | * interrupts |
| 173 | */ |
| 174 | PCI_BDF(1, 0, 0) INTA PIRQA |
| 175 | PCI_BDF(1, 0, 0) INTB PIRQB |
| 176 | PCI_BDF(1, 0, 0) INTC PIRQC |
| 177 | PCI_BDF(1, 0, 0) INTD PIRQD |
| 178 | PCI_BDF(2, 0, 0) INTA PIRQB |
| 179 | PCI_BDF(2, 0, 0) INTB PIRQC |
| 180 | PCI_BDF(2, 0, 0) INTC PIRQD |
| 181 | PCI_BDF(2, 0, 0) INTD PIRQA |
| 182 | PCI_BDF(3, 0, 0) INTA PIRQC |
| 183 | PCI_BDF(3, 0, 0) INTB PIRQD |
| 184 | PCI_BDF(3, 0, 0) INTC PIRQA |
| 185 | PCI_BDF(3, 0, 0) INTD PIRQB |
| 186 | PCI_BDF(4, 0, 0) INTA PIRQD |
| 187 | PCI_BDF(4, 0, 0) INTB PIRQA |
| 188 | PCI_BDF(4, 0, 0) INTC PIRQB |
| 189 | PCI_BDF(4, 0, 0) INTD PIRQC |
| 190 | >; |
| 191 | }; |
| 192 | |
Bin Meng | 4f8d4e9 | 2016-01-27 00:56:34 -0800 | [diff] [blame] | 193 | spi: spi { |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 194 | #address-cells = <1>; |
| 195 | #size-cells = <0>; |
Bin Meng | d940667 | 2016-02-01 01:40:37 -0800 | [diff] [blame] | 196 | compatible = "intel,ich9-spi"; |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 197 | spi-flash@0 { |
| 198 | #address-cells = <1>; |
| 199 | #size-cells = <1>; |
| 200 | reg = <0>; |
| 201 | compatible = "stmicro,n25q064a", |
| 202 | "spi-flash"; |
| 203 | memory-map = <0xff800000 0x00800000>; |
| 204 | rw-mrc-cache { |
| 205 | label = "rw-mrc-cache"; |
| 206 | reg = <0x006f0000 0x00010000>; |
| 207 | }; |
| 208 | }; |
| 209 | }; |
Bin Meng | 6e916cc | 2016-02-01 01:40:47 -0800 | [diff] [blame] | 210 | |
| 211 | gpioa { |
| 212 | compatible = "intel,ich6-gpio"; |
| 213 | u-boot,dm-pre-reloc; |
| 214 | reg = <0 0x20>; |
| 215 | bank-name = "A"; |
Bin Meng | 59be2c0 | 2017-05-07 19:52:29 -0700 | [diff] [blame] | 216 | use-lvl-write-cache; |
Bin Meng | 6e916cc | 2016-02-01 01:40:47 -0800 | [diff] [blame] | 217 | }; |
| 218 | |
| 219 | gpiob { |
| 220 | compatible = "intel,ich6-gpio"; |
| 221 | u-boot,dm-pre-reloc; |
| 222 | reg = <0x20 0x20>; |
| 223 | bank-name = "B"; |
Bin Meng | 59be2c0 | 2017-05-07 19:52:29 -0700 | [diff] [blame] | 224 | use-lvl-write-cache; |
Bin Meng | 6e916cc | 2016-02-01 01:40:47 -0800 | [diff] [blame] | 225 | }; |
| 226 | |
| 227 | gpioc { |
| 228 | compatible = "intel,ich6-gpio"; |
| 229 | u-boot,dm-pre-reloc; |
| 230 | reg = <0x40 0x20>; |
| 231 | bank-name = "C"; |
Bin Meng | 59be2c0 | 2017-05-07 19:52:29 -0700 | [diff] [blame] | 232 | use-lvl-write-cache; |
Bin Meng | 6e916cc | 2016-02-01 01:40:47 -0800 | [diff] [blame] | 233 | }; |
| 234 | |
| 235 | gpiod { |
| 236 | compatible = "intel,ich6-gpio"; |
| 237 | u-boot,dm-pre-reloc; |
| 238 | reg = <0x60 0x20>; |
| 239 | bank-name = "D"; |
Bin Meng | 59be2c0 | 2017-05-07 19:52:29 -0700 | [diff] [blame] | 240 | use-lvl-write-cache; |
Bin Meng | 6e916cc | 2016-02-01 01:40:47 -0800 | [diff] [blame] | 241 | }; |
| 242 | |
| 243 | gpioe { |
| 244 | compatible = "intel,ich6-gpio"; |
| 245 | u-boot,dm-pre-reloc; |
| 246 | reg = <0x80 0x20>; |
| 247 | bank-name = "E"; |
Bin Meng | 59be2c0 | 2017-05-07 19:52:29 -0700 | [diff] [blame] | 248 | use-lvl-write-cache; |
Bin Meng | 6e916cc | 2016-02-01 01:40:47 -0800 | [diff] [blame] | 249 | }; |
| 250 | |
| 251 | gpiof { |
| 252 | compatible = "intel,ich6-gpio"; |
| 253 | u-boot,dm-pre-reloc; |
| 254 | reg = <0xA0 0x20>; |
| 255 | bank-name = "F"; |
Bin Meng | 59be2c0 | 2017-05-07 19:52:29 -0700 | [diff] [blame] | 256 | use-lvl-write-cache; |
Bin Meng | 6e916cc | 2016-02-01 01:40:47 -0800 | [diff] [blame] | 257 | }; |
Simon Glass | 7133c39 | 2015-08-13 10:36:16 -0600 | [diff] [blame] | 258 | }; |
Simon Glass | 0e87edc | 2015-07-03 18:28:26 -0600 | [diff] [blame] | 259 | }; |
| 260 | |
Andrew Bradford | 74fdb58 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 261 | fsp { |
| 262 | compatible = "intel,baytrail-fsp"; |
Bin Meng | 497c516 | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 263 | fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>; |
| 264 | fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>; |
Andrew Bradford | 74fdb58 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 265 | fsp,mrc-init-spd-addr1 = <0xa0>; |
| 266 | fsp,mrc-init-spd-addr2 = <0xa2>; |
Bin Meng | 497c516 | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 267 | fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>; |
Andrew Bradford | 74fdb58 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 268 | fsp,enable-sdio; |
| 269 | fsp,enable-sdcard; |
| 270 | fsp,enable-hsuart1; |
| 271 | fsp,enable-spi; |
| 272 | fsp,enable-sata; |
Bin Meng | 497c516 | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 273 | fsp,sata-mode = <SATA_MODE_AHCI>; |
Bin Meng | bfe1c71 | 2017-07-19 21:50:10 +0800 | [diff] [blame] | 274 | #ifdef CONFIG_USB_XHCI_HCD |
| 275 | fsp,enable-xhci; |
| 276 | #endif |
Bin Meng | e5bf969 | 2017-05-31 01:04:15 -0700 | [diff] [blame] | 277 | fsp,lpe-mode = <LPE_MODE_PCI>; |
| 278 | fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; |
Andrew Bradford | 74fdb58 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 279 | fsp,enable-dma0; |
| 280 | fsp,enable-dma1; |
| 281 | fsp,enable-i2c0; |
| 282 | fsp,enable-i2c1; |
| 283 | fsp,enable-i2c2; |
| 284 | fsp,enable-i2c3; |
| 285 | fsp,enable-i2c4; |
| 286 | fsp,enable-i2c5; |
| 287 | fsp,enable-i2c6; |
| 288 | fsp,enable-pwm0; |
| 289 | fsp,enable-pwm1; |
Bin Meng | 497c516 | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 290 | fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>; |
| 291 | fsp,aperture-size = <APERTURE_SIZE_256MB>; |
| 292 | fsp,gtt-size = <GTT_SIZE_2MB>; |
Bin Meng | e5bf969 | 2017-05-31 01:04:15 -0700 | [diff] [blame] | 293 | fsp,scc-mode = <SCC_MODE_PCI>; |
Bin Meng | 497c516 | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 294 | fsp,os-selection = <OS_SELECTION_LINUX>; |
Andrew Bradford | 74fdb58 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 295 | fsp,emmc45-ddr50-enabled; |
| 296 | fsp,emmc45-retune-timer-value = <8>; |
| 297 | fsp,enable-igd; |
| 298 | fsp,enable-memory-down; |
| 299 | fsp,memory-down-params { |
| 300 | compatible = "intel,baytrail-fsp-mdp"; |
Bin Meng | 497c516 | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 301 | fsp,dram-speed = <DRAM_SPEED_1066MTS>; |
| 302 | fsp,dram-type = <DRAM_TYPE_DDR3L>; |
Andrew Bradford | 74fdb58 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 303 | fsp,dimm-0-enable; |
Bin Meng | 497c516 | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 304 | fsp,dimm-width = <DIMM_WIDTH_X16>; |
| 305 | fsp,dimm-density = <DIMM_DENSITY_4GBIT>; |
| 306 | fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>; |
| 307 | fsp,dimm-sides = <DIMM_SIDES_1RANKS>; |
Andrew Bradford | 74fdb58 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 308 | fsp,dimm-tcl = <0xb>; |
| 309 | fsp,dimm-trpt-rcd = <0xb>; |
| 310 | fsp,dimm-twr = <0xc>; |
| 311 | fsp,dimm-twtr = <6>; |
| 312 | fsp,dimm-trrd = <6>; |
| 313 | fsp,dimm-trtp = <6>; |
| 314 | fsp,dimm-tfaw = <0x14>; |
| 315 | }; |
| 316 | }; |
| 317 | |
Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 318 | microcode { |
| 319 | update@0 { |
Bin Meng | ae86455 | 2016-05-23 15:25:20 +0800 | [diff] [blame] | 320 | #include "microcode/m0130673325.dtsi" |
Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 321 | }; |
Bin Meng | 35dffd5 | 2015-08-15 14:37:50 -0600 | [diff] [blame] | 322 | update@1 { |
Bin Meng | ae86455 | 2016-05-23 15:25:20 +0800 | [diff] [blame] | 323 | #include "microcode/m0130679907.dtsi" |
Bin Meng | 35dffd5 | 2015-08-15 14:37:50 -0600 | [diff] [blame] | 324 | }; |
Simon Glass | 4a56f10 | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 325 | }; |
| 326 | |
| 327 | }; |