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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass4a56f102015-01-27 22:13:47 -07002/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
Simon Glass4a56f102015-01-27 22:13:47 -07004 */
5
6/dts-v1/;
7
Bin Meng497c5162017-05-31 01:04:14 -07008#include <asm/arch-baytrail/fsp/fsp_configs.h>
Gabriel Huauf8135482015-05-25 22:27:37 -07009#include <dt-bindings/gpio/x86-gpio.h>
Simon Glass7133c392015-08-13 10:36:16 -060010#include <dt-bindings/interrupt-router/intel-irq.h>
Gabriel Huauf8135482015-05-25 22:27:37 -070011
Simon Glass4a56f102015-01-27 22:13:47 -070012/include/ "skeleton.dtsi"
13/include/ "serial.dtsi"
Bin Mengaf5b8d22018-07-19 03:07:33 -070014/include/ "reset.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +080015/include/ "rtc.dtsi"
Bin Meng38de0202015-11-13 00:11:22 -080016/include/ "tsc_timer.dtsi"
Simon Glass4a56f102015-01-27 22:13:47 -070017
18/ {
19 model = "Intel Minnowboard Max";
20 compatible = "intel,minnowmax", "intel,baytrail";
21
22 aliases {
23 serial0 = &serial;
Bin Meng4f8d4e92016-01-27 00:56:34 -080024 spi0 = &spi;
Simon Glass4a56f102015-01-27 22:13:47 -070025 };
26
27 config {
28 silent_console = <0>;
29 };
30
Gabriel Huauf8135482015-05-25 22:27:37 -070031 pch_pinctrl {
32 compatible = "intel,x86-pinctrl";
Bin Mengde6d1982016-06-08 05:07:33 -070033 reg = <0 0>;
Gabriel Huauf8135482015-05-25 22:27:37 -070034
Simon Glass1b464852015-08-22 15:58:53 -060035 /* GPIO E0 */
36 soc_gpio_s5_0@0 {
37 gpio-offset = <0x80 0>;
Simon Glass1b464852015-08-22 15:58:53 -060038 mode-gpio;
39 output-value = <0>;
40 direction = <PIN_OUTPUT>;
41 };
42
43 /* GPIO E1 */
44 soc_gpio_s5_1@0 {
45 gpio-offset = <0x80 1>;
Simon Glass1b464852015-08-22 15:58:53 -060046 mode-gpio;
47 output-value = <0>;
48 direction = <PIN_OUTPUT>;
49 };
50
51 /* GPIO E2 */
52 soc_gpio_s5_2@0 {
53 gpio-offset = <0x80 2>;
Simon Glass1b464852015-08-22 15:58:53 -060054 mode-gpio;
55 output-value = <0>;
56 direction = <PIN_OUTPUT>;
57 };
58
Gabriel Huauf8135482015-05-25 22:27:37 -070059 pin_usb_host_en0@0 {
60 gpio-offset = <0x80 8>;
Gabriel Huauf8135482015-05-25 22:27:37 -070061 mode-gpio;
62 output-value = <1>;
63 direction = <PIN_OUTPUT>;
64 };
65
66 pin_usb_host_en1@0 {
67 gpio-offset = <0x80 9>;
Gabriel Huauf8135482015-05-25 22:27:37 -070068 mode-gpio;
69 output-value = <1>;
70 direction = <PIN_OUTPUT>;
71 };
Bin Menge4d977f2016-06-08 05:07:35 -070072
73 /*
74 * As of today, the latest version FSP (gold4) for BayTrail
75 * misses the PAD configuration of the SD controller's Card
76 * Detect signal. The default PAD value for the CD pin sets
77 * the pin to work in GPIO mode, which causes card detect
78 * status cannot be reflected by the Present State register
79 * in the SD controller (bit 16 & bit 18 are always zero).
80 *
81 * Configure this pin to function 1 (SD controller).
82 */
83 sdmmc3_cd@0 {
84 pad-offset = <0x3a0>;
85 mode-func = <1>;
86 };
Gabriel Huauf8135482015-05-25 22:27:37 -070087 };
88
Simon Glass4a56f102015-01-27 22:13:47 -070089 chosen {
90 stdout-path = "/serial";
91 };
92
Simon Glass1eaaf6c2015-04-29 22:26:03 -060093 cpus {
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 cpu@0 {
98 device_type = "cpu";
99 compatible = "intel,baytrail-cpu";
100 reg = <0>;
101 intel,apic-id = <0>;
102 };
103
104 cpu@1 {
105 device_type = "cpu";
106 compatible = "intel,baytrail-cpu";
107 reg = <1>;
108 intel,apic-id = <4>;
109 };
110
111 };
112
Simon Glass0e87edc2015-07-03 18:28:26 -0600113 pci {
114 compatible = "intel,pci-baytrail", "pci-x86";
115 #address-cells = <3>;
116 #size-cells = <2>;
117 u-boot,dm-pre-reloc;
Simon Glass7133c392015-08-13 10:36:16 -0600118 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
119 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
120 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
121
Simon Glass32761632016-01-18 20:19:21 -0700122 pch@1f,0 {
Simon Glass7133c392015-08-13 10:36:16 -0600123 reg = <0x0000f800 0 0 0 0>;
Simon Glass32761632016-01-18 20:19:21 -0700124 compatible = "pci8086,0f1c", "intel,pch9";
Bin Meng6e916cc2016-02-01 01:40:47 -0800125 #address-cells = <1>;
126 #size-cells = <1>;
Simon Glass7133c392015-08-13 10:36:16 -0600127
Simon Glass32761632016-01-18 20:19:21 -0700128 irq-router {
129 compatible = "intel,irq-router";
130 intel,pirq-config = "ibase";
131 intel,ibase-offset = <0x50>;
Bin Meng0651f622016-05-07 07:46:15 -0700132 intel,actl-addr = <0>;
Simon Glass32761632016-01-18 20:19:21 -0700133 intel,pirq-link = <8 8>;
134 intel,pirq-mask = <0xdee0>;
135 intel,pirq-routing = <
136 /* BayTrail PCI devices */
137 PCI_BDF(0, 2, 0) INTA PIRQA
138 PCI_BDF(0, 3, 0) INTA PIRQA
139 PCI_BDF(0, 16, 0) INTA PIRQA
140 PCI_BDF(0, 17, 0) INTA PIRQA
141 PCI_BDF(0, 18, 0) INTA PIRQA
142 PCI_BDF(0, 19, 0) INTA PIRQA
143 PCI_BDF(0, 20, 0) INTA PIRQA
144 PCI_BDF(0, 21, 0) INTA PIRQA
145 PCI_BDF(0, 22, 0) INTA PIRQA
146 PCI_BDF(0, 23, 0) INTA PIRQA
147 PCI_BDF(0, 24, 0) INTA PIRQA
148 PCI_BDF(0, 24, 1) INTC PIRQC
149 PCI_BDF(0, 24, 2) INTD PIRQD
150 PCI_BDF(0, 24, 3) INTB PIRQB
151 PCI_BDF(0, 24, 4) INTA PIRQA
152 PCI_BDF(0, 24, 5) INTC PIRQC
153 PCI_BDF(0, 24, 6) INTD PIRQD
154 PCI_BDF(0, 24, 7) INTB PIRQB
155 PCI_BDF(0, 26, 0) INTA PIRQA
156 PCI_BDF(0, 27, 0) INTA PIRQA
157 PCI_BDF(0, 28, 0) INTA PIRQA
158 PCI_BDF(0, 28, 1) INTB PIRQB
159 PCI_BDF(0, 28, 2) INTC PIRQC
160 PCI_BDF(0, 28, 3) INTD PIRQD
161 PCI_BDF(0, 29, 0) INTA PIRQA
162 PCI_BDF(0, 30, 0) INTA PIRQA
163 PCI_BDF(0, 30, 1) INTD PIRQD
164 PCI_BDF(0, 30, 2) INTB PIRQB
165 PCI_BDF(0, 30, 3) INTC PIRQC
166 PCI_BDF(0, 30, 4) INTD PIRQD
167 PCI_BDF(0, 30, 5) INTB PIRQB
168 PCI_BDF(0, 31, 3) INTB PIRQB
169
170 /*
171 * PCIe root ports downstream
172 * interrupts
173 */
174 PCI_BDF(1, 0, 0) INTA PIRQA
175 PCI_BDF(1, 0, 0) INTB PIRQB
176 PCI_BDF(1, 0, 0) INTC PIRQC
177 PCI_BDF(1, 0, 0) INTD PIRQD
178 PCI_BDF(2, 0, 0) INTA PIRQB
179 PCI_BDF(2, 0, 0) INTB PIRQC
180 PCI_BDF(2, 0, 0) INTC PIRQD
181 PCI_BDF(2, 0, 0) INTD PIRQA
182 PCI_BDF(3, 0, 0) INTA PIRQC
183 PCI_BDF(3, 0, 0) INTB PIRQD
184 PCI_BDF(3, 0, 0) INTC PIRQA
185 PCI_BDF(3, 0, 0) INTD PIRQB
186 PCI_BDF(4, 0, 0) INTA PIRQD
187 PCI_BDF(4, 0, 0) INTB PIRQA
188 PCI_BDF(4, 0, 0) INTC PIRQB
189 PCI_BDF(4, 0, 0) INTD PIRQC
190 >;
191 };
192
Bin Meng4f8d4e92016-01-27 00:56:34 -0800193 spi: spi {
Simon Glass32761632016-01-18 20:19:21 -0700194 #address-cells = <1>;
195 #size-cells = <0>;
Bin Mengd9406672016-02-01 01:40:37 -0800196 compatible = "intel,ich9-spi";
Simon Glass32761632016-01-18 20:19:21 -0700197 spi-flash@0 {
198 #address-cells = <1>;
199 #size-cells = <1>;
200 reg = <0>;
201 compatible = "stmicro,n25q064a",
202 "spi-flash";
203 memory-map = <0xff800000 0x00800000>;
204 rw-mrc-cache {
205 label = "rw-mrc-cache";
206 reg = <0x006f0000 0x00010000>;
207 };
208 };
209 };
Bin Meng6e916cc2016-02-01 01:40:47 -0800210
211 gpioa {
212 compatible = "intel,ich6-gpio";
213 u-boot,dm-pre-reloc;
214 reg = <0 0x20>;
215 bank-name = "A";
Bin Meng59be2c02017-05-07 19:52:29 -0700216 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800217 };
218
219 gpiob {
220 compatible = "intel,ich6-gpio";
221 u-boot,dm-pre-reloc;
222 reg = <0x20 0x20>;
223 bank-name = "B";
Bin Meng59be2c02017-05-07 19:52:29 -0700224 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800225 };
226
227 gpioc {
228 compatible = "intel,ich6-gpio";
229 u-boot,dm-pre-reloc;
230 reg = <0x40 0x20>;
231 bank-name = "C";
Bin Meng59be2c02017-05-07 19:52:29 -0700232 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800233 };
234
235 gpiod {
236 compatible = "intel,ich6-gpio";
237 u-boot,dm-pre-reloc;
238 reg = <0x60 0x20>;
239 bank-name = "D";
Bin Meng59be2c02017-05-07 19:52:29 -0700240 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800241 };
242
243 gpioe {
244 compatible = "intel,ich6-gpio";
245 u-boot,dm-pre-reloc;
246 reg = <0x80 0x20>;
247 bank-name = "E";
Bin Meng59be2c02017-05-07 19:52:29 -0700248 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800249 };
250
251 gpiof {
252 compatible = "intel,ich6-gpio";
253 u-boot,dm-pre-reloc;
254 reg = <0xA0 0x20>;
255 bank-name = "F";
Bin Meng59be2c02017-05-07 19:52:29 -0700256 use-lvl-write-cache;
Bin Meng6e916cc2016-02-01 01:40:47 -0800257 };
Simon Glass7133c392015-08-13 10:36:16 -0600258 };
Simon Glass0e87edc2015-07-03 18:28:26 -0600259 };
260
Andrew Bradford74fdb582015-08-07 08:36:35 -0400261 fsp {
262 compatible = "intel,baytrail-fsp";
Bin Meng497c5162017-05-31 01:04:14 -0700263 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
264 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400265 fsp,mrc-init-spd-addr1 = <0xa0>;
266 fsp,mrc-init-spd-addr2 = <0xa2>;
Bin Meng497c5162017-05-31 01:04:14 -0700267 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400268 fsp,enable-sdio;
269 fsp,enable-sdcard;
270 fsp,enable-hsuart1;
271 fsp,enable-spi;
272 fsp,enable-sata;
Bin Meng497c5162017-05-31 01:04:14 -0700273 fsp,sata-mode = <SATA_MODE_AHCI>;
Bin Mengbfe1c712017-07-19 21:50:10 +0800274#ifdef CONFIG_USB_XHCI_HCD
275 fsp,enable-xhci;
276#endif
Bin Menge5bf9692017-05-31 01:04:15 -0700277 fsp,lpe-mode = <LPE_MODE_PCI>;
278 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400279 fsp,enable-dma0;
280 fsp,enable-dma1;
281 fsp,enable-i2c0;
282 fsp,enable-i2c1;
283 fsp,enable-i2c2;
284 fsp,enable-i2c3;
285 fsp,enable-i2c4;
286 fsp,enable-i2c5;
287 fsp,enable-i2c6;
288 fsp,enable-pwm0;
289 fsp,enable-pwm1;
Bin Meng497c5162017-05-31 01:04:14 -0700290 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
291 fsp,aperture-size = <APERTURE_SIZE_256MB>;
292 fsp,gtt-size = <GTT_SIZE_2MB>;
Bin Menge5bf9692017-05-31 01:04:15 -0700293 fsp,scc-mode = <SCC_MODE_PCI>;
Bin Meng497c5162017-05-31 01:04:14 -0700294 fsp,os-selection = <OS_SELECTION_LINUX>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400295 fsp,emmc45-ddr50-enabled;
296 fsp,emmc45-retune-timer-value = <8>;
297 fsp,enable-igd;
298 fsp,enable-memory-down;
299 fsp,memory-down-params {
300 compatible = "intel,baytrail-fsp-mdp";
Bin Meng497c5162017-05-31 01:04:14 -0700301 fsp,dram-speed = <DRAM_SPEED_1066MTS>;
302 fsp,dram-type = <DRAM_TYPE_DDR3L>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400303 fsp,dimm-0-enable;
Bin Meng497c5162017-05-31 01:04:14 -0700304 fsp,dimm-width = <DIMM_WIDTH_X16>;
305 fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
306 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
307 fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
Andrew Bradford74fdb582015-08-07 08:36:35 -0400308 fsp,dimm-tcl = <0xb>;
309 fsp,dimm-trpt-rcd = <0xb>;
310 fsp,dimm-twr = <0xc>;
311 fsp,dimm-twtr = <6>;
312 fsp,dimm-trrd = <6>;
313 fsp,dimm-trtp = <6>;
314 fsp,dimm-tfaw = <0x14>;
315 };
316 };
317
Simon Glass4a56f102015-01-27 22:13:47 -0700318 microcode {
319 update@0 {
Bin Mengae864552016-05-23 15:25:20 +0800320#include "microcode/m0130673325.dtsi"
Simon Glass4a56f102015-01-27 22:13:47 -0700321 };
Bin Meng35dffd52015-08-15 14:37:50 -0600322 update@1 {
Bin Mengae864552016-05-23 15:25:20 +0800323#include "microcode/m0130679907.dtsi"
Bin Meng35dffd52015-08-15 14:37:50 -0600324 };
Simon Glass4a56f102015-01-27 22:13:47 -0700325 };
326
327};