| Angelo Dureghello | 9ffe1eb | 2019-03-13 21:46:53 +0100 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2019 |
| 4 | * Angelo Dureghello <angleo@sysam.it> |
| 5 | * |
| 6 | * CPU specific dspi routines |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <asm/immap.h> |
| 11 | #include <asm/io.h> |
| 12 | |
| 13 | #ifdef CONFIG_CF_DSPI |
| 14 | void dspi_chip_select(int cs) |
| 15 | { |
| 16 | struct gpio *gpio = (struct gpio *)MMAP_GPIO; |
| 17 | |
| 18 | #ifdef CONFIG_MCF5445x |
| 19 | switch (cs) { |
| 20 | case 0: |
| 21 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); |
| 22 | setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); |
| 23 | break; |
| 24 | case 1: |
| 25 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); |
| 26 | setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); |
| 27 | break; |
| 28 | case 2: |
| 29 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); |
| 30 | setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); |
| 31 | break; |
| 32 | case 3: |
| 33 | clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); |
| 34 | setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3); |
| 35 | break; |
| 36 | case 5: |
| 37 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); |
| 38 | setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); |
| 39 | break; |
| 40 | } |
| 41 | #endif |
| 42 | #ifdef CONFIG_MCF5441x |
| 43 | switch (cs) { |
| 44 | case 0: |
| 45 | clrbits_8(&gpio->par_dspi0, |
| 46 | ~GPIO_PAR_DSPI0_PCS0_MASK); |
| 47 | setbits_8(&gpio->par_dspi0, |
| 48 | GPIO_PAR_DSPI0_PCS0_DSPI0PCS0); |
| 49 | break; |
| 50 | case 1: |
| 51 | clrbits_8(&gpio->par_dspiow, |
| 52 | GPIO_PAR_DSPIOW_DSPI0PSC1); |
| 53 | setbits_8(&gpio->par_dspiow, |
| 54 | GPIO_PAR_DSPIOW_DSPI0PSC1); |
| 55 | break; |
| 56 | } |
| 57 | #endif |
| 58 | } |
| 59 | |
| 60 | void dspi_chip_unselect(int cs) |
| 61 | { |
| 62 | struct gpio *gpio = (struct gpio *)MMAP_GPIO; |
| 63 | |
| 64 | #ifdef CONFIG_MCF5445x |
| 65 | switch (cs) { |
| 66 | case 0: |
| 67 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); |
| 68 | break; |
| 69 | case 1: |
| 70 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); |
| 71 | break; |
| 72 | case 2: |
| 73 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); |
| 74 | break; |
| 75 | case 3: |
| 76 | clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); |
| 77 | break; |
| 78 | case 5: |
| 79 | clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); |
| 80 | break; |
| 81 | } |
| 82 | #endif |
| 83 | #ifdef CONFIG_MCF5441x |
| 84 | if (cs == 1) |
| 85 | clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); |
| 86 | #endif |
| 87 | } |
| 88 | #endif /* CONFIG_CF_DSPI */ |