| Chandan Nath | 77a73fe | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 1 | /* |
| 2 | * omap.h |
| 3 | * |
| 4 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * Author: |
| 7 | * Chandan Nath <chandan.nath@ti.com> |
| 8 | * |
| 9 | * Derived from OMAP4 work by |
| 10 | * Aneesh V <aneesh@ti.com> |
| 11 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 12 | * SPDX-License-Identifier: GPL-2.0+ |
| Chandan Nath | 77a73fe | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #ifndef _OMAP_H_ |
| 16 | #define _OMAP_H_ |
| 17 | |
| 18 | /* |
| 19 | * Non-secure SRAM Addresses |
| 20 | * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE |
| 21 | * at 0x40304000(EMU base) so that our code works for both EMU and GP |
| 22 | */ |
| Matt Porter | 691fbe3 | 2013-03-15 10:07:06 +0000 | [diff] [blame] | 23 | #ifdef CONFIG_AM33XX |
| Tom Rini | 3a30083 | 2013-05-31 10:48:03 -0400 | [diff] [blame] | 24 | #define NON_SECURE_SRAM_START 0x402F0400 |
| 25 | #define NON_SECURE_SRAM_END 0x40310000 |
| Tom Rini | c513b61 | 2013-06-06 08:57:45 -0400 | [diff] [blame] | 26 | #define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 |
| Matt Porter | 691fbe3 | 2013-03-15 10:07:06 +0000 | [diff] [blame] | 27 | #elif defined(CONFIG_TI814X) |
| 28 | #define NON_SECURE_SRAM_START 0x40300000 |
| 29 | #define NON_SECURE_SRAM_END 0x40320000 |
| Tom Rini | c513b61 | 2013-06-06 08:57:45 -0400 | [diff] [blame] | 30 | #define SRAM_SCRATCH_SPACE_ADDR 0x4031B800 |
| Matt Porter | 691fbe3 | 2013-03-15 10:07:06 +0000 | [diff] [blame] | 31 | #endif |
| Chandan Nath | 77a73fe | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 32 | #endif |