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git01.mediatek.com / filogic / uboot / 9fe526db6e1dde0a8710a5c08aedb86dd02693b4 / . / arch / arm / dts / imx93-var-som-symphony.dts
blob: 1bc619427165e38344efae05c242e4257b7bdb7a [file] [log] [blame]
Mathieu Othacehe2415f1d2023-12-29 11:55:23 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 NXP
4 * Copyright 2023 Variscite Ltd.
5 */
6
7/dts-v1/;
8
9#include "imx93-var-som.dtsi"
10
11/{
12 model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";
13 compatible = "variscite,var-som-mx93-symphony",
14 "variscite,var-som-mx93", "fsl,imx93";
15
16 aliases {
17 ethernet0 = &eqos;
18 ethernet1 = &fec;
19 };
20
21 chosen {
22 stdout-path = &lpuart1;
23 };
24
25 /*
26 * Needed only for Symphony <= v1.5
27 */
28 reg_fec_phy: regulator-fec-phy {
29 compatible = "regulator-fixed";
30 regulator-name = "fec-phy";
31 regulator-min-microvolt = <1800000>;
32 regulator-max-microvolt = <1800000>;
33 regulator-enable-ramp-delay = <20000>;
34 gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
35 enable-active-high;
36 regulator-always-on;
37 };
38
39 reg_usdhc2_vmmc: regulator-usdhc2 {
40 compatible = "regulator-fixed";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
43 regulator-name = "VSD_3V3";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
47 off-on-delay-us = <20000>;
48 enable-active-high;
49 };
50
51 reg_vref_1v8: regulator-adc-vref {
52 compatible = "regulator-fixed";
53 regulator-name = "vref_1v8";
54 regulator-min-microvolt = <1800000>;
55 regulator-max-microvolt = <1800000>;
56 };
57
58 reserved-memory {
59 #address-cells = <2>;
60 #size-cells = <2>;
61 ranges;
62
63 ethosu_mem: ethosu-region@88000000 {
64 compatible = "shared-dma-pool";
65 reusable;
66 reg = <0x0 0x88000000 0x0 0x8000000>;
67 };
68
69 vdev0vring0: vdev0vring0@87ee0000 {
70 reg = <0 0x87ee0000 0 0x8000>;
71 no-map;
72 };
73
74 vdev0vring1: vdev0vring1@87ee8000 {
75 reg = <0 0x87ee8000 0 0x8000>;
76 no-map;
77 };
78
79 vdev1vring0: vdev1vring0@87ef0000 {
80 reg = <0 0x87ef0000 0 0x8000>;
81 no-map;
82 };
83
84 vdev1vring1: vdev1vring1@87ef8000 {
85 reg = <0 0x87ef8000 0 0x8000>;
86 no-map;
87 };
88
89 rsc_table: rsc-table@2021f000 {
90 reg = <0 0x2021f000 0 0x1000>;
91 no-map;
92 };
93
94 vdevbuffer: vdevbuffer@87f00000 {
95 compatible = "shared-dma-pool";
96 reg = <0 0x87f00000 0 0x100000>;
97 no-map;
98 };
99
100 ele_reserved: ele-reserved@87de0000 {
101 compatible = "shared-dma-pool";
102 reg = <0 0x87de0000 0 0x100000>;
103 no-map;
104 };
105 };
106};
107
108/* Use external instead of internal RTC*/
109&bbnsm_rtc {
110 status = "disabled";
111};
112
113&eqos {
114 mdio {
115 ethphy1: ethernet-phy@5 {
116 compatible = "ethernet-phy-ieee802.3-c22";
117 reg = <5>;
118 qca,disable-smarteee;
119 eee-broken-1000t;
120 reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
121 reset-assert-us = <10000>;
122 reset-deassert-us = <20000>;
123 vddio-supply = <&vddio1>;
124
125 vddio1: vddio-regulator {
126 regulator-min-microvolt = <1800000>;
127 regulator-max-microvolt = <1800000>;
128 };
129 };
130 };
131};
132
133&fec {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_fec>;
136 phy-mode = "rgmii";
137 phy-handle = <&ethphy1>;
138 phy-supply = <&reg_fec_phy>;
139 status = "okay";
140};
141
142&flexcan1 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_flexcan1>;
145 status = "okay";
146};
147
148&iomuxc {
149 pinctrl_fec: fecgrp {
150 fsl,pins = <
151 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
152 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
153 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
154 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
155 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
156 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
157 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
158 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
159 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
160 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
161 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
162 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
163 >;
164 };
165
166 pinctrl_flexcan1: flexcan1grp {
167 fsl,pins = <
168 MX93_PAD_PDM_CLK__CAN1_TX 0x139e
169 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
170 >;
171 };
172
173 pinctrl_lpi2c1: lpi2c1grp {
174 fsl,pins = <
175 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
176 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
177 >;
178 };
179
180 pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
181 fsl,pins = <
182 MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e
183 MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
184 >;
185 };
186
187 pinctrl_lpi2c5: lpi2c5grp {
188 fsl,pins = <
189 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
190 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
191 >;
192 };
193
194 pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
195 fsl,pins = <
196 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
197 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
198 >;
199 };
200
201 pinctrl_pca9534: pca9534grp {
202 fsl,pins = <
203 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
204 >;
205 };
206
207 pinctrl_uart1: uart1grp {
208 fsl,pins = <
209 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
210 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
211 >;
212 };
213
214 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
215 fsl,pins = <
216 MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e
217 >;
218 };
219
220 pinctrl_usdhc2: usdhc2grp {
221 fsl,pins = <
222 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
223 MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
224 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
225 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
226 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
227 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
228 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
229 >;
230 };
231
232 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
233 fsl,pins = <
234 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
235 >;
236 };
237};
238
239&lpi2c1 {
240 clock-frequency = <400000>;
241 pinctrl-names = "default", "sleep", "gpio";
242 pinctrl-0 = <&pinctrl_lpi2c1>;
243 pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
244 pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
245 scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
246 sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
247 status = "okay";
248
249 /* DS1337 RTC module */
250 rtc@68 {
251 compatible = "dallas,ds1337";
252 reg = <0x68>;
253 };
254};
255
256&lpi2c5 {
257 clock-frequency = <400000>;
258 pinctrl-names = "default", "sleep", "gpio";
259 pinctrl-0 = <&pinctrl_lpi2c5>;
260 pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
261 pinctrl-2 = <&pinctrl_lpi2c5_gpio>;
262 scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
263 sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
264 status = "okay";
265
266 pca9534: gpio@20 {
267 compatible = "nxp,pca9534";
268 reg = <0x20>;
269 gpio-controller;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_pca9534>;
272 interrupt-parent = <&gpio3>;
273 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
274 #gpio-cells = <2>;
275 wakeup-source;
276 };
277};
278
279/* Console */
280&lpuart1 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_uart1>;
283 clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
284 clock-names = "ipg", "per";
285 status = "okay";
286};
287
Mathieu Othacehe8194bc42024-02-20 11:35:03 +0100[diff] [blame]288&usbotg1 {
289 dr_mode = "otg";
290 hnp-disable;
291 srp-disable;
292 adp-disable;
293 disable-over-current;
294 status = "okay";
295};
296
297&usbotg2 {
298 dr_mode = "host";
299 hnp-disable;
300 srp-disable;
301 adp-disable;
302 disable-over-current;
303 status = "okay";
304};
305
Mathieu Othacehe2415f1d2023-12-29 11:55:23 +0100[diff] [blame]306/* SD */
307&usdhc2 {
308 pinctrl-names = "default", "state_100mhz", "state_200mhz";
309 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
310 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
311 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
312 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
313 vmmc-supply = <&reg_usdhc2_vmmc>;
314 bus-width = <4>;
315 status = "okay";
316 no-sdio;
317 no-mmc;
318};
319
320/* Watchdog */
321&wdog3 {
322 status = "okay";
323};