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wdenk041b1de2002-09-07 21:30:09 +00001/* originally from linux source.
2 * removed the dependencies on CONFIG_ values
3 * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
4 * Modified By Rob Taylor, Flying Pig Systems, 2000
5 */
6
7#ifndef _PPC_IO_H
8#define _PPC_IO_H
9
wdenk041b1de2002-09-07 21:30:09 +000010#include <asm/byteorder.h>
11
Kumar Gala64dcf472008-12-16 14:59:21 -060012#ifdef CONFIG_ADDR_MAP
Bin Meng39d49a82021-02-25 17:22:37 +080013#include <asm/global_data.h>
Kumar Gala64dcf472008-12-16 14:59:21 -060014#include <addr_map.h>
Bin Meng39d49a82021-02-25 17:22:37 +080015
16DECLARE_GLOBAL_DATA_PTR;
Kumar Gala64dcf472008-12-16 14:59:21 -060017#endif
18
wdenk041b1de2002-09-07 21:30:09 +000019#define SIO_CONFIG_RA 0x398
20#define SIO_CONFIG_RD 0x399
21
Heiko Schocher2559e0f2007-08-28 17:39:14 +020022#ifndef _IO_BASE
23#define _IO_BASE 0
24#endif
wdenk041b1de2002-09-07 21:30:09 +000025
26#define readb(addr) in_8((volatile u8 *)(addr))
27#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
28#if !defined(__BIG_ENDIAN)
29#define readw(addr) (*(volatile u16 *) (addr))
30#define readl(addr) (*(volatile u32 *) (addr))
31#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
32#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
33#else
34#define readw(addr) in_le16((volatile u16 *)(addr))
35#define readl(addr) in_le32((volatile u32 *)(addr))
36#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
37#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
38#endif
39
40/*
41 * The insw/outsw/insl/outsl macros don't do byte-swapping.
42 * They are only used in practice for transferring buffers which
43 * are arrays of bytes, and byte-swapping is not appropriate in
44 * that case. - paulus
45 */
46#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
47#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
48#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
49#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
50#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
51#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
52
53#define inb(port) in_8((u8 *)((port)+_IO_BASE))
54#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
55#if !defined(__BIG_ENDIAN)
56#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
57#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
58#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
59#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
60#else
61#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
62#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
63#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
64#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
65#endif
66
67#define inb_p(port) in_8((u8 *)((port)+_IO_BASE))
68#define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
69#define inw_p(port) in_le16((u16 *)((port)+_IO_BASE))
70#define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
71#define inl_p(port) in_le32((u32 *)((port)+_IO_BASE))
72#define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
73
74extern void _insb(volatile u8 *port, void *buf, int ns);
75extern void _outsb(volatile u8 *port, const void *buf, int ns);
76extern void _insw(volatile u16 *port, void *buf, int ns);
77extern void _outsw(volatile u16 *port, const void *buf, int ns);
78extern void _insl(volatile u32 *port, void *buf, int nl);
79extern void _outsl(volatile u32 *port, const void *buf, int nl);
80extern void _insw_ns(volatile u16 *port, void *buf, int ns);
81extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
82extern void _insl_ns(volatile u32 *port, void *buf, int nl);
83extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
84
85/*
86 * The *_ns versions below don't do byte-swapping.
87 * Neither do the standard versions now, these are just here
88 * for older code.
89 */
90#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
91#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
92#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
93#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
94
wdenk041b1de2002-09-07 21:30:09 +000095#define IO_SPACE_LIMIT ~0
96
Christophe Leroy9a77a0b2023-05-05 07:24:16 +020097#define memset_io(a,b,c) memset((void __force *)(a),(b),(c))
98#define memcpy_fromio(a,b,c) memcpy((a),(void __force *)(b),(c))
99#define memcpy_toio(a,b,c) memcpy((void __force *)(a),(b),(c))
wdenk041b1de2002-09-07 21:30:09 +0000100
101/*
102 * Enforce In-order Execution of I/O:
103 * Acts as a barrier to ensure all previous I/O accesses have
104 * completed before any further ones are issued.
105 */
Haiying Wangc123a382007-02-21 16:52:31 +0100106static inline void eieio(void)
107{
108 __asm__ __volatile__ ("eieio" : : : "memory");
109}
110
111static inline void sync(void)
112{
113 __asm__ __volatile__ ("sync" : : : "memory");
114}
wdenk041b1de2002-09-07 21:30:09 +0000115
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200116static inline void isync(void)
117{
118 __asm__ __volatile__ ("isync" : : : "memory");
119}
120
wdenk041b1de2002-09-07 21:30:09 +0000121/* Enforce in-order execution of data I/O.
122 * No distinction between read/write on PPC; use eieio for all three.
123 */
124#define iobarrier_rw() eieio()
125#define iobarrier_r() eieio()
126#define iobarrier_w() eieio()
127
York Sun157e72d2014-06-23 15:36:44 -0700128#define mb() sync()
129#define isb() isync()
130
wdenk041b1de2002-09-07 21:30:09 +0000131/*
Haavard Skinnemoen47f60852007-12-13 12:56:31 +0100132 * Non ordered and non-swapping "raw" accessors
133 */
Haavard Skinnemoen47f60852007-12-13 12:56:31 +0100134#define PCI_FIX_ADDR(addr) (addr)
135
136static inline unsigned char __raw_readb(const volatile void __iomem *addr)
137{
138 return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
139}
Igor Prusov3caad582023-11-14 14:02:52 +0300140#define __raw_readb __raw_readb
141
Haavard Skinnemoen47f60852007-12-13 12:56:31 +0100142static inline unsigned short __raw_readw(const volatile void __iomem *addr)
143{
144 return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
145}
Igor Prusov3caad582023-11-14 14:02:52 +0300146#define __raw_readw __raw_readw
147
Haavard Skinnemoen47f60852007-12-13 12:56:31 +0100148static inline unsigned int __raw_readl(const volatile void __iomem *addr)
149{
150 return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
151}
Igor Prusov3caad582023-11-14 14:02:52 +0300152#define __raw_readl __raw_readl
153
Haavard Skinnemoen47f60852007-12-13 12:56:31 +0100154static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
155{
156 *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
157}
Igor Prusov3caad582023-11-14 14:02:52 +0300158#define __raw_writeb __raw_writeb
159
Haavard Skinnemoen47f60852007-12-13 12:56:31 +0100160static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
161{
162 *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
163}
Igor Prusov3caad582023-11-14 14:02:52 +0300164#define __raw_writew __raw_writew
165
Haavard Skinnemoen47f60852007-12-13 12:56:31 +0100166static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
167{
168 *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
169}
Igor Prusov3caad582023-11-14 14:02:52 +0300170#define __raw_writel __raw_writel
Haavard Skinnemoen47f60852007-12-13 12:56:31 +0100171
172/*
wdenk041b1de2002-09-07 21:30:09 +0000173 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200174 *
175 * Read operations have additional twi & isync to make sure the read
176 * is actually performed (i.e. the data has come back) before we start
177 * executing any following instructions.
wdenk041b1de2002-09-07 21:30:09 +0000178 */
Måns Rullgård4dc39702015-11-06 12:44:01 +0000179static inline u8 in_8(const volatile unsigned char __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000180{
Prabhakar Kushwaha79e052a2012-04-10 22:48:59 +0000181 u8 ret;
wdenk041b1de2002-09-07 21:30:09 +0000182
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200183 __asm__ __volatile__(
184 "sync; lbz%U1%X1 %0,%1;\n"
185 "twi 0,%0,0;\n"
186 "isync" : "=r" (ret) : "m" (*addr));
187 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000188}
189
Måns Rullgård4dc39702015-11-06 12:44:01 +0000190static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
wdenk041b1de2002-09-07 21:30:09 +0000191{
Timur Tabi451ee1b2010-12-03 09:03:46 +0000192 __asm__ __volatile__("sync;\n"
193 "stb%U0%X0 %1,%0;\n"
194 : "=m" (*addr)
195 : "r" (val));
wdenk041b1de2002-09-07 21:30:09 +0000196}
197
Måns Rullgård4dc39702015-11-06 12:44:01 +0000198static inline u16 in_le16(const volatile unsigned short __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000199{
Prabhakar Kushwaha79e052a2012-04-10 22:48:59 +0000200 u16 ret;
wdenk041b1de2002-09-07 21:30:09 +0000201
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200202 __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
203 "twi 0,%0,0;\n"
204 "isync" : "=r" (ret) :
205 "r" (addr), "m" (*addr));
206 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000207}
208
Måns Rullgård4dc39702015-11-06 12:44:01 +0000209static inline u16 in_be16(const volatile unsigned short __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000210{
Prabhakar Kushwaha79e052a2012-04-10 22:48:59 +0000211 u16 ret;
wdenk041b1de2002-09-07 21:30:09 +0000212
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200213 __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
214 "twi 0,%0,0;\n"
215 "isync" : "=r" (ret) : "m" (*addr));
216 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000217}
218
Måns Rullgård4dc39702015-11-06 12:44:01 +0000219static inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
wdenk041b1de2002-09-07 21:30:09 +0000220{
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200221 __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
222 "r" (val), "r" (addr));
wdenk041b1de2002-09-07 21:30:09 +0000223}
224
Måns Rullgård4dc39702015-11-06 12:44:01 +0000225static inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
wdenk041b1de2002-09-07 21:30:09 +0000226{
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200227 __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
wdenk041b1de2002-09-07 21:30:09 +0000228}
229
Måns Rullgård4dc39702015-11-06 12:44:01 +0000230static inline u32 in_le32(const volatile unsigned __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000231{
Prabhakar Kushwaha79e052a2012-04-10 22:48:59 +0000232 u32 ret;
wdenk041b1de2002-09-07 21:30:09 +0000233
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200234 __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
235 "twi 0,%0,0;\n"
236 "isync" : "=r" (ret) :
237 "r" (addr), "m" (*addr));
238 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000239}
240
Måns Rullgård4dc39702015-11-06 12:44:01 +0000241static inline u32 in_be32(const volatile unsigned __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000242{
Prabhakar Kushwaha79e052a2012-04-10 22:48:59 +0000243 u32 ret;
wdenk041b1de2002-09-07 21:30:09 +0000244
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200245 __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
246 "twi 0,%0,0;\n"
247 "isync" : "=r" (ret) : "m" (*addr));
248 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000249}
250
Måns Rullgård4dc39702015-11-06 12:44:01 +0000251static inline void out_le32(volatile unsigned __iomem *addr, u32 val)
wdenk041b1de2002-09-07 21:30:09 +0000252{
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200253 __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
254 "r" (val), "r" (addr));
wdenk041b1de2002-09-07 21:30:09 +0000255}
256
Måns Rullgård4dc39702015-11-06 12:44:01 +0000257static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
wdenk041b1de2002-09-07 21:30:09 +0000258{
Stefan Roeseb0fb4522007-06-01 15:16:58 +0200259 __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
wdenk041b1de2002-09-07 21:30:09 +0000260}
261
Wolfgang Grandegger8b941772008-06-04 12:45:22 +0200262/* Clear and set bits in one shot. These macros can be used to clear and
263 * set multiple bits in a register using a single call. These macros can
264 * also be used to set a multiple-bit bit pattern using a mask, by
265 * specifying the mask in the 'clear' parameter and the new bit pattern
266 * in the 'set' parameter.
267 */
268
269#define clrbits(type, addr, clear) \
270 out_##type((addr), in_##type(addr) & ~(clear))
271
272#define setbits(type, addr, set) \
273 out_##type((addr), in_##type(addr) | (set))
274
275#define clrsetbits(type, addr, clear, set) \
276 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
277
278#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
279#define setbits_be32(addr, set) setbits(be32, addr, set)
280#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
281
282#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
283#define setbits_le32(addr, set) setbits(le32, addr, set)
284#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
285
286#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
287#define setbits_be16(addr, set) setbits(be16, addr, set)
288#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
289
290#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
291#define setbits_le16(addr, set) setbits(le16, addr, set)
292#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
293
294#define clrbits_8(addr, clear) clrbits(8, addr, clear)
295#define setbits_8(addr, set) setbits(8, addr, set)
296#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
297
Mario Sixf3c66422018-08-06 10:23:31 +0200298#define readb_be(addr) \
299 __raw_readb((__force unsigned *)(addr))
300#define readw_be(addr) \
301 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
302#define readl_be(addr) \
303 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
304#define readq_be(addr) \
305 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
306
307#define writeb_be(val, addr) \
308 __raw_writeb((val), (__force unsigned *)(addr))
309#define writew_be(val, addr) \
310 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
311#define writel_be(val, addr) \
312 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
313#define writeq_be(val, addr) \
314 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
315
Paul Burtona846d112017-09-14 15:05:12 -0700316static inline void *phys_to_virt(phys_addr_t paddr)
Haavard Skinnemoenf9855512007-12-13 12:56:33 +0100317{
Kumar Gala64dcf472008-12-16 14:59:21 -0600318#ifdef CONFIG_ADDR_MAP
Bin Meng39d49a82021-02-25 17:22:37 +0800319 if (gd->flags & GD_FLG_RELOC)
320 return addrmap_phys_to_virt(paddr);
Kumar Gala64dcf472008-12-16 14:59:21 -0600321#endif
Bin Meng39d49a82021-02-25 17:22:37 +0800322 return (void *)((unsigned long)paddr);
Haavard Skinnemoenf9855512007-12-13 12:56:33 +0100323}
Paul Burtona846d112017-09-14 15:05:12 -0700324#define phys_to_virt phys_to_virt
Haavard Skinnemoenf9855512007-12-13 12:56:33 +0100325
Kumar Gala9364a672008-12-13 17:20:27 -0600326static inline phys_addr_t virt_to_phys(void * vaddr)
327{
Kumar Gala64dcf472008-12-16 14:59:21 -0600328#ifdef CONFIG_ADDR_MAP
Bin Meng39d49a82021-02-25 17:22:37 +0800329 if (gd->flags & GD_FLG_RELOC)
330 return addrmap_virt_to_phys(vaddr);
Kumar Gala64dcf472008-12-16 14:59:21 -0600331#endif
Bin Meng39d49a82021-02-25 17:22:37 +0800332 return (phys_addr_t)((unsigned long)vaddr);
Kumar Gala9364a672008-12-13 17:20:27 -0600333}
Paul Burtona846d112017-09-14 15:05:12 -0700334#define virt_to_phys virt_to_phys
335
336#include <asm-generic/io.h>
Kumar Gala9364a672008-12-13 17:20:27 -0600337
wdenk041b1de2002-09-07 21:30:09 +0000338#endif