Stefan Roese | e373c5f | 2009-01-21 17:24:49 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation; either version 2 of |
| 7 | * the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 17 | * MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #include <common.h> |
| 21 | #include <asm/io.h> |
| 22 | #include "vct.h" |
| 23 | |
| 24 | /* |
| 25 | * Find out to which of the 2 gpio modules the pin specified in the |
| 26 | * argument belongs: |
| 27 | * GPIO_MODULE yields 0 for pins 0 to 31, |
| 28 | * 1 for pins 32 to 63 |
| 29 | */ |
| 30 | #define GPIO_MODULE(pin) ((pin) >> 5) |
| 31 | |
| 32 | /* |
| 33 | * Bit position within a 32-bit peripheral register (where every |
| 34 | * bit is one bitslice) |
| 35 | */ |
| 36 | #define MASK(pin) (1 << ((pin) & 0x1F)) |
| 37 | #define BASE_ADDR(mod) module_base[mod] |
| 38 | |
| 39 | /* |
| 40 | * Lookup table for transforming gpio module number 0 to 2 to |
| 41 | * address offsets |
| 42 | */ |
| 43 | static u32 module_base[] = { |
| 44 | GPIO1_BASE, |
| 45 | GPIO2_BASE |
| 46 | }; |
| 47 | |
| 48 | static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask) |
| 49 | { |
| 50 | reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask); |
| 51 | } |
| 52 | |
| 53 | int vct_gpio_dir(int pin, int dir) |
| 54 | { |
| 55 | u32 gpio_base; |
| 56 | |
| 57 | gpio_base = BASE_ADDR(GPIO_MODULE(pin)); |
| 58 | |
| 59 | if (dir == 0) |
| 60 | clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); |
| 61 | else |
| 62 | clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); |
| 63 | |
| 64 | return 0; |
| 65 | } |
| 66 | |
| 67 | void vct_gpio_set(int pin, int val) |
| 68 | { |
| 69 | u32 gpio_base; |
| 70 | |
| 71 | gpio_base = BASE_ADDR(GPIO_MODULE(pin)); |
| 72 | |
| 73 | if (val == 0) |
| 74 | clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); |
| 75 | else |
| 76 | clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin)); |
| 77 | } |
| 78 | |
| 79 | int vct_gpio_get(int pin) |
| 80 | { |
| 81 | u32 gpio_base; |
| 82 | u32 value; |
| 83 | |
| 84 | gpio_base = BASE_ADDR(GPIO_MODULE(pin)); |
| 85 | value = reg_read(GPIO_EXT_PORTA(gpio_base)); |
| 86 | |
| 87 | return ((value & MASK(pin)) ? 1 : 0); |
| 88 | } |