Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2022 Marek Vasut <marex@denx.de> |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <asm/arch/clock.h> |
| 8 | #include <asm/arch/sys_proto.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <dm.h> |
| 11 | #include <env.h> |
| 12 | #include <env_internal.h> |
| 13 | #include <i2c_eeprom.h> |
| 14 | #include <malloc.h> |
| 15 | #include <net.h> |
| 16 | #include <miiphy.h> |
| 17 | |
| 18 | #include "lpddr4_timing.h" |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 19 | #include "../common/dh_common.h" |
| 20 | #include "../common/dh_imx.h" |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | int mach_cpu_init(void) |
| 25 | { |
| 26 | icache_enable(); |
| 27 | return 0; |
| 28 | } |
| 29 | |
| 30 | int board_phys_sdram_size(phys_size_t *size) |
| 31 | { |
| 32 | const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 }; |
| 33 | u8 memcfg = dh_get_memcfg(); |
| 34 | |
| 35 | *size = (u64)memsz[memcfg] << 20ULL; |
| 36 | |
| 37 | return 0; |
| 38 | } |
| 39 | |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 40 | static void setup_eqos(void) |
| 41 | { |
| 42 | struct iomuxc_gpr_base_regs *gpr = |
| 43 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
| 44 | |
| 45 | /* Set INTF as RGMII, enable RGMII TXC clock. */ |
| 46 | clrsetbits_le32(&gpr->gpr[1], |
| 47 | IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); |
| 48 | setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); |
| 49 | |
| 50 | set_clk_eqos(ENET_125MHZ); |
| 51 | } |
| 52 | |
| 53 | static void setup_fec(void) |
| 54 | { |
| 55 | struct iomuxc_gpr_base_regs *gpr = |
| 56 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
| 57 | |
| 58 | /* Enable RGMII TX clk output. */ |
| 59 | setbits_le32(&gpr->gpr[1], BIT(22)); |
| 60 | |
| 61 | set_clk_enet(ENET_125MHZ); |
| 62 | } |
| 63 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 64 | static int dh_imx8_setup_ethaddr(void) |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 65 | { |
| 66 | unsigned char enetaddr[6]; |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 67 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 68 | if (dh_mac_is_in_env("ethaddr")) |
| 69 | return 0; |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 70 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 71 | if (!dh_imx_get_mac_from_fuse(enetaddr)) |
| 72 | goto out; |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 73 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 74 | if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0")) |
| 75 | goto out; |
| 76 | |
| 77 | return -ENXIO; |
| 78 | |
| 79 | out: |
| 80 | return eth_env_set_enetaddr("ethaddr", enetaddr); |
| 81 | } |
| 82 | |
| 83 | static int dh_imx8_setup_eth1addr(void) |
| 84 | { |
| 85 | unsigned char enetaddr[6]; |
| 86 | |
| 87 | if (dh_mac_is_in_env("eth1addr")) |
| 88 | return 0; |
| 89 | |
| 90 | if (!dh_imx_get_mac_from_fuse(enetaddr)) |
| 91 | goto increment_out; |
| 92 | |
| 93 | if (!dh_get_mac_from_eeprom(enetaddr, "eeprom1")) |
| 94 | goto out; |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 95 | |
| 96 | /* |
| 97 | * Populate second ethernet MAC from first ethernet EEPROM with MAC |
| 98 | * address LSByte incremented by 1. This is only used on SoMs without |
| 99 | * second ethernet EEPROM, i.e. early prototypes. |
| 100 | */ |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 101 | if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0")) |
| 102 | goto increment_out; |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 103 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 104 | return -ENXIO; |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 105 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 106 | increment_out: |
| 107 | enetaddr[5]++; |
| 108 | |
| 109 | out: |
| 110 | return eth_env_set_enetaddr("eth1addr", enetaddr); |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 111 | } |
| 112 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 113 | int dh_setup_mac_address(void) |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 114 | { |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 115 | int ret; |
| 116 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 117 | ret = dh_imx8_setup_ethaddr(); |
| 118 | if (ret) |
| 119 | printf("%s: Unable to setup ethaddr! ret = %d\n", __func__, ret); |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 120 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 121 | ret = dh_imx8_setup_eth1addr(); |
| 122 | if (ret) |
| 123 | printf("%s: Unable to setup eth1addr! ret = %d\n", __func__, ret); |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 124 | |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 125 | return ret; |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | int board_init(void) |
| 129 | { |
| 130 | setup_eqos(); |
| 131 | setup_fec(); |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 132 | return 0; |
| 133 | } |
| 134 | |
| 135 | int board_late_init(void) |
| 136 | { |
Philip Oberfichtner | d24f1de | 2022-07-26 15:04:52 +0200 | [diff] [blame] | 137 | dh_setup_mac_address(); |
Marek Vasut | f670cd7 | 2022-05-21 16:56:26 +0200 | [diff] [blame] | 138 | return 0; |
| 139 | } |
| 140 | |
| 141 | enum env_location env_get_location(enum env_operation op, int prio) |
| 142 | { |
| 143 | return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH; |
| 144 | } |