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git01.mediatek.com / filogic / uboot / 9fa68514eb9dfaeb6c8afac100ac7b1f786cb52d / . / drivers / rtc / max6900.c
blob: e03a87f94da9d401ca3e96b3c2beabc6ee8befa6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]2/*
3 * (C) Copyright 2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]5 */
6
7/*
8 * Date & Time support for MAXIM MAX6900 RTC
9 */
10
11/* #define DEBUG */
12
13#include <common.h>
14#include <command.h>
15#include <rtc.h>
16#include <i2c.h>
Simon Glassdbd79542020-05-10 11:40:11 -0600[diff] [blame]17#include <linux/delay.h>
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]18
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]19#ifndef CFG_SYS_I2C_RTC_ADDR
20#define CFG_SYS_I2C_RTC_ADDR 0x50
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]21#endif
22
23/* ------------------------------------------------------------------------- */
24
25static uchar rtc_read (uchar reg)
26{
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]27 return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]28}
29
30static void rtc_write (uchar reg, uchar val)
31{
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]32 i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]33 udelay(2500);
34}
35
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]36/* ------------------------------------------------------------------------- */
37
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300[diff] [blame]38int rtc_get (struct rtc_time *tmp)
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]39{
40 uchar sec, min, hour, mday, wday, mon, cent, year;
41 int retry = 1;
42
43 do {
44 sec = rtc_read (0x80);
45 min = rtc_read (0x82);
46 hour = rtc_read (0x84);
47 mday = rtc_read (0x86);
48 mon = rtc_read (0x88);
49 wday = rtc_read (0x8a);
50 year = rtc_read (0x8c);
51 cent = rtc_read (0x92);
52 /*
53 * Check for seconds rollover
54 */
55 if ((sec != 59) || (rtc_read(0x80) == sec)){
56 retry = 0;
57 }
58 } while (retry);
59
60 debug ( "Get RTC year: %02x mon: %02x cent: %02x mday: %02x wday: %02x "
61 "hr: %02x min: %02x sec: %02x\n",
62 year, mon, cent, mday, wday,
63 hour, min, sec );
64
65 tmp->tm_sec = bcd2bin (sec & 0x7F);
66 tmp->tm_min = bcd2bin (min & 0x7F);
67 tmp->tm_hour = bcd2bin (hour & 0x3F);
68 tmp->tm_mday = bcd2bin (mday & 0x3F);
69 tmp->tm_mon = bcd2bin (mon & 0x1F);
70 tmp->tm_year = bcd2bin (year) + bcd2bin(cent) * 100;
71 tmp->tm_wday = bcd2bin (wday & 0x07);
72 tmp->tm_yday = 0;
73 tmp->tm_isdst= 0;
74
75 debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
76 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
77 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300[diff] [blame]78
79 return 0;
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]80}
81
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200[diff] [blame]82int rtc_set (struct rtc_time *tmp)
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]83{
84
85 debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
86 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
87 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
88
89 rtc_write (0x9E, 0x00);
90 rtc_write (0x80, 0); /* Clear seconds to ensure no rollover */
91 rtc_write (0x92, bin2bcd(tmp->tm_year / 100));
92 rtc_write (0x8c, bin2bcd(tmp->tm_year % 100));
93 rtc_write (0x8a, bin2bcd(tmp->tm_wday));
94 rtc_write (0x88, bin2bcd(tmp->tm_mon));
95 rtc_write (0x86, bin2bcd(tmp->tm_mday));
96 rtc_write (0x84, bin2bcd(tmp->tm_hour));
97 rtc_write (0x82, bin2bcd(tmp->tm_min ));
98 rtc_write (0x80, bin2bcd(tmp->tm_sec ));
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200[diff] [blame]99
100 return 0;
wdenkaeba06f2004-06-09 17:34:58 +0000[diff] [blame]101}
102
103void rtc_reset (void)
104{
105}