Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 1 | # |
| 2 | # Multifunction miscellaneous devices |
| 3 | # |
| 4 | |
| 5 | menu "Multifunction device drivers" |
| 6 | |
Thomas Chou | b1ed686 | 2015-10-07 20:20:51 +0800 | [diff] [blame] | 7 | config MISC |
| 8 | bool "Enable Driver Model for Misc drivers" |
| 9 | depends on DM |
| 10 | help |
| 11 | Enable driver model for miscellaneous devices. This class is |
| 12 | used only for those do not fit other more general classes. A |
| 13 | set of generic read, write and ioctl methods may be used to |
| 14 | access the device. |
| 15 | |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 16 | config SPL_MISC |
| 17 | bool "Enable Driver Model for Misc drivers in SPL" |
| 18 | depends on SPL_DM |
| 19 | help |
| 20 | Enable driver model for miscellaneous devices. This class is |
| 21 | used only for those do not fit other more general classes. A |
| 22 | set of generic read, write and ioctl methods may be used to |
| 23 | access the device. |
| 24 | |
| 25 | config TPL_MISC |
| 26 | bool "Enable Driver Model for Misc drivers in TPL" |
| 27 | depends on TPL_DM |
| 28 | help |
| 29 | Enable driver model for miscellaneous devices. This class is |
| 30 | used only for those do not fit other more general classes. A |
| 31 | set of generic read, write and ioctl methods may be used to |
| 32 | access the device. |
| 33 | |
Thomas Chou | 36b9c9a | 2015-10-14 08:43:31 +0800 | [diff] [blame] | 34 | config ALTERA_SYSID |
| 35 | bool "Altera Sysid support" |
| 36 | depends on MISC |
| 37 | help |
| 38 | Select this to enable a sysid for Altera devices. Please find |
| 39 | details on the "Embedded Peripherals IP User Guide" of Altera. |
| 40 | |
Marek BehĂșn | ef2b6b1 | 2017-06-09 19:28:44 +0200 | [diff] [blame] | 41 | config ATSHA204A |
| 42 | bool "Support for Atmel ATSHA204A module" |
| 43 | depends on MISC |
| 44 | help |
| 45 | Enable support for I2C connected Atmel's ATSHA204A |
| 46 | CryptoAuthentication module found for example on the Turris Omnia |
| 47 | board. |
| 48 | |
Philipp Tomsich | fcc1d63 | 2017-05-05 19:21:38 +0200 | [diff] [blame] | 49 | config ROCKCHIP_EFUSE |
| 50 | bool "Rockchip e-fuse support" |
| 51 | depends on MISC |
| 52 | help |
| 53 | Enable (read-only) access for the e-fuse block found in Rockchip |
| 54 | SoCs: accesses can either be made using byte addressing and a length |
| 55 | or through child-nodes that are generated based on the e-fuse map |
| 56 | retrieved from the DTS. |
| 57 | |
| 58 | This driver currently supports the RK3399 only, but can easily be |
| 59 | extended (by porting the read function from the Linux kernel sources) |
| 60 | to support other recent Rockchip devices. |
| 61 | |
Finley Xiao | 20d52a0 | 2019-09-25 17:57:49 +0200 | [diff] [blame] | 62 | config ROCKCHIP_OTP |
| 63 | bool "Rockchip OTP Support" |
| 64 | depends on MISC |
| 65 | help |
| 66 | Enable (read-only) access for the one-time-programmable memory block |
| 67 | found in Rockchip SoCs: accesses can either be made using byte |
| 68 | addressing and a length or through child-nodes that are generated |
| 69 | based on the e-fuse map retrieved from the DTS. |
| 70 | |
Pragnesh Patel | 6e9661f | 2020-05-29 11:33:21 +0530 | [diff] [blame] | 71 | config SIFIVE_OTP |
| 72 | bool "SiFive eMemory OTP driver" |
| 73 | depends on MISC |
| 74 | help |
| 75 | Enable support for reading and writing the eMemory OTP on the |
| 76 | SiFive SoCs. |
| 77 | |
Liviu Dudau | 688db7f | 2018-09-28 13:43:31 +0100 | [diff] [blame] | 78 | config VEXPRESS_CONFIG |
| 79 | bool "Enable support for Arm Versatile Express config bus" |
| 80 | depends on MISC |
| 81 | help |
| 82 | If you say Y here, you will get support for accessing the |
| 83 | configuration bus on the Arm Versatile Express boards via |
| 84 | a sysreg driver. |
| 85 | |
Simon Glass | 5b79bb2 | 2015-02-13 12:20:47 -0700 | [diff] [blame] | 86 | config CMD_CROS_EC |
| 87 | bool "Enable crosec command" |
| 88 | depends on CROS_EC |
| 89 | help |
| 90 | Enable command-line access to the Chrome OS EC (Embedded |
| 91 | Controller). This provides the 'crosec' command which has |
| 92 | a number of sub-commands for performing EC tasks such as |
| 93 | updating its flash, accessing a small saved context area |
| 94 | and talking to the I2C bus behind the EC (if there is one). |
| 95 | |
| 96 | config CROS_EC |
| 97 | bool "Enable Chrome OS EC" |
| 98 | help |
| 99 | Enable access to the Chrome OS EC. This is a separate |
| 100 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 101 | provides access to the keyboard, some internal storage and may |
| 102 | control access to the battery and main PMIC depending on the |
| 103 | device. You can use the 'crosec' command to access it. |
| 104 | |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 105 | config SPL_CROS_EC |
| 106 | bool "Enable Chrome OS EC in SPL" |
Adam Ford | ac4d80e | 2019-08-24 13:50:34 -0500 | [diff] [blame] | 107 | depends on SPL |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 108 | help |
| 109 | Enable access to the Chrome OS EC in SPL. This is a separate |
| 110 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 111 | provides access to the keyboard, some internal storage and may |
| 112 | control access to the battery and main PMIC depending on the |
| 113 | device. You can use the 'crosec' command to access it. |
| 114 | |
| 115 | config TPL_CROS_EC |
| 116 | bool "Enable Chrome OS EC in TPL" |
Adam Ford | ac4d80e | 2019-08-24 13:50:34 -0500 | [diff] [blame] | 117 | depends on TPL |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 118 | help |
| 119 | Enable access to the Chrome OS EC in TPL. This is a separate |
| 120 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 121 | provides access to the keyboard, some internal storage and may |
| 122 | control access to the battery and main PMIC depending on the |
| 123 | device. You can use the 'crosec' command to access it. |
| 124 | |
Simon Glass | 5b79bb2 | 2015-02-13 12:20:47 -0700 | [diff] [blame] | 125 | config CROS_EC_I2C |
| 126 | bool "Enable Chrome OS EC I2C driver" |
| 127 | depends on CROS_EC |
| 128 | help |
| 129 | Enable I2C access to the Chrome OS EC. This is used on older |
| 130 | ARM Chromebooks such as snow and spring before the standard bus |
| 131 | changed to SPI. The EC will accept commands across the I2C using |
| 132 | a special message protocol, and provide responses. |
| 133 | |
| 134 | config CROS_EC_LPC |
| 135 | bool "Enable Chrome OS EC LPC driver" |
| 136 | depends on CROS_EC |
| 137 | help |
| 138 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 139 | Chromebooks such as link and falco. The keyboard is provided |
| 140 | through a legacy port interface, so on x86 machines the main |
| 141 | function of the EC is power and thermal management. |
| 142 | |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 143 | config SPL_CROS_EC_LPC |
| 144 | bool "Enable Chrome OS EC LPC driver in SPL" |
| 145 | depends on CROS_EC |
| 146 | help |
| 147 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 148 | Chromebooks such as link and falco. The keyboard is provided |
| 149 | through a legacy port interface, so on x86 machines the main |
| 150 | function of the EC is power and thermal management. |
| 151 | |
| 152 | config TPL_CROS_EC_LPC |
| 153 | bool "Enable Chrome OS EC LPC driver in TPL" |
| 154 | depends on CROS_EC |
| 155 | help |
| 156 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 157 | Chromebooks such as link and falco. The keyboard is provided |
| 158 | through a legacy port interface, so on x86 machines the main |
| 159 | function of the EC is power and thermal management. |
| 160 | |
Simon Glass | c6e0669 | 2015-03-26 09:29:40 -0600 | [diff] [blame] | 161 | config CROS_EC_SANDBOX |
| 162 | bool "Enable Chrome OS EC sandbox driver" |
| 163 | depends on CROS_EC && SANDBOX |
| 164 | help |
| 165 | Enable a sandbox emulation of the Chrome OS EC. This supports |
| 166 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 167 | EC flash read/write/erase support and a few other things. It is |
| 168 | enough to perform a Chrome OS verified boot on sandbox. |
| 169 | |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 170 | config SPL_CROS_EC_SANDBOX |
| 171 | bool "Enable Chrome OS EC sandbox driver in SPL" |
| 172 | depends on SPL_CROS_EC && SANDBOX |
| 173 | help |
| 174 | Enable a sandbox emulation of the Chrome OS EC in SPL. This supports |
| 175 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 176 | EC flash read/write/erase support and a few other things. It is |
| 177 | enough to perform a Chrome OS verified boot on sandbox. |
| 178 | |
| 179 | config TPL_CROS_EC_SANDBOX |
| 180 | bool "Enable Chrome OS EC sandbox driver in TPL" |
| 181 | depends on TPL_CROS_EC && SANDBOX |
| 182 | help |
| 183 | Enable a sandbox emulation of the Chrome OS EC in TPL. This supports |
| 184 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 185 | EC flash read/write/erase support and a few other things. It is |
| 186 | enough to perform a Chrome OS verified boot on sandbox. |
| 187 | |
Simon Glass | 5b79bb2 | 2015-02-13 12:20:47 -0700 | [diff] [blame] | 188 | config CROS_EC_SPI |
| 189 | bool "Enable Chrome OS EC SPI driver" |
| 190 | depends on CROS_EC |
| 191 | help |
| 192 | Enable SPI access to the Chrome OS EC. This is used on newer |
| 193 | ARM Chromebooks such as pit, pi and nyan-big. The SPI interface |
| 194 | provides a faster and more robust interface than I2C but the bugs |
| 195 | are less interesting. |
| 196 | |
Simon Glass | 58ed322 | 2017-05-17 03:25:02 -0600 | [diff] [blame] | 197 | config DS4510 |
| 198 | bool "Enable support for DS4510 CPU supervisor" |
| 199 | help |
| 200 | Enable support for the Maxim DS4510 CPU supervisor. It has an |
| 201 | integrated 64-byte EEPROM, four programmable non-volatile I/O pins |
| 202 | and a configurable timer for the supervisor function. The device is |
| 203 | connected over I2C. |
| 204 | |
Peng Fan | fb6166a | 2015-08-26 15:41:33 +0800 | [diff] [blame] | 205 | config FSL_SEC_MON |
gaurav rana | 9aaea44 | 2015-02-27 09:44:22 +0530 | [diff] [blame] | 206 | bool "Enable FSL SEC_MON Driver" |
| 207 | help |
| 208 | Freescale Security Monitor block is responsible for monitoring |
| 209 | system states. |
| 210 | Security Monitor can be transitioned on any security failures, |
| 211 | like software violations or hardware security violations. |
Stefan Roese | 04b2275 | 2015-03-12 11:22:46 +0100 | [diff] [blame] | 212 | |
Simon Glass | ff418d9 | 2019-12-06 21:41:58 -0700 | [diff] [blame] | 213 | config IRQ |
| 214 | bool "Intel Interrupt controller" |
| 215 | depends on X86 || SANDBOX |
| 216 | help |
| 217 | This enables support for Intel interrupt controllers, including ITSS. |
| 218 | Some devices have extra features, such as Apollo Lake. The |
| 219 | device has its own uclass since there are several operations |
| 220 | involved. |
| 221 | |
Paul Burton | 738d8a8 | 2018-12-16 19:25:19 -0300 | [diff] [blame] | 222 | config JZ4780_EFUSE |
| 223 | bool "Ingenic JZ4780 eFUSE support" |
| 224 | depends on ARCH_JZ47XX |
| 225 | help |
| 226 | This selects support for the eFUSE on Ingenic JZ4780 SoCs. |
| 227 | |
Peng Fan | e187225 | 2015-08-27 14:49:05 +0800 | [diff] [blame] | 228 | config MXC_OCOTP |
| 229 | bool "Enable MXC OCOTP Driver" |
Peng Fan | c45a81a | 2019-07-22 01:24:55 +0000 | [diff] [blame] | 230 | depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 |
Marcel Ziswiler | f221314 | 2019-03-25 17:24:57 +0100 | [diff] [blame] | 231 | default y |
Peng Fan | e187225 | 2015-08-27 14:49:05 +0800 | [diff] [blame] | 232 | help |
| 233 | If you say Y here, you will get support for the One Time |
| 234 | Programmable memory pages that are stored on the some |
| 235 | Freescale i.MX processors. |
| 236 | |
Stefan Roese | 4a269f2 | 2016-07-19 07:45:46 +0200 | [diff] [blame] | 237 | config NUVOTON_NCT6102D |
| 238 | bool "Enable Nuvoton NCT6102D Super I/O driver" |
| 239 | help |
| 240 | If you say Y here, you will get support for the Nuvoton |
| 241 | NCT6102D Super I/O driver. This can be used to enable or |
| 242 | disable the legacy UART, the watchdog or other devices |
| 243 | in the Nuvoton Super IO chips on X86 platforms. |
| 244 | |
Simon Glass | 2ee1f6a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 245 | config P2SB |
| 246 | bool "Intel Primary-to-Sideband Bus" |
| 247 | depends on X86 || SANDBOX |
| 248 | help |
| 249 | This enables support for the Intel Primary-to-Sideband bus, |
| 250 | abbreviated to P2SB. The P2SB is used to access various peripherals |
| 251 | such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI |
| 252 | space. The space is segmented into different channels and peripherals |
| 253 | are accessed by device-specific means within those channels. Devices |
| 254 | should be added in the device tree as subnodes of the P2SB. A |
| 255 | Peripheral Channel Register? (PCR) API is provided to access those |
| 256 | devices - see pcr_readl(), etc. |
| 257 | |
| 258 | config SPL_P2SB |
| 259 | bool "Intel Primary-to-Sideband Bus in SPL" |
| 260 | depends on SPL && (X86 || SANDBOX) |
| 261 | help |
| 262 | The Primary-to-Sideband bus is used to access various peripherals |
| 263 | through memory-mapped I/O in a large chunk of PCI space. The space is |
| 264 | segmented into different channels and peripherals are accessed by |
| 265 | device-specific means within those channels. Devices should be added |
| 266 | in the device tree as subnodes of the p2sb. |
| 267 | |
| 268 | config TPL_P2SB |
| 269 | bool "Intel Primary-to-Sideband Bus in TPL" |
| 270 | depends on TPL && (X86 || SANDBOX) |
| 271 | help |
| 272 | The Primary-to-Sideband bus is used to access various peripherals |
| 273 | through memory-mapped I/O in a large chunk of PCI space. The space is |
| 274 | segmented into different channels and peripherals are accessed by |
| 275 | device-specific means within those channels. Devices should be added |
| 276 | in the device tree as subnodes of the p2sb. |
| 277 | |
Simon Glass | c979517 | 2016-01-21 19:43:31 -0700 | [diff] [blame] | 278 | config PWRSEQ |
| 279 | bool "Enable power-sequencing drivers" |
| 280 | depends on DM |
| 281 | help |
| 282 | Power-sequencing drivers provide support for controlling power for |
| 283 | devices. They are typically referenced by a phandle from another |
| 284 | device. When the device is started up, its power sequence can be |
| 285 | initiated. |
| 286 | |
| 287 | config SPL_PWRSEQ |
| 288 | bool "Enable power-sequencing drivers for SPL" |
| 289 | depends on PWRSEQ |
| 290 | help |
| 291 | Power-sequencing drivers provide support for controlling power for |
| 292 | devices. They are typically referenced by a phandle from another |
| 293 | device. When the device is started up, its power sequence can be |
| 294 | initiated. |
| 295 | |
Stefan Roese | 04b2275 | 2015-03-12 11:22:46 +0100 | [diff] [blame] | 296 | config PCA9551_LED |
| 297 | bool "Enable PCA9551 LED driver" |
| 298 | help |
| 299 | Enable driver for PCA9551 LED controller. This controller |
| 300 | is connected via I2C. So I2C needs to be enabled. |
| 301 | |
| 302 | config PCA9551_I2C_ADDR |
| 303 | hex "I2C address of PCA9551 LED controller" |
| 304 | depends on PCA9551_LED |
| 305 | default 0x60 |
| 306 | help |
| 307 | The I2C address of the PCA9551 LED controller. |
Simon Glass | 1400086 | 2015-06-23 15:39:13 -0600 | [diff] [blame] | 308 | |
Patrick Delaunay | 0c4656b | 2018-05-17 15:24:06 +0200 | [diff] [blame] | 309 | config STM32MP_FUSE |
| 310 | bool "Enable STM32MP fuse wrapper providing the fuse API" |
| 311 | depends on ARCH_STM32MP && MISC |
| 312 | default y if CMD_FUSE |
| 313 | help |
| 314 | If you say Y here, you will get support for the fuse API (OTP) |
| 315 | for STM32MP architecture. |
| 316 | This API is needed for CMD_FUSE. |
| 317 | |
Christophe Kerello | 275f706 | 2017-09-13 18:00:08 +0200 | [diff] [blame] | 318 | config STM32_RCC |
| 319 | bool "Enable RCC driver for the STM32 SoC's family" |
Trevor Woerner | 2bcc1ed | 2020-05-06 08:02:42 -0400 | [diff] [blame] | 320 | depends on (ARCH_STM32 || ARCH_STM32MP) && MISC |
Christophe Kerello | 275f706 | 2017-09-13 18:00:08 +0200 | [diff] [blame] | 321 | help |
| 322 | Enable the STM32 RCC driver. The RCC block (Reset and Clock Control |
| 323 | block) is responsible of the management of the clock and reset |
| 324 | generation. |
| 325 | This driver is similar to an MFD driver in the Linux kernel. |
| 326 | |
Stephen Warren | f641700 | 2016-09-13 10:45:57 -0600 | [diff] [blame] | 327 | config TEGRA_CAR |
| 328 | bool "Enable support for the Tegra CAR driver" |
| 329 | depends on TEGRA_NO_BPMP |
| 330 | help |
| 331 | The Tegra CAR (Clock and Reset Controller) is a HW module that |
| 332 | controls almost all clocks and resets in a Tegra SoC. |
| 333 | |
Stephen Warren | a214892 | 2016-08-08 09:41:34 -0600 | [diff] [blame] | 334 | config TEGRA186_BPMP |
| 335 | bool "Enable support for the Tegra186 BPMP driver" |
| 336 | depends on TEGRA186 |
| 337 | help |
| 338 | The Tegra BPMP (Boot and Power Management Processor) is a separate |
| 339 | auxiliary CPU embedded into Tegra to perform power management work, |
| 340 | and controls related features such as clocks, resets, power domains, |
| 341 | PMIC I2C bus, etc. This driver provides the core low-level |
| 342 | communication path by which feature-specific drivers (such as clock) |
| 343 | can make requests to the BPMP. This driver is similar to an MFD |
| 344 | driver in the Linux kernel. |
| 345 | |
Adam Ford | c8cdce7 | 2018-08-06 14:26:50 -0500 | [diff] [blame] | 346 | config TWL4030_LED |
| 347 | bool "Enable TWL4030 LED controller" |
| 348 | help |
| 349 | Enable this to add support for the TWL4030 LED controller. |
| 350 | |
Stefan Roese | ba019ed | 2016-01-19 14:05:10 +0100 | [diff] [blame] | 351 | config WINBOND_W83627 |
| 352 | bool "Enable Winbond Super I/O driver" |
| 353 | help |
| 354 | If you say Y here, you will get support for the Winbond |
| 355 | W83627 Super I/O driver. This can be used to enable the |
| 356 | legacy UART or other devices in the Winbond Super IO chips |
| 357 | on X86 platforms. |
| 358 | |
Miao Yan | 4fcd7f2 | 2016-05-22 19:37:14 -0700 | [diff] [blame] | 359 | config QFW |
| 360 | bool |
| 361 | help |
| 362 | Hidden option to enable QEMU fw_cfg interface. This will be selected by |
Miao Yan | 9210627 | 2016-05-22 19:37:17 -0700 | [diff] [blame] | 363 | either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. |
Miao Yan | 4fcd7f2 | 2016-05-22 19:37:14 -0700 | [diff] [blame] | 364 | |
mario.six@gdsys.cc | 7559ac4 | 2016-06-22 15:14:16 +0200 | [diff] [blame] | 365 | config I2C_EEPROM |
| 366 | bool "Enable driver for generic I2C-attached EEPROMs" |
| 367 | depends on MISC |
| 368 | help |
| 369 | Enable a generic driver for EEPROMs attached via I2C. |
Adam Ford | 5664f83 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 370 | |
Wenyou Yang | f791d56 | 2017-09-06 13:08:14 +0800 | [diff] [blame] | 371 | |
| 372 | config SPL_I2C_EEPROM |
| 373 | bool "Enable driver for generic I2C-attached EEPROMs for SPL" |
| 374 | depends on MISC && SPL && SPL_DM |
| 375 | help |
| 376 | This option is an SPL-variant of the I2C_EEPROM option. |
| 377 | See the help of I2C_EEPROM for details. |
| 378 | |
Vipul Kumar | 9621967 | 2018-02-16 19:07:21 +0530 | [diff] [blame] | 379 | config ZYNQ_GEM_I2C_MAC_OFFSET |
| 380 | hex "Set the I2C MAC offset" |
| 381 | default 0x0 |
Michal Simek | d9bdc6d | 2019-01-22 15:55:46 +0100 | [diff] [blame] | 382 | depends on DM_I2C |
Vipul Kumar | 9621967 | 2018-02-16 19:07:21 +0530 | [diff] [blame] | 383 | help |
| 384 | Set the MAC offset for i2C. |
| 385 | |
Adam Ford | 5664f83 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 386 | if I2C_EEPROM |
| 387 | |
| 388 | config SYS_I2C_EEPROM_ADDR |
| 389 | hex "Chip address of the EEPROM device" |
| 390 | default 0 |
| 391 | |
| 392 | config SYS_I2C_EEPROM_BUS |
| 393 | int "I2C bus of the EEPROM device." |
| 394 | default 0 |
| 395 | |
| 396 | config SYS_EEPROM_SIZE |
| 397 | int "Size in bytes of the EEPROM device" |
| 398 | default 256 |
| 399 | |
| 400 | config SYS_EEPROM_PAGE_WRITE_BITS |
| 401 | int "Number of bits used to address bytes in a single page" |
| 402 | default 0 |
| 403 | help |
| 404 | The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. |
| 405 | A 64 byte page, for example would require six bits. |
| 406 | |
| 407 | config SYS_EEPROM_PAGE_WRITE_DELAY_MS |
| 408 | int "Number of milliseconds to delay between page writes" |
| 409 | default 0 |
| 410 | |
| 411 | config SYS_I2C_EEPROM_ADDR_LEN |
| 412 | int "Length in bytes of the EEPROM memory array address" |
| 413 | default 1 |
| 414 | help |
| 415 | Note: This is NOT the chip address length! |
| 416 | |
| 417 | config SYS_I2C_EEPROM_ADDR_OVERFLOW |
| 418 | hex "EEPROM Address Overflow" |
| 419 | default 0 |
| 420 | help |
| 421 | EEPROM chips that implement "address overflow" are ones |
| 422 | like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
| 423 | address and the extra bits end up in the "chip address" bit |
| 424 | slots. This makes a 24WC08 (1Kbyte) chip look like four 256 |
| 425 | byte chips. |
| 426 | |
| 427 | endif |
| 428 | |
Mario Six | 7f504a0 | 2018-04-27 14:53:33 +0200 | [diff] [blame] | 429 | config GDSYS_RXAUI_CTRL |
| 430 | bool "Enable gdsys RXAUI control driver" |
| 431 | depends on MISC |
| 432 | help |
| 433 | Support gdsys FPGA's RXAUI control. |
Mario Six | 0cafb65 | 2018-07-31 14:24:15 +0200 | [diff] [blame] | 434 | |
| 435 | config GDSYS_IOEP |
| 436 | bool "Enable gdsys IOEP driver" |
| 437 | depends on MISC |
| 438 | help |
| 439 | Support gdsys FPGA's IO endpoint driver. |
Mario Six | 7fdcf28 | 2018-08-06 10:23:46 +0200 | [diff] [blame] | 440 | |
| 441 | config MPC83XX_SERDES |
| 442 | bool "Enable MPC83xx serdes driver" |
| 443 | depends on MISC |
| 444 | help |
| 445 | Support for serdes found on MPC83xx SoCs. |
| 446 | |
Tien Fong Chee | 5ca878b | 2018-07-06 16:28:03 +0800 | [diff] [blame] | 447 | config FS_LOADER |
| 448 | bool "Enable loader driver for file system" |
| 449 | help |
| 450 | This is file system generic loader which can be used to load |
| 451 | the file image from the storage into target such as memory. |
| 452 | |
| 453 | The consumer driver would then use this loader to program whatever, |
| 454 | ie. the FPGA device. |
| 455 | |
Mario Six | 8862f45 | 2018-10-04 09:00:54 +0200 | [diff] [blame] | 456 | config GDSYS_SOC |
| 457 | bool "Enable gdsys SOC driver" |
| 458 | depends on MISC |
| 459 | help |
| 460 | Support for gdsys IHS SOC, a simple bus associated with each gdsys |
| 461 | IHS (Integrated Hardware Systems) FPGA, which holds all devices whose |
| 462 | register maps are contained within the FPGA's register map. |
| 463 | |
Mario Six | 1a9d43f | 2018-10-04 09:00:55 +0200 | [diff] [blame] | 464 | config IHS_FPGA |
| 465 | bool "Enable IHS FPGA driver" |
| 466 | depends on MISC |
| 467 | help |
| 468 | Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on |
| 469 | gdsys devices, which supply the majority of the functionality offered |
| 470 | by the devices. This driver supports both CON and CPU variants of the |
| 471 | devices, depending on the device tree entry. |
Tero Kristo | f81f4cd | 2020-02-14 11:18:15 +0200 | [diff] [blame] | 472 | config ESM_K3 |
| 473 | bool "Enable K3 ESM driver" |
| 474 | depends on ARCH_K3 |
| 475 | help |
| 476 | Support ESM (Error Signaling Module) on TI K3 SoCs. |
Mario Six | 1a9d43f | 2018-10-04 09:00:55 +0200 | [diff] [blame] | 477 | |
Eugen Hristev | 3bd5610 | 2019-10-09 09:23:39 +0000 | [diff] [blame] | 478 | config MICROCHIP_FLEXCOM |
| 479 | bool "Enable Microchip Flexcom driver" |
| 480 | depends on MISC |
| 481 | help |
| 482 | The Atmel Flexcom is just a wrapper which embeds a SPI controller, |
| 483 | an I2C controller and an USART. |
| 484 | Only one function can be used at a time and is chosen at boot time |
| 485 | according to the device tree. |
| 486 | |
Tero Kristo | 887dde5 | 2019-10-24 15:00:46 +0530 | [diff] [blame] | 487 | config K3_AVS0 |
| 488 | depends on ARCH_K3 && SPL_DM_REGULATOR |
| 489 | bool "AVS class 0 support for K3 devices" |
| 490 | help |
| 491 | K3 devices have the optimized voltage values for the main voltage |
| 492 | domains stored in efuse within the VTM IP. This driver reads the |
| 493 | optimized voltage from the efuse, so that it can be programmed |
| 494 | to the PMIC on board. |
| 495 | |
Tero Kristo | 1444e11 | 2020-02-14 11:18:16 +0200 | [diff] [blame] | 496 | config ESM_PMIC |
| 497 | bool "Enable PMIC ESM driver" |
| 498 | depends on DM_PMIC |
| 499 | help |
| 500 | Support ESM (Error Signal Monitor) on PMIC devices. ESM is used |
| 501 | typically to reboot the board in error condition. |
| 502 | |
Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 503 | endmenu |