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Fabio Estevam5ffd3c52011-12-20 05:46:34 +00001/*
2 * Freescale MX28EVK board
3 *
4 * (C) Copyright 2011 Freescale Semiconductor, Inc.
5 *
6 * Author: Fabio Estevam <fabio.estevam@freescale.com>
7 *
8 * Based on m28evk.c:
9 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
10 * on behalf of DENX Software Engineering GmbH
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26#include <common.h>
27#include <asm/gpio.h>
28#include <asm/io.h>
29#include <asm/arch/imx-regs.h>
30#include <asm/arch/iomux-mx28.h>
31#include <asm/arch/clock.h>
32#include <asm/arch/sys_proto.h>
33#include <linux/mii.h>
34#include <miiphy.h>
35#include <netdev.h>
36#include <errno.h>
37
38DECLARE_GLOBAL_DATA_PTR;
39
40/*
41 * Functions
42 */
43int board_early_init_f(void)
44{
45 /* IO0 clock at 480MHz */
Otavio Salvador2906f942013-01-11 03:19:03 +000046 mxs_set_ioclk(MXC_IOCLK0, 480000);
Fabio Estevam5ffd3c52011-12-20 05:46:34 +000047 /* IO1 clock at 480MHz */
Otavio Salvador2906f942013-01-11 03:19:03 +000048 mxs_set_ioclk(MXC_IOCLK1, 480000);
Fabio Estevam5ffd3c52011-12-20 05:46:34 +000049
50 /* SSP0 clock at 96MHz */
Otavio Salvador2906f942013-01-11 03:19:03 +000051 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
Otavio Salvador22ff8942012-08-27 23:56:40 +000052 /* SSP2 clock at 160MHz */
Otavio Salvador2906f942013-01-11 03:19:03 +000053 mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
Fabio Estevam5ffd3c52011-12-20 05:46:34 +000054
Matthias Fuchsce575c42012-01-18 01:33:08 +000055#ifdef CONFIG_CMD_USB
56 mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
57 mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
58 MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
59 gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
60#endif
61
Fabio Estevam9f95ce22013-05-10 09:14:09 +000062 /* Power on LCD */
63 gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
64
65 /* Set contrast to maximum */
66 gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
67
Fabio Estevam5ffd3c52011-12-20 05:46:34 +000068 return 0;
69}
70
71int dram_init(void)
72{
Otavio Salvadora2bbe0c2012-08-19 04:58:30 +000073 return mxs_dram_init();
Fabio Estevam5ffd3c52011-12-20 05:46:34 +000074}
75
76int board_init(void)
77{
78 /* Adress of boot parameters */
79 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
80
81 return 0;
82}
83
84#ifdef CONFIG_CMD_MMC
85static int mx28evk_mmc_wp(int id)
86{
87 if (id != 0) {
88 printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
89 return 1;
90 }
91
92 return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
93}
94
95int board_mmc_init(bd_t *bis)
96{
97 /* Configure WP as input */
98 gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
99
100 /* Configure MMC0 Power Enable */
101 gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
102
Marek Vasut722181e2013-01-22 15:01:03 +0000103 return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
Fabio Estevam5ffd3c52011-12-20 05:46:34 +0000104}
105#endif
106
107#ifdef CONFIG_CMD_NET
108
Fabio Estevam5ffd3c52011-12-20 05:46:34 +0000109int board_eth_init(bd_t *bis)
110{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000111 struct mxs_clkctrl_regs *clkctrl_regs =
112 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Fabio Estevam5ffd3c52011-12-20 05:46:34 +0000113 struct eth_device *dev;
114 int ret;
115
116 ret = cpu_eth_init(bis);
117
118 /* MX28EVK uses ENET_CLK PAD to drive FEC clock */
119 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
120 &clkctrl_regs->hw_clkctrl_enet);
121
122 /* Power-on FECs */
123 gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
124
125 /* Reset FEC PHYs */
126 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
127 udelay(200);
128 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
129
130 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
131 if (ret) {
132 puts("FEC MXS: Unable to init FEC0\n");
133 return ret;
134 }
135
136 ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
137 if (ret) {
138 puts("FEC MXS: Unable to init FEC1\n");
139 return ret;
140 }
141
142 dev = eth_get_dev_by_name("FEC0");
143 if (!dev) {
144 puts("FEC MXS: Unable to get FEC0 device entry\n");
145 return -EINVAL;
146 }
147
Fabio Estevam5ffd3c52011-12-20 05:46:34 +0000148 dev = eth_get_dev_by_name("FEC1");
149 if (!dev) {
150 puts("FEC MXS: Unable to get FEC1 device entry\n");
151 return -EINVAL;
152 }
153
Fabio Estevam5ffd3c52011-12-20 05:46:34 +0000154 return ret;
155}
156
157#endif