blob: 9a5e5bd009d8e5ba375a1a7aeb2f3787e5bb18d0 [file] [log] [blame]
Marek Vasut0b16ba52022-04-12 17:26:01 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */
5
6#ifndef __IMX8MM_DATA_MODUL_EDM_SBC_H
7#define __IMX8MM_DATA_MODUL_EDM_SBC_H
8
9#include <linux/sizes.h>
10#include <linux/stringify.h>
11#include <asm/arch/imx-regs.h>
12
Marek Vasut0b16ba52022-04-12 17:26:01 +020013#ifdef CONFIG_SPL_BUILD
Tom Rinifb52b942022-12-04 10:04:49 -050014#define CFG_MALLOC_F_ADDR 0x930000
Marek Vasut0b16ba52022-04-12 17:26:01 +020015
16/* For RAW image gives a error info not panic */
Marek Vasut0b16ba52022-04-12 17:26:01 +020017
18#endif
19
20/* Link Definitions */
Tom Rini6a5dccc2022-11-16 13:10:41 -050021#define CFG_SYS_INIT_RAM_ADDR 0x40000000
22#define CFG_SYS_INIT_RAM_SIZE 0x200000
Marek Vasut0b16ba52022-04-12 17:26:01 +020023
Tom Rinibb4dd962022-11-16 13:10:37 -050024#define CFG_SYS_SDRAM_BASE 0x40000000
Marek Vasut0b16ba52022-04-12 17:26:01 +020025#define PHYS_SDRAM 0x40000000
26#define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
27
Tom Rinia17aa192022-12-04 10:04:55 -050028#define CFG_MXC_UART_BASE UART3_BASE_ADDR
Marek Vasut0b16ba52022-04-12 17:26:01 +020029
30/* PHY needs a longer autonegotiation timeout after reset */
Marek Vasut0b16ba52022-04-12 17:26:01 +020031
32/* USDHC */
Tom Rini376b88a2022-10-28 20:27:13 -040033#define CFG_SYS_FSL_USDHC_NUM 2
34#define CFG_SYS_FSL_ESDHC_ADDR 0
Marek Vasut0b16ba52022-04-12 17:26:01 +020035
Marek Vasut54e99772024-01-13 18:59:13 +010036#define CFG_EXTRA_ENV_SETTINGS \
Marek Vasut0b16ba52022-04-12 17:26:01 +020037 "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
38 "bootlimit=3\0" \
39 "devtype=mmc\0" \
40 "devpart=1\0" \
Marek Vasut0b16ba52022-04-12 17:26:01 +020041 "dfu_alt_info=" \
42 /* RAM block at DRAM offset 256..768 MiB */ \
43 "ram ram0=ram ram 0x50000000 0x20000000&" \
44 /* 16 MiB SPI NOR */ \
45 "mtd nor0=sf raw 0x0 0x1000000\0" \
46 "dmo_preboot=" \
47 "sf probe ; " /* Scan for SPI NOR, needed by DFU */ \
Marek Vasut0b16ba52022-04-12 17:26:01 +020048 /* Attempt to start USB and Network console */ \
49 "run dmo_usb_cdc_acm_start ; " \
50 "run dmo_netconsole_start\0" \
51 "dmo_update_env=" \
52 "setenv dmo_update_env true ; saveenv ; saveenv\0" \
53 "dmo_usb_cdc_acm_start=" \
54 "if test \"${dmo_usb_cdc_acm_enabled}\" = \"true\" ; then "\
55 /* Ungate IMX8MM_CLK_USB1_CTRL_ROOT */ \
56 "mw 0x303844d0 3 ; " \
57 /* Read USBNC_n_PHY_STATUS BIT(4) VBUS_VLD */ \
58 "setexpr.l usbnc_n_phy_status *0x32e4023c \\\\& 0x8 ; " \
59 /* If USB OTG has valid VBUS, enable CDC ACM */ \
60 "if test \"${usbnc_n_phy_status}\" -eq 8 ; then "\
61 "usb start && " \
62 "setenv stderr ${stderr},usbacm && " \
63 "setenv stdout ${stdout},usbacm && " \
64 "setenv stdin ${stdin},usbacm ; " \
65 "fi ; " \
66 "fi\0" \
Marek Vasut0b16ba52022-04-12 17:26:01 +020067 "dmo_netconsole_start=" \
68 "if test \"${dmo_netconsole_enabled}\" = \"true\" ; then "\
69 "setenv autoload false && " \
70 "dhcp && " \
71 "setenv autoload && " \
72 "setenv ncip ${serverip} && " \
73 "setenv stderr ${stderr},nc && " \
74 "setenv stdout ${stdout},nc && " \
75 "setenv stdin ${stdin},nc ; " \
Marek Vasut54e99772024-01-13 18:59:13 +010076 "fi\0" \
77 "stdin=serial\0" \
78 "stdout=serial\0" \
79 "stderr=serial\0" \
80 /* Give slow devices beyond USB HUB chance to come up. */ \
81 "usb_pgood_delay=2000\0"
Marek Vasut0b16ba52022-04-12 17:26:01 +020082
83#endif