blob: 4ba83142841a23c0672620e193e08a4165f8b985 [file] [log] [blame]
Peng Fan702c6dc2018-10-18 14:28:37 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -06007#include <env.h>
Peng Fan702c6dc2018-10-18 14:28:37 +02008#include <errno.h>
9#include <linux/libfdt.h>
Yangbo Lu73340382019-06-21 11:42:28 +080010#include <fsl_esdhc_imx.h>
Peng Fan702c6dc2018-10-18 14:28:37 +020011#include <asm/io.h>
12#include <asm/gpio.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/sci/sci.h>
15#include <asm/arch/imx8-pins.h>
16#include <asm/arch/iomux.h>
17#include <asm/arch/sys_proto.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
22 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
23 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
24 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
25
26#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
27 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
28 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
29 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
30
31static iomux_cfg_t uart0_pads[] = {
32 SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
33 SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
34};
35
36static void setup_iomux_uart(void)
37{
38 imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
39}
40
41int board_early_init_f(void)
42{
Anatolij Gustschinef156d22019-06-12 13:35:25 +020043 sc_pm_clock_rate_t rate = SC_80MHZ;
Peng Fan702c6dc2018-10-18 14:28:37 +020044 int ret;
Peng Fan702c6dc2018-10-18 14:28:37 +020045
Anatolij Gustschinef156d22019-06-12 13:35:25 +020046 /* Set UART0 clock root to 80 MHz */
47 ret = sc_pm_setup_uart(SC_R_UART_0, rate);
Peng Fan702c6dc2018-10-18 14:28:37 +020048 if (ret)
49 return ret;
50
51 setup_iomux_uart();
52
53 return 0;
54}
55
56#if IS_ENABLED(CONFIG_DM_GPIO)
57static void board_gpio_init(void)
58{
59 struct gpio_desc desc;
60 int ret;
61
62 ret = dm_gpio_lookup_name("gpio@1a_3", &desc);
63 if (ret)
64 return;
65
66 ret = dm_gpio_request(&desc, "bb_per_rst_b");
67 if (ret)
68 return;
69
70 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
71 dm_gpio_set_value(&desc, 0);
72 udelay(50);
73 dm_gpio_set_value(&desc, 1);
74}
75#else
76static inline void board_gpio_init(void) {}
77#endif
78
79#if IS_ENABLED(CONFIG_FEC_MXC)
80#include <miiphy.h>
81
82int board_phy_config(struct phy_device *phydev)
83{
84 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
85 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
86
87 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
88 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
89
90 if (phydev->drv->config)
91 phydev->drv->config(phydev);
92
93 return 0;
94}
95#endif
96
Peng Fan702c6dc2018-10-18 14:28:37 +020097int checkboard(void)
98{
99 puts("Board: iMX8QXP MEK\n");
100
101 build_info();
102 print_bootinfo();
103
104 return 0;
105}
106
107int board_init(void)
108{
109 board_gpio_init();
110
111 return 0;
112}
113
114void detail_board_ddr_info(void)
115{
116 puts("\nDDR ");
117}
118
119/*
120 * Board specific reset that is system reset.
121 */
122void reset_cpu(ulong addr)
123{
124 /* TODO */
125}
126
127#ifdef CONFIG_OF_BOARD_SETUP
128int ft_board_setup(void *blob, bd_t *bd)
129{
130 return 0;
131}
132#endif
133
134int board_mmc_get_env_dev(int devno)
135{
136 return devno;
137}
138
139int board_late_init(void)
140{
141#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
142 env_set("board_name", "MEK");
143 env_set("board_rev", "iMX8QXP");
144#endif
145
146 return 0;
147}