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git01.mediatek.com / filogic / uboot / 9f0a8e9b65634ab00f2c44686cc5a3ab7ca89cb5 / . / board / zyxel / nsa310s / nsa310s.c
blob: aab33cfa2a2dd3fade10fb56587ffb0f84a6b403 [file] [log] [blame]
Gerald Kerma06990b82015-10-23 09:50:58 +0200[diff] [blame]1/*
2 * Copyright (C) 2015
3 * Gerald Kerma <dreagle@doukki.net>
4 * Tony Dinh <mibodhi@gmail.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <miiphy.h>
11#include <asm/arch/cpu.h>
12#include <asm/arch/soc.h>
13#include <asm/arch/mpp.h>
14#include <asm/io.h>
15#include "nsa310s.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19int board_early_init_f(void)
20{
21 /*
22 * default gpio configuration
23 * There are maximum 64 gpios controlled through 2 sets of registers
24 * the below configuration configures mainly initial LED status
25 */
26 mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
27 NSA310S_OE_LOW, NSA310S_OE_HIGH);
28
29 /* (all LEDs & power off active high) */
30 /* Multi-Purpose Pins Functionality configuration */
31 static const u32 kwmpp_config[] = {
32 MPP0_NF_IO2,
33 MPP1_NF_IO3,
34 MPP2_NF_IO4,
35 MPP3_NF_IO5,
36 MPP4_NF_IO6,
37 MPP5_NF_IO7,
38 MPP6_SYSRST_OUTn,
39 MPP7_GPO,
40 MPP8_TW_SDA,
41 MPP9_TW_SCK,
42 MPP10_UART0_TXD,
43 MPP11_UART0_RXD,
44 MPP12_GPO,
45 MPP13_GPIO,
46 MPP14_GPIO,
47 MPP15_GPIO,
48 MPP16_GPIO,
49 MPP17_GPIO,
50 MPP18_NF_IO0,
51 MPP19_NF_IO1,
52 MPP20_GPIO,
53 MPP21_GPIO,
54 MPP22_GPIO,
55 MPP23_GPIO,
56 MPP24_GPIO,
57 MPP25_GPIO,
58 MPP26_GPIO,
59 MPP27_GPIO,
60 MPP28_GPIO,
61 MPP29_GPIO,
62 MPP30_GPIO,
63 MPP31_GPIO,
64 MPP32_GPIO,
65 MPP33_GPIO,
66 MPP34_GPIO,
67 MPP35_GPIO,
68 0
69 };
70 kirkwood_mpp_conf(kwmpp_config, NULL);
71 return 0;
72}
73
74int board_init(void)
75{
76 /* address of boot parameters */
77 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
78
79 return 0;
80}
81
82#ifdef CONFIG_RESET_PHY_R
83void reset_phy(void)
84{
85 u16 reg;
86 u16 phyaddr;
87 char *name = "egiga0";
88
89 if (miiphy_set_current_dev(name))
90 return;
91
92 /* read PHY dev address */
93 if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
94 printf("could not read PHY dev address\n");
95 return;
96 }
97
98 /* set RGMII delay */
99 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
100 miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg);
101 reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
102 miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
103 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
104
105 /* reset PHY */
106 if (miiphy_reset(name, phyaddr))
107 return;
108
109 /*
110 * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
111 * and has an MCU attached to the LED[2] via tristate interrupt
112 */
113
114 /* switch to LED register page */
115 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
116 /* read out LED polarity register */
117 miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, &reg);
118 /* clear 4, set 5 - LED2 low, tri-state */
119 reg &= ~(MV88E1318_LED2_4);
120 reg |= (MV88E1318_LED2_5);
121 /* write back LED polarity register */
122 miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
123 /* jump back to page 0, per the PHY chip documenation. */
124 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
125
126 /* set PHY back to auto-negotiation mode */
127 miiphy_write(name, phyaddr, 0x4, 0x1e1);
128 miiphy_write(name, phyaddr, 0x9, 0x300);
129 /* downshift */
130 miiphy_write(name, phyaddr, 0x10, 0x3860);
131 miiphy_write(name, phyaddr, 0x0, 0x9140);
132}
133#endif /* CONFIG_RESET_PHY_R */