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git01.mediatek.com / filogic / uboot / 9ef026b6cf59f04833effecbac77fdd66ef8aa2e / . / arch / arm / dts / imx8mm-venice-gw7902.dts
blob: 07e436be95e5b7df0970901f5dc33f5316d05b1f [file] [log] [blame]
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12
13#include "imx8mm.dtsi"
14
15/ {
16 model = "Gateworks Venice GW7902 i.MX8MM board";
17 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
18
19 aliases {
20 usb0 = &usbotg1;
21 usb1 = &usbotg2;
22 };
23
24 chosen {
25 stdout-path = &uart2;
26 };
27
28 memory@40000000 {
29 device_type = "memory";
30 reg = <0x0 0x40000000 0 0x80000000>;
31 };
32
33 can20m: can20m {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <20000000>;
37 clock-output-names = "can20m";
38 };
39
40 gpio-keys {
41 compatible = "gpio-keys";
42
43 user-pb {
44 label = "user_pb";
45 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
46 linux,code = <BTN_0>;
47 };
48
49 user-pb1x {
50 label = "user_pb1x";
51 linux,code = <BTN_1>;
52 interrupt-parent = <&gsc>;
53 interrupts = <0>;
54 };
55
56 key-erased {
57 label = "key_erased";
58 linux,code = <BTN_2>;
59 interrupt-parent = <&gsc>;
60 interrupts = <1>;
61 };
62
63 eeprom-wp {
64 label = "eeprom_wp";
65 linux,code = <BTN_3>;
66 interrupt-parent = <&gsc>;
67 interrupts = <2>;
68 };
69
70 tamper {
71 label = "tamper";
72 linux,code = <BTN_4>;
73 interrupt-parent = <&gsc>;
74 interrupts = <5>;
75 };
76
77 switch-hold {
78 label = "switch_hold";
79 linux,code = <BTN_5>;
80 interrupt-parent = <&gsc>;
81 interrupts = <7>;
82 };
83 };
84
85 led-controller {
86 compatible = "gpio-leds";
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_gpio_leds>;
89
90 led-0 {
91 function = LED_FUNCTION_STATUS;
92 color = <LED_COLOR_ID_GREEN>;
93 label = "panel1";
94 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
95 default-state = "off";
96 };
97
98 led-1 {
99 function = LED_FUNCTION_STATUS;
100 color = <LED_COLOR_ID_GREEN>;
101 label = "panel2";
102 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
103 default-state = "off";
104 };
105
106 led-2 {
107 function = LED_FUNCTION_STATUS;
108 color = <LED_COLOR_ID_GREEN>;
109 label = "panel3";
110 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
111 default-state = "off";
112 };
113
114 led-3 {
115 function = LED_FUNCTION_STATUS;
116 color = <LED_COLOR_ID_GREEN>;
117 label = "panel4";
118 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
119 default-state = "off";
120 };
121
122 led-4 {
123 function = LED_FUNCTION_STATUS;
124 color = <LED_COLOR_ID_GREEN>;
125 label = "panel5";
126 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
127 default-state = "off";
128 };
129 };
130
131 pps {
132 compatible = "pps-gpio";
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_pps>;
135 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
136 status = "okay";
137 };
138
139 reg_3p3v: regulator-3p3v {
140 compatible = "regulator-fixed";
141 regulator-name = "3P3V";
142 regulator-min-microvolt = <3300000>;
143 regulator-max-microvolt = <3300000>;
144 };
145
146 reg_usb1_vbus: regulator-usb1 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_reg_usb1>;
149 compatible = "regulator-fixed";
150 regulator-name = "usb_usb1_vbus";
151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
152 enable-active-high;
153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <5000000>;
155 };
156
157 reg_wifi: regulator-wifi {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_reg_wl>;
160 compatible = "regulator-fixed";
161 regulator-name = "wifi";
162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
163 enable-active-high;
164 startup-delay-us = <100>;
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
167 };
168};
169
170&A53_0 {
171 cpu-supply = <&buck2>;
172};
173
174&A53_1 {
175 cpu-supply = <&buck2>;
176};
177
178&A53_2 {
179 cpu-supply = <&buck2>;
180};
181
182&A53_3 {
183 cpu-supply = <&buck2>;
184};
185
186&ddrc {
187 operating-points-v2 = <&ddrc_opp_table>;
188
189 ddrc_opp_table: opp-table {
190 compatible = "operating-points-v2";
191
192 opp-25M {
193 opp-hz = /bits/ 64 <25000000>;
194 };
195
196 opp-100M {
197 opp-hz = /bits/ 64 <100000000>;
198 };
199
200 opp-750M {
201 opp-hz = /bits/ 64 <750000000>;
202 };
203 };
204};
205
206&ecspi1 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi1>;
209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
210 status = "okay";
211
212 can@0 {
213 compatible = "microchip,mcp2515";
214 reg = <0>;
215 clocks = <&can20m>;
216 oscillator-frequency = <20000000>;
217 interrupt-parent = <&gpio2>;
218 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
219 spi-max-frequency = <10000000>;
220 };
221};
222
223/* off-board header */
224&ecspi2 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_spi2>;
227 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
228 status = "okay";
229};
230
231&fec1 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_fec1>;
234 phy-mode = "rgmii-id";
235 phy-handle = <&ethphy0>;
236 local-mac-address = [00 00 00 00 00 00];
237 status = "okay";
238
239 mdio {
240 #address-cells = <1>;
241 #size-cells = <0>;
242
243 ethphy0: ethernet-phy@0 {
244 compatible = "ethernet-phy-ieee802.3-c22";
245 reg = <0>;
246 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
247 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
248 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
249 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
250 };
251 };
252};
253
254&i2c1 {
255 clock-frequency = <100000>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_i2c1>;
258 status = "okay";
259
260 gsc: gsc@20 {
261 compatible = "gw,gsc";
262 reg = <0x20>;
263 pinctrl-0 = <&pinctrl_gsc>;
264 interrupt-parent = <&gpio2>;
265 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
266 interrupt-controller;
267 #interrupt-cells = <1>;
268
269 adc {
270 compatible = "gw,gsc-adc";
271 #address-cells = <1>;
272 #size-cells = <0>;
273
274 channel@6 {
275 gw,mode = <0>;
276 reg = <0x06>;
277 label = "temp";
278 };
279
280 channel@8 {
281 gw,mode = <1>;
282 reg = <0x08>;
283 label = "vdd_bat";
284 };
285
286 channel@82 {
287 gw,mode = <2>;
288 reg = <0x82>;
289 label = "vin";
290 gw,voltage-divider-ohms = <22100 1000>;
291 gw,voltage-offset-microvolt = <700000>;
292 };
293
294 channel@84 {
295 gw,mode = <2>;
296 reg = <0x84>;
297 label = "vin_4p0";
298 gw,voltage-divider-ohms = <10000 10000>;
299 };
300
301 channel@86 {
302 gw,mode = <2>;
303 reg = <0x86>;
304 label = "vdd_3p3";
305 gw,voltage-divider-ohms = <10000 10000>;
306 };
307
308 channel@88 {
309 gw,mode = <2>;
310 reg = <0x88>;
311 label = "vdd_0p9";
312 };
313
314 channel@8c {
315 gw,mode = <2>;
316 reg = <0x8c>;
317 label = "vdd_soc";
318 };
319
320 channel@8e {
321 gw,mode = <2>;
322 reg = <0x8e>;
323 label = "vdd_arm";
324 };
325
326 channel@90 {
327 gw,mode = <2>;
328 reg = <0x90>;
329 label = "vdd_1p8";
330 };
331
332 channel@92 {
333 gw,mode = <2>;
334 reg = <0x92>;
335 label = "vdd_dram";
336 };
337
338 channel@98 {
339 gw,mode = <2>;
340 reg = <0x98>;
341 label = "vdd_1p0";
342 };
343
344 channel@9a {
345 gw,mode = <2>;
346 reg = <0x9a>;
347 label = "vdd_2p5";
348 gw,voltage-divider-ohms = <10000 10000>;
349 };
350
351 channel@a2 {
352 gw,mode = <2>;
353 reg = <0xa2>;
354 label = "vdd_gsc";
355 gw,voltage-divider-ohms = <10000 10000>;
356 };
357 };
358 };
359
360 gpio: gpio@23 {
361 compatible = "nxp,pca9555";
362 reg = <0x23>;
363 gpio-controller;
364 #gpio-cells = <2>;
365 interrupt-parent = <&gsc>;
366 interrupts = <4>;
367 };
368
369 pmic@4b {
370 compatible = "rohm,bd71847";
371 reg = <0x4b>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_pmic>;
374 interrupt-parent = <&gpio3>;
375 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
376 rohm,reset-snvs-powered;
377 #clock-cells = <0>;
378 clocks = <&osc_32k 0>;
379 clock-output-names = "clk-32k-out";
380
381 regulators {
382 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
383 BUCK1 {
384 regulator-name = "buck1";
385 regulator-min-microvolt = <700000>;
386 regulator-max-microvolt = <1300000>;
387 regulator-boot-on;
388 regulator-always-on;
389 regulator-ramp-delay = <1250>;
390 };
391
392 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
393 buck2: BUCK2 {
394 regulator-name = "buck2";
395 regulator-min-microvolt = <700000>;
396 regulator-max-microvolt = <1300000>;
397 regulator-boot-on;
398 regulator-always-on;
399 regulator-ramp-delay = <1250>;
400 rohm,dvs-run-voltage = <1000000>;
401 rohm,dvs-idle-voltage = <900000>;
402 };
403
404 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
405 BUCK3 {
406 regulator-name = "buck3";
407 regulator-min-microvolt = <700000>;
408 regulator-max-microvolt = <1350000>;
409 regulator-boot-on;
410 regulator-always-on;
411 };
412
413 /* vdd_3p3 */
414 BUCK4 {
415 regulator-name = "buck4";
416 regulator-min-microvolt = <3000000>;
417 regulator-max-microvolt = <3300000>;
418 regulator-boot-on;
419 regulator-always-on;
420 };
421
422 /* vdd_1p8 */
423 BUCK5 {
424 regulator-name = "buck5";
425 regulator-min-microvolt = <1605000>;
426 regulator-max-microvolt = <1995000>;
427 regulator-boot-on;
428 regulator-always-on;
429 };
430
431 /* vdd_dram */
432 BUCK6 {
433 regulator-name = "buck6";
434 regulator-min-microvolt = <800000>;
435 regulator-max-microvolt = <1400000>;
436 regulator-boot-on;
437 regulator-always-on;
438 };
439
440 /* nvcc_snvs_1p8 */
441 LDO1 {
442 regulator-name = "ldo1";
443 regulator-min-microvolt = <1600000>;
444 regulator-max-microvolt = <1900000>;
445 regulator-boot-on;
446 regulator-always-on;
447 };
448
449 /* vdd_snvs_0p8 */
450 LDO2 {
451 regulator-name = "ldo2";
452 regulator-min-microvolt = <800000>;
453 regulator-max-microvolt = <900000>;
454 regulator-boot-on;
455 regulator-always-on;
456 };
457
458 /* vdda_1p8 */
459 LDO3 {
460 regulator-name = "ldo3";
461 regulator-min-microvolt = <1800000>;
462 regulator-max-microvolt = <3300000>;
463 regulator-boot-on;
464 regulator-always-on;
465 };
466
467 LDO4 {
468 regulator-name = "ldo4";
469 regulator-min-microvolt = <900000>;
470 regulator-max-microvolt = <1800000>;
471 regulator-boot-on;
472 regulator-always-on;
473 };
474
475 LDO6 {
476 regulator-name = "ldo6";
477 regulator-min-microvolt = <900000>;
478 regulator-max-microvolt = <1800000>;
479 regulator-boot-on;
480 regulator-always-on;
481 };
482 };
483 };
484
485 eeprom@50 {
486 compatible = "atmel,24c02";
487 reg = <0x50>;
488 pagesize = <16>;
489 };
490
491 eeprom@51 {
492 compatible = "atmel,24c02";
493 reg = <0x51>;
494 pagesize = <16>;
495 };
496
497 eeprom@52 {
498 compatible = "atmel,24c02";
499 reg = <0x52>;
500 pagesize = <16>;
501 };
502
503 eeprom@53 {
504 compatible = "atmel,24c02";
505 reg = <0x53>;
506 pagesize = <16>;
507 };
508
509 rtc@68 {
510 compatible = "dallas,ds1672";
511 reg = <0x68>;
512 };
513};
514
515&i2c2 {
516 clock-frequency = <400000>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_i2c2>;
519 status = "okay";
520
521 accelerometer@19 {
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_accel>;
524 compatible = "st,lis2de12";
525 reg = <0x19>;
526 st,drdy-int-pin = <1>;
527 interrupt-parent = <&gpio1>;
528 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
529 interrupt-names = "INT1";
530 };
531
532 secure-element@60 {
533 compatible = "nxp,se050";
534 reg = <0x60>;
535 };
536};
537
538/* off-board header */
539&i2c3 {
540 clock-frequency = <400000>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&pinctrl_i2c3>;
543 status = "okay";
544};
545
546/* off-board header */
547&i2c4 {
548 clock-frequency = <400000>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_i2c4>;
551 status = "okay";
552};
553
554/* off-board header */
555&sai3 {
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_sai3>;
558 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
559 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
560 assigned-clock-rates = <24576000>;
561 status = "okay";
562};
563
564/* RS232/RS485/RS422 selectable */
565&uart1 {
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
568 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
569 cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
570 status = "okay";
571};
572
573/* RS232 console */
574&uart2 {
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_uart2>;
577 status = "okay";
578};
579
580/* bluetooth HCI */
581&uart3 {
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
584 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
585 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
586 status = "okay";
587
588 bluetooth {
589 compatible = "brcm,bcm4330-bt";
590 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
591 };
592};
593
594/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
595&uart4 {
596 pinctrl-names = "default";
597 pinctrl-0 = <&pinctrl_uart4>;
598 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
599 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
600 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
601 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
602 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
603 status = "okay";
604};
605
606&usbotg1 {
607 dr_mode = "host";
608 vbus-supply = <&reg_usb1_vbus>;
609 disable-over-current;
610 status = "okay";
611};
612
613&usbotg2 {
614 dr_mode = "host";
615 disable-over-current;
616 status = "okay";
617};
618
619/* SDIO WiFi */
620&usdhc2 {
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_usdhc2>;
623 bus-width = <4>;
624 non-removable;
625 vmmc-supply = <&reg_wifi>;
626 status = "okay";
627};
628
629/* eMMC */
630&usdhc3 {
631 pinctrl-names = "default", "state_100mhz", "state_200mhz";
632 pinctrl-0 = <&pinctrl_usdhc3>;
633 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
634 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
635 bus-width = <8>;
636 non-removable;
637 status = "okay";
638};
639
640&wdog1 {
641 pinctrl-names = "default";
642 pinctrl-0 = <&pinctrl_wdog>;
643 fsl,ext-reset-output;
644 status = "okay";
645};
646
647&iomuxc {
648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_hog>;
650
651 pinctrl_hog: hoggrp {
652 fsl,pins = <
653 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
654 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* M2_RST# */
655 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
656 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
657 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
658 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
659 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
660 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
661 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
662 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
663 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
664 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
665 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
666 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
667 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
668 >;
669 };
670
671 pinctrl_accel: accelgrp {
672 fsl,pins = <
673 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
674 >;
675 };
676
677 pinctrl_fec1: fec1grp {
678 fsl,pins = <
679 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
680 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
681 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
682 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
683 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
684 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
685 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
686 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
687 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
688 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
689 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
690 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
691 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
692 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
693 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
694 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
695 MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
696 MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
697 >;
698 };
699
700 pinctrl_gsc: gscgrp {
701 fsl,pins = <
702 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
703 >;
704 };
705
706 pinctrl_i2c1: i2c1grp {
707 fsl,pins = <
708 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
709 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
710 >;
711 };
712
713 pinctrl_i2c2: i2c2grp {
714 fsl,pins = <
715 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
716 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
717 >;
718 };
719
720 pinctrl_i2c3: i2c3grp {
721 fsl,pins = <
722 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
723 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
724 >;
725 };
726
727 pinctrl_i2c4: i2c4grp {
728 fsl,pins = <
729 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
730 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
731 >;
732 };
733
734 pinctrl_gpio_leds: gpioledgrp {
735 fsl,pins = <
736 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x40000019
737 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x40000019
738 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x40000019
739 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x40000019
740 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000019
741 >;
742 };
743
744 pinctrl_pmic: pmicgrp {
745 fsl,pins = <
746 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
747 >;
748 };
749
750 pinctrl_pps: ppsgrp {
751 fsl,pins = <
752 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
753 >;
754 };
755
756 pinctrl_reg_wl: regwlgrp {
757 fsl,pins = <
758 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
759 >;
760 };
761
762 pinctrl_reg_usb1: regusb1grp {
763 fsl,pins = <
764 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
765 >;
766 };
767
768 pinctrl_sai3: sai3grp {
769 fsl,pins = <
770 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
771 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
772 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
773 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
774 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
775 >;
776 };
777
778 pinctrl_spi1: spi1grp {
779 fsl,pins = <
780 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
781 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
782 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
783 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
784 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
785 >;
786 };
787
788 pinctrl_spi2: spi2grp {
789 fsl,pins = <
790 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
791 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
792 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
793 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
794 >;
795 };
796
797 pinctrl_uart1: uart1grp {
798 fsl,pins = <
799 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
800 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
801 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
802 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
803 >;
804 };
805
806 pinctrl_uart1_gpio: uart1gpiogrp {
807 fsl,pins = <
808 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
809 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
810 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
811 >;
812 };
813
814 pinctrl_uart2: uart2grp {
815 fsl,pins = <
816 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
817 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
818 >;
819 };
820
821 pinctrl_uart3_gpio: uart3_gpiogrp {
822 fsl,pins = <
823 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
824 >;
825 };
826
827 pinctrl_uart3: uart3grp {
828 fsl,pins = <
829 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
830 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
831 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
832 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
833 >;
834 };
835
836 pinctrl_uart4: uart4grp {
837 fsl,pins = <
838 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
839 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
840 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
841 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
842 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
843 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
844 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
845 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
846 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
847 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
848 >;
849 };
850
851 pinctrl_usdhc2: usdhc2grp {
852 fsl,pins = <
853 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
854 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
855 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
856 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
857 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
858 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
859 >;
860 };
861
862 pinctrl_usdhc3: usdhc3grp {
863 fsl,pins = <
864 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
865 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
866 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
867 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
868 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
869 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
870 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
871 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
872 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
873 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
874 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
875 >;
876 };
877
878 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
879 fsl,pins = <
880 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
881 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
882 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
883 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
884 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
885 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
886 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
887 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
888 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
889 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
890 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
891 >;
892 };
893
894 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
895 fsl,pins = <
896 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
897 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
898 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
899 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
900 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
901 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
902 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
903 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
904 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
905 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
906 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
907 >;
908 };
909
910 pinctrl_wdog: wdoggrp {
911 fsl,pins = <
912 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
913 >;
914 };
915};