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Thomas Choufb798b12015-10-09 13:46:34 +08001menu "Timer Support"
2
3config TIMER
Bin Meng8a7b8642015-11-13 00:11:14 -08004 bool "Enable driver model for timer drivers"
Thomas Choufb798b12015-10-09 13:46:34 +08005 depends on DM
6 help
Bin Meng8a7b8642015-11-13 00:11:14 -08007 Enable driver model for timer access. It uses the same API as
8 lib/time.c, but now implemented by the uclass. The first timer
Thomas Choufb798b12015-10-09 13:46:34 +08009 will be used. The timer is usually a 32 bits free-running up
10 counter. There may be no real tick, and no timer interrupt.
11
Philipp Tomsich4fac4ea2017-07-28 17:38:42 +020012config SPL_TIMER
13 bool "Enable driver model for timer drivers in SPL"
14 depends on TIMER && SPL
15 help
16 Enable support for timer drivers in SPL. These can be used to get
17 a timer value when in SPL, or perhaps for implementing a delay
18 function. This enables the drivers in drivers/timer as part of an
19 SPL build.
20
21config TPL_TIMER
22 bool "Enable driver model for timer drivers in TPL"
23 depends on TIMER && TPL
24 help
25 Enable support for timer drivers in TPL. These can be used to get
26 a timer value when in TPL, or perhaps for implementing a delay
27 function. This enables the drivers in drivers/timer as part of an
28 TPL build.
29
Simon Glasse7ca7da2022-04-30 00:56:53 -060030config VPL_TIMER
31 bool "Enable driver model for timer drivers in VPL"
32 depends on TIMER && VPL
33 default y if TPL_TIMER
34 help
35 Enable support for timer drivers in VPL. These can be used to get
36 a timer value when in VPL, or perhaps for implementing a delay
37 function. This enables the drivers in drivers/timer as part of an
38 TPL build.
39
Simon Glass32f6c172016-02-24 09:14:49 -070040config TIMER_EARLY
41 bool "Allow timer to be used early in U-Boot"
42 depends on TIMER
Simon Glass6abd89b2018-09-02 17:02:24 -060043 # initr_bootstage() requires a timer and is called before initr_dm()
44 # so only the early timer is available
45 default y if X86 && BOOTSTAGE
Simon Glass32f6c172016-02-24 09:14:49 -070046 help
47 In some cases the timer must be accessible before driver model is
48 active. Examples include when using CONFIG_TRACE to trace U-Boot's
49 execution before driver model is set up. Enable this option to
50 use an early timer. These functions must be supported by your timer
51 driver: timer_early_get_count() and timer_early_get_rate().
52
Thomas Chou221d2ac2015-10-22 22:28:53 +080053config ALTERA_TIMER
Bin Meng8a7b8642015-11-13 00:11:14 -080054 bool "Altera timer support"
Thomas Chou221d2ac2015-10-22 22:28:53 +080055 depends on TIMER
56 help
Bin Meng8a7b8642015-11-13 00:11:14 -080057 Select this to enable a timer for Altera devices. Please find
Thomas Chou221d2ac2015-10-22 22:28:53 +080058 details on the "Embedded Peripherals IP User Guide" of Altera.
59
Sean Anderson5a238652020-10-25 21:46:57 -040060config ANDES_PLMT_TIMER
Sean Anderson5abf1f32020-10-25 21:46:56 -040061 bool
62 depends on RISCV_MMODE || SPL_RISCV_MMODE
63 help
64 The Andes PLMT block holds memory-mapped mtime register
65 associated with timer tick.
66
Bin Meng19f88b22018-10-10 22:07:02 -070067config ARC_TIMER
68 bool "ARC timer support"
69 depends on TIMER && ARC && CLK
70 help
71 Select this to enable built-in ARC timers.
72 ARC cores may have up to 2 built-in timers: timer0 and timer1,
73 usually at least one of them exists. Either of them is supported
74 in U-Boot.
75
76config AST_TIMER
77 bool "Aspeed ast2400/ast2500 timer support"
78 depends on TIMER
79 default y if ARCH_ASPEED
80 help
81 Select this to enable timer for Aspeed ast2400/ast2500 devices.
82 This is a simple sys timer driver, it is compatible with lib/time.c,
83 but does not support any interrupts. Even though SoC has 8 hardware
84 counters, they are all treated as a single device by this driver.
85 This is mostly because they all share several registers which
86 makes it difficult to completely separate them.
87
88config ATCPIT100_TIMER
89 bool "ATCPIT100 timer support"
90 depends on TIMER
91 help
92 Select this to enable a ATCPIT100 timer which will be embedded
93 in AE3XX, AE250 boards.
94
Wenyou.Yang@microchip.comce8a36f2017-08-15 17:40:26 +080095config ATMEL_PIT_TIMER
96 bool "Atmel periodic interval timer support"
97 depends on TIMER
98 help
99 Select this to enable a periodic interval timer for Atmel devices,
100 it is designed to offer maximum accuracy and efficient management,
101 even for systems with long response time.
102
Eugen Hristev59d62892022-04-04 11:35:51 +0300103config SPL_ATMEL_PIT_TIMER
104 bool "Atmel periodic interval timer support in SPL"
105 depends on SPL_TIMER
106 help
107 Select this to enable a periodic interval timer for Atmel devices,
108 it is designed to offer maximum accuracy and efficient management,
109 even for systems with long response time.
110 Select this to be available in SPL.
111
Clément Léger7e5c11b2022-03-31 10:55:06 +0200112config ATMEL_TCB_TIMER
113 bool "Atmel timer counter support"
114 depends on TIMER
115 depends on ARCH_AT91
116 help
117 Select this to enable the use of the timer counter as a monotonic
118 counter.
119
Eugen Hristev118141e2022-04-04 11:35:50 +0300120config SPL_ATMEL_TCB_TIMER
121 bool "Atmel timer counter support in SPL"
122 depends on SPL_TIMER
123 depends on ARCH_AT91
124 help
125 Select this to enable the use of the timer counter as a monotonic
126 counter in SPL.
127
Michal Simekc3caac52018-04-17 13:40:46 +0200128config CADENCE_TTC_TIMER
129 bool "Cadence TTC (Triple Timer Counter)"
130 depends on TIMER
131 help
132 Enables support for the cadence ttc driver. This driver is present
133 on Xilinx Zynq and ZynqMP SoCs.
134
Marek Vasut442c0f12018-08-18 15:58:32 +0200135config DESIGNWARE_APB_TIMER
136 bool "Designware APB Timer"
137 depends on TIMER
138 help
139 Enables support for the Designware APB Timer driver. This timer is
140 present on Altera SoCFPGA SoCs.
141
Bin Meng19f88b22018-10-10 22:07:02 -0700142config MPC83XX_TIMER
143 bool "MPC83xx timer support"
144 depends on TIMER
Bin Mengb2aa4c52015-11-13 00:11:24 -0800145 help
Bin Meng19f88b22018-10-10 22:07:02 -0700146 Select this to enable support for the timer found on
147 devices based on the MPC83xx family of SoCs.
Bin Mengb2aa4c52015-11-13 00:11:24 -0800148
Marek Vasut6be61c62019-05-04 17:30:58 +0200149config RENESAS_OSTM_TIMER
150 bool "Renesas RZ/A1 R7S72100 OSTM Timer"
151 depends on TIMER
152 help
153 Enables support for the Renesas OSTM Timer driver.
154 This timer is present on Renesas RZ/A1 R7S72100 SoCs.
155
Bin Meng917d2b82021-07-28 12:00:22 +0800156config X86_TSC_TIMER_FREQ
157 int "x86 TSC timer frequency in Hz"
Bin Meng855e6572018-10-13 20:52:10 -0700158 depends on X86_TSC_TIMER
Bin Meng917d2b82021-07-28 12:00:22 +0800159 default 1000000000
Bin Meng855e6572018-10-13 20:52:10 -0700160 help
Bin Meng917d2b82021-07-28 12:00:22 +0800161 Sets the estimated CPU frequency in Hz when TSC is used as the
Bin Meng855e6572018-10-13 20:52:10 -0700162 early timer and the frequency can neither be calibrated via some
163 hardware ways, nor got from device tree at the time when device
164 tree is not available yet.
165
Stephan Gerhold7b0c1c52020-01-04 18:45:15 +0100166config NOMADIK_MTU_TIMER
167 bool "Nomadik MTU Timer"
168 depends on TIMER
169 help
170 Enables support for the Nomadik Multi Timer Unit (MTU),
171 used in ST-Ericsson Ux500 SoCs.
172 The MTU provides 4 decrementing free-running timers.
173 At the moment, only the first timer is used by the driver.
174
Mugunthan V Nafae3702015-12-24 16:08:07 +0530175config OMAP_TIMER
176 bool "Omap timer support"
177 depends on TIMER
178 help
179 Select this to enable an timer for Omap devices.
180
Bin Meng25399032018-12-12 06:12:27 -0800181config RISCV_TIMER
182 bool "RISC-V timer support"
183 depends on TIMER && RISCV
184 help
Sean Anderson9baaaef2020-09-28 10:52:21 -0400185 Select this to enable support for a generic RISC-V S-Mode timer
186 driver.
Bin Meng25399032018-12-12 06:12:27 -0800187
Bin Meng19f88b22018-10-10 22:07:02 -0700188config ROCKCHIP_TIMER
189 bool "Rockchip timer support"
maxims@google.comf57bd002017-01-18 13:44:55 -0800190 depends on TIMER
maxims@google.comf57bd002017-01-18 13:44:55 -0800191 help
Bin Meng19f88b22018-10-10 22:07:02 -0700192 Select this to enable support for the timer found on
193 Rockchip devices.
194
195config SANDBOX_TIMER
196 bool "Sandbox timer support"
197 depends on SANDBOX && TIMER
198 help
199 Select this to enable an emulated timer for sandbox. It gets
200 time from host os.
maxims@google.comf57bd002017-01-18 13:44:55 -0800201
Patrice Chotard200a7992017-02-21 13:37:05 +0100202config STI_TIMER
203 bool "STi timer support"
204 depends on TIMER
205 default y if ARCH_STI
206 help
207 Select this to enable a timer for STi devices.
208
Patrice Chotardfdfefdc2018-02-07 10:44:45 +0100209config STM32_TIMER
Bin Meng19f88b22018-10-10 22:07:02 -0700210 bool "STM32 timer support"
Patrice Chotardfdfefdc2018-02-07 10:44:45 +0100211 depends on TIMER
212 help
213 Select this to enable support for the timer found on
214 STM32 devices.
215
Bin Meng19f88b22018-10-10 22:07:02 -0700216config X86_TSC_TIMER
217 bool "x86 Time-Stamp Counter (TSC) timer support"
218 depends on TIMER && X86
Mario Six3c516552018-08-06 10:23:38 +0200219 help
Bin Meng19f88b22018-10-10 22:07:02 -0700220 Select this to enable Time-Stamp Counter (TSC) timer for x86.
Mario Six3c516552018-08-06 10:23:38 +0200221
Simon Glassd3edd422019-12-06 21:41:49 -0700222config X86_TSC_READ_BASE
223 bool "Read the TSC timer base on start-up"
224 depends on X86_TSC_TIMER
225 help
226 On x86 platforms the TSC timer tick starts at the value 0 on reset.
227 This it makes no sense to read the timer on boot and use that as the
228 base, since we will miss some time taken to load U-Boot, etc. This
229 delay is controlled by the SoC and we cannot reduce it, but for
230 bootstage we want to record the time since reset as accurately as
231 possible.
232
233 The only exception is when U-Boot is used as a secondary bootloader,
234 where this option should be enabled.
235
Simon Glassbba203e2019-12-06 21:41:50 -0700236config TPL_X86_TSC_TIMER_NATIVE
237 bool "x86 TSC timer uses native calibration"
238 depends on TPL && X86_TSC_TIMER
239 help
240 Selects native timer calibration for TPL and don't include the other
241 methods in the code. This helps to reduce code size in TPL and works
242 on fairly modern Intel chips. Code-size reductions is about 700
243 bytes.
244
developer4a347352018-11-15 10:07:56 +0800245config MTK_TIMER
246 bool "MediaTek timer support"
247 depends on TIMER
248 help
249 Select this to enable support for the timer found on
250 MediaTek devices.
251
Claudiu Beznea5669c3d2020-09-07 18:36:33 +0300252config MCHP_PIT64B_TIMER
253 bool "Microchip 64-bit periodic interval timer support"
254 depends on TIMER
255 help
256 Select this to enable support for Microchip 64-bit periodic
257 interval timer.
258
Giulio Benetti9aed42b2021-05-13 12:18:31 +0200259config IMX_GPT_TIMER
260 bool "NXP i.MX GPT timer support"
261 depends on TIMER
262 help
263 Select this to enable support for the timer found on
264 NXP i.MX devices.
265
Thomas Choufb798b12015-10-09 13:46:34 +0800266endmenu