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Ramneek Mehreshf4de4072015-05-29 14:47:19 +05301/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * FSL USB HOST xHCI Controller
5 *
6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <usb.h>
13#include <asm-generic/errno.h>
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053014#include <linux/compat.h>
15#include <linux/usb/xhci-fsl.h>
16#include <linux/usb/dwc3.h>
17#include "xhci.h"
Sriram Dash01820952016-06-13 09:58:36 +053018#include <fsl_errata.h>
19#include <fsl_usb.h>
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053020
21/* Declare global data pointer */
22DECLARE_GLOBAL_DATA_PTR;
23
24static struct fsl_xhci fsl_xhci;
25unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
26
27__weak int __board_usb_init(int index, enum usb_init_type init)
28{
29 return 0;
30}
31
Sriram Dash01820952016-06-13 09:58:36 +053032static int erratum_a008751(void)
33{
34#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB)
35 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
36 writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
37 return 0;
38#endif
39 return 1;
40}
41
42static void fsl_apply_xhci_errata(void)
43{
44 int ret;
45 if (has_erratum_a008751()) {
46 ret = erratum_a008751();
47 if (ret != 0)
48 puts("Failed to apply erratum a008751\n");
49 }
50}
51
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053052static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
53{
54 int ret = 0;
55
56 ret = dwc3_core_init(fsl_xhci->dwc3_reg);
57 if (ret) {
58 debug("%s:failed to initialize core\n", __func__);
59 return ret;
60 }
61
62 /* We are hard-coding DWC3 core to Host Mode */
63 dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
64
Nikhil Badola807babb2015-06-23 09:17:49 +053065 /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
66 dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
67
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053068 return ret;
69}
70
71static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
72{
73 /*
74 * Currently fsl socs do not support PHY shutdown from
75 * sw. But this support may be added in future socs.
76 */
77 return 0;
78}
79
80int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
81{
82 struct fsl_xhci *ctx = &fsl_xhci;
83 int ret = 0;
84
85 ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
86 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
87
88 ret = board_usb_init(index, USB_INIT_HOST);
89 if (ret != 0) {
90 puts("Failed to initialize board for USB\n");
91 return ret;
92 }
93
Sriram Dash01820952016-06-13 09:58:36 +053094 fsl_apply_xhci_errata();
95
Ramneek Mehreshf4de4072015-05-29 14:47:19 +053096 ret = fsl_xhci_core_init(ctx);
97 if (ret < 0) {
98 puts("Failed to initialize xhci\n");
99 return ret;
100 }
101
102 *hccr = (struct xhci_hccr *)ctx->hcd;
Nikhil Badola05a18f42015-06-23 09:17:32 +0530103 *hcor = (struct xhci_hcor *)((uintptr_t) *hccr
Ramneek Mehreshf4de4072015-05-29 14:47:19 +0530104 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
105
Nikhil Badola05a18f42015-06-23 09:17:32 +0530106 debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
107 (uintptr_t)*hccr, (uintptr_t)*hcor,
108 (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
Ramneek Mehreshf4de4072015-05-29 14:47:19 +0530109
110 return ret;
111}
112
113void xhci_hcd_stop(int index)
114{
115 struct fsl_xhci *ctx = &fsl_xhci;
116
117 fsl_xhci_core_exit(ctx);
118}