blob: c4949301b756b82fac175fc1dbf032dbc142d5e1 [file] [log] [blame]
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00001#
2# (C) Copyright 2000-2003
3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4#
5# Copyright (C) 2012 Altera Corporation <www.altera.com>
6#
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007# SPDX-License-Identifier: GPL-2.0+
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00008#
9
Ley Foon Tand5c5e3b2017-04-26 02:44:35 +080010obj-y += misc.o timer.o reset_manager.o clock_manager.o \
Dinh Nguyen9365e902015-12-02 13:31:32 -060011 fpga_manager.o board.o
12
Ley Foon Tanca40f292017-04-26 02:44:39 +080013obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
14 reset_manager_arria10.o
Ley Foon Tan778ed2c2017-04-26 02:44:38 +080015
Dinh Nguyen8ed66612015-08-01 03:42:10 +020016obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
Marek Vasutaefb78d2015-08-02 21:12:09 +020017
18# QTS-generated config file wrappers
Ley Foon Tanec6f8822017-04-26 02:44:33 +080019obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
Ley Foon Tand5c5e3b2017-04-26 02:44:35 +080020 clock_manager_gen5.o reset_manager_gen5.o \
Ley Foon Tanb149f2b2017-04-26 02:44:36 +080021 misc_gen5.o system_manager_gen5.o
Marek Vasutaefb78d2015-08-02 21:12:09 +020022obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
23 wrap_sdram_config.o
24CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
25CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
26CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
27CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)