| Fabio Estevam | f22d759 | 2014-01-03 15:55:58 -0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Boundary Devices |
| 3 | * Copyright (C) 2013 SolidRun ltd. |
| 4 | * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | /* ZQ Calibrations */ |
| 10 | DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 |
| 11 | DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 |
| 12 | /* write leveling */ |
| 13 | DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057 |
| 14 | DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052 |
| 15 | /* |
| 16 | * DQS gating, read delay, write delay calibration values |
| 17 | * based on calibration compare of 0x00ffff00 |
| 18 | */ |
| 19 | DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240 |
| 20 | DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230 |
| 21 | DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440 |
| 22 | DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034 |
| 23 | /* read data bit delay */ |
| 24 | DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 |
| 25 | DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 |
| 26 | DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 |
| 27 | DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 |
| 28 | /* Complete calibration by forced measurement */ |
| 29 | DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 |
| 30 | DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 |
| 31 | |
| 32 | /* |
| 33 | * MMDC init: |
| 34 | * in DDR3, 32-bit mode, only MMDC0 is initiated: |
| 35 | */ |
| 36 | DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d |
| 37 | DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040 |
| 38 | |
| 39 | DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313 |
| 40 | DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63 |
| 41 | |
| 42 | DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db |
| 43 | DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 |
| 44 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 |
| 45 | DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 |
| 46 | DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 |
| 47 | /* CS0_END - 0x2fffffff, 512M */ |
| 48 | DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 |
| 49 | |
| 50 | /* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */ |
| 51 | DATA 4, 0x021b0400, 0x11420000 |
| 52 | |
| 53 | /* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */ |
| 54 | DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 |
| 55 | |
| 56 | /* |
| 57 | * Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C |
| 58 | * MR2 |
| 59 | */ |
| 60 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032 |
| 61 | /* MR3 */ |
| 62 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 |
| 63 | /* MR1 */ |
| 64 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 |
| 65 | /* MR0 */ |
| 66 | DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 |
| 67 | /* ZQ calibration */ |
| 68 | DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 |
| 69 | /* final DDR setup */ |
| 70 | DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 |
| 71 | DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 |
| 72 | DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d |
| 73 | DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 |
| 74 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 |