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git01.mediatek.com / filogic / uboot / 9e8fabc28669a585cd6a235e62340931e3060173 / . / arch / arm / include / asm / arch-tegra114 / clock-tables.h
blob: d4511817fa3b53ac8a15019a52bb2523222e07bb [file] [log] [blame]
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]1/*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 *
Tom Rinie2378802016-01-14 22:05:13 -0500[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]5 */
6
7/* Tegra114 clock PLL tables */
8
9#ifndef _TEGRA114_CLOCK_TABLES_H_
10#define _TEGRA114_CLOCK_TABLES_H_
11
12/* The PLLs supported by the hardware */
13enum clock_id {
14 CLOCK_ID_FIRST,
15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
16 CLOCK_ID_MEMORY,
17 CLOCK_ID_PERIPH,
18 CLOCK_ID_AUDIO,
19 CLOCK_ID_USB,
20 CLOCK_ID_DISPLAY,
21
22 /* now the simple ones */
23 CLOCK_ID_FIRST_SIMPLE,
24 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
25 CLOCK_ID_EPCI,
26 CLOCK_ID_SFROM32KHZ,
27
28 /* These are the base clocks (inputs to the Tegra SOC) */
29 CLOCK_ID_32KHZ,
30 CLOCK_ID_OSC,
Thierry Redingfa6e24d2015-08-20 11:42:19 +0200[diff] [blame]31 CLOCK_ID_CLK_M,
Tom Warrenc47e7172013-01-28 13:32:07 +0000[diff] [blame]32
33 CLOCK_ID_COUNT, /* number of PLLs */
34 CLOCK_ID_DISPLAY2, /* placeholder */
35 CLOCK_ID_NONE = -1,
36};
37
38/* The clocks supported by the hardware */
39enum periph_id {
40 PERIPH_ID_FIRST,
41
42 /* Low word: 31:0 (DEVICES_L) */
43 PERIPH_ID_CPU = PERIPH_ID_FIRST,
44 PERIPH_ID_COP,
45 PERIPH_ID_TRIGSYS,
46 PERIPH_ID_RESERVED3,
47 PERIPH_ID_RTC,
48 PERIPH_ID_TMR,
49 PERIPH_ID_UART1,
50 PERIPH_ID_UART2,
51
52 /* 8 */
53 PERIPH_ID_GPIO,
54 PERIPH_ID_SDMMC2,
55 PERIPH_ID_SPDIF,
56 PERIPH_ID_I2S1,
57 PERIPH_ID_I2C1,
58 PERIPH_ID_NDFLASH,
59 PERIPH_ID_SDMMC1,
60 PERIPH_ID_SDMMC4,
61
62 /* 16 */
63 PERIPH_ID_RESERVED16,
64 PERIPH_ID_PWM,
65 PERIPH_ID_I2S2,
66 PERIPH_ID_EPP,
67 PERIPH_ID_VI,
68 PERIPH_ID_2D,
69 PERIPH_ID_USBD,
70 PERIPH_ID_ISP,
71
72 /* 24 */
73 PERIPH_ID_3D,
74 PERIPH_ID_RESERVED24,
75 PERIPH_ID_DISP2,
76 PERIPH_ID_DISP1,
77 PERIPH_ID_HOST1X,
78 PERIPH_ID_VCP,
79 PERIPH_ID_I2S0,
80 PERIPH_ID_CACHE2,
81
82 /* Middle word: 63:32 (DEVICES_H) */
83 PERIPH_ID_MEM,
84 PERIPH_ID_AHBDMA,
85 PERIPH_ID_APBDMA,
86 PERIPH_ID_RESERVED35,
87 PERIPH_ID_KBC,
88 PERIPH_ID_STAT_MON,
89 PERIPH_ID_PMC,
90 PERIPH_ID_FUSE,
91
92 /* 40 */
93 PERIPH_ID_KFUSE,
94 PERIPH_ID_SBC1,
95 PERIPH_ID_SNOR,
96 PERIPH_ID_RESERVED43,
97 PERIPH_ID_SBC2,
98 PERIPH_ID_RESERVED45,
99 PERIPH_ID_SBC3,
100 PERIPH_ID_I2C5,
101
102 /* 48 */
103 PERIPH_ID_DSI,
104 PERIPH_ID_TVO,
105 PERIPH_ID_MIPI,
106 PERIPH_ID_HDMI,
107 PERIPH_ID_CSI,
108 PERIPH_ID_TVDAC,
109 PERIPH_ID_I2C2,
110 PERIPH_ID_UART3,
111
112 /* 56 */
113 PERIPH_ID_RESERVED56,
114 PERIPH_ID_EMC,
115 PERIPH_ID_USB2,
116 PERIPH_ID_USB3,
117 PERIPH_ID_MPE,
118 PERIPH_ID_VDE,
119 PERIPH_ID_BSEA,
120 PERIPH_ID_BSEV,
121
122 /* Upper word 95:64 (DEVICES_U) */
123 PERIPH_ID_SPEEDO,
124 PERIPH_ID_UART4,
125 PERIPH_ID_UART5,
126 PERIPH_ID_I2C3,
127 PERIPH_ID_SBC4,
128 PERIPH_ID_SDMMC3,
129 PERIPH_ID_PCIE,
130 PERIPH_ID_OWR,
131
132 /* 72 */
133 PERIPH_ID_AFI,
134 PERIPH_ID_CORESIGHT,
135 PERIPH_ID_PCIEXCLK,
136 PERIPH_ID_AVPUCQ,
137 PERIPH_ID_RESERVED76,
138 PERIPH_ID_RESERVED77,
139 PERIPH_ID_RESERVED78,
140 PERIPH_ID_DTV,
141
142 /* 80 */
143 PERIPH_ID_NANDSPEED,
144 PERIPH_ID_I2CSLOW,
145 PERIPH_ID_DSIB,
146 PERIPH_ID_RESERVED83,
147 PERIPH_ID_IRAMA,
148 PERIPH_ID_IRAMB,
149 PERIPH_ID_IRAMC,
150 PERIPH_ID_IRAMD,
151
152 /* 88 */
153 PERIPH_ID_CRAM2,
154 PERIPH_ID_RESERVED89,
155 PERIPH_ID_MDOUBLER,
156 PERIPH_ID_RESERVED91,
157 PERIPH_ID_SUSOUT,
158 PERIPH_ID_RESERVED93,
159 PERIPH_ID_RESERVED94,
160 PERIPH_ID_RESERVED95,
161
162 PERIPH_ID_VW_FIRST,
163 /* V word: 31:0 */
164 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
165 PERIPH_ID_CPULP,
166 PERIPH_ID_3D2,
167 PERIPH_ID_MSELECT,
168 PERIPH_ID_TSENSOR,
169 PERIPH_ID_I2S3,
170 PERIPH_ID_I2S4,
171 PERIPH_ID_I2C4,
172
173 /* 104 */
174 PERIPH_ID_SBC5,
175 PERIPH_ID_SBC6,
176 PERIPH_ID_AUDIO,
177 PERIPH_ID_APBIF,
178 PERIPH_ID_DAM0,
179 PERIPH_ID_DAM1,
180 PERIPH_ID_DAM2,
181 PERIPH_ID_HDA2CODEC2X,
182
183 /* 112 */
184 PERIPH_ID_ATOMICS,
185 PERIPH_ID_EX_RESERVED17,
186 PERIPH_ID_EX_RESERVED18,
187 PERIPH_ID_EX_RESERVED19,
188 PERIPH_ID_EX_RESERVED20,
189 PERIPH_ID_EX_RESERVED21,
190 PERIPH_ID_EX_RESERVED22,
191 PERIPH_ID_ACTMON,
192
193 /* 120 */
194 PERIPH_ID_EX_RESERVED24,
195 PERIPH_ID_EX_RESERVED25,
196 PERIPH_ID_EX_RESERVED26,
197 PERIPH_ID_EX_RESERVED27,
198 PERIPH_ID_SATA,
199 PERIPH_ID_HDA,
200 PERIPH_ID_EX_RESERVED30,
201 PERIPH_ID_EX_RESERVED31,
202
203 /* W word: 31:0 */
204 PERIPH_ID_HDA2HDMICODEC,
205 PERIPH_ID_RESERVED1_SATACOLD,
206 PERIPH_ID_RESERVED2_PCIERX0,
207 PERIPH_ID_RESERVED3_PCIERX1,
208 PERIPH_ID_RESERVED4_PCIERX2,
209 PERIPH_ID_RESERVED5_PCIERX3,
210 PERIPH_ID_RESERVED6_PCIERX4,
211 PERIPH_ID_RESERVED7_PCIERX5,
212
213 /* 136 */
214 PERIPH_ID_CEC,
215 PERIPH_ID_PCIE2_IOBIST,
216 PERIPH_ID_EMC_IOBIST,
217 PERIPH_ID_HDMI_IOBIST,
218 PERIPH_ID_SATA_IOBIST,
219 PERIPH_ID_MIPI_IOBIST,
220 PERIPH_ID_EMC1_IOBIST,
221 PERIPH_ID_XUSB,
222
223 /* 144 */
224 PERIPH_ID_CILAB,
225 PERIPH_ID_CILCD,
226 PERIPH_ID_CILE,
227 PERIPH_ID_DSIA_LP,
228 PERIPH_ID_DSIB_LP,
229 PERIPH_ID_RESERVED21_ENTROPY,
230 PERIPH_ID_RESERVED22_W,
231 PERIPH_ID_RESERVED23_W,
232
233 /* 152 */
234 PERIPH_ID_RESERVED24_W,
235 PERIPH_ID_AMX0,
236 PERIPH_ID_ADX0,
237 PERIPH_ID_DVFS,
238 PERIPH_ID_XUSB_SS,
239 PERIPH_ID_EMC_DLL,
240 PERIPH_ID_MC1,
241 PERIPH_ID_EMC1,
242
243 PERIPH_ID_COUNT,
244 PERIPH_ID_NONE = -1,
245};
246
247enum pll_out_id {
248 PLL_OUT1,
249 PLL_OUT2,
250 PLL_OUT3,
251 PLL_OUT4
252};
253
254/*
255 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
256 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
257 * confusion bewteen PERIPH_ID_... and PERIPHC_...
258 *
259 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
260 * confusing.
261 */
262enum periphc_internal_id {
263 /* 0x00 */
264 PERIPHC_I2S1,
265 PERIPHC_I2S2,
266 PERIPHC_SPDIF_OUT,
267 PERIPHC_SPDIF_IN,
268 PERIPHC_PWM,
269 PERIPHC_05h,
270 PERIPHC_SBC2,
271 PERIPHC_SBC3,
272
273 /* 0x08 */
274 PERIPHC_08h,
275 PERIPHC_I2C1,
276 PERIPHC_I2C5,
277 PERIPHC_0bh,
278 PERIPHC_0ch,
279 PERIPHC_SBC1,
280 PERIPHC_DISP1,
281 PERIPHC_DISP2,
282
283 /* 0x10 */
284 PERIPHC_CVE,
285 PERIPHC_11h,
286 PERIPHC_VI,
287 PERIPHC_13h,
288 PERIPHC_SDMMC1,
289 PERIPHC_SDMMC2,
290 PERIPHC_G3D,
291 PERIPHC_G2D,
292
293 /* 0x18 */
294 PERIPHC_NDFLASH,
295 PERIPHC_SDMMC4,
296 PERIPHC_VFIR,
297 PERIPHC_EPP,
298 PERIPHC_MPE,
299 PERIPHC_MIPI,
300 PERIPHC_UART1,
301 PERIPHC_UART2,
302
303 /* 0x20 */
304 PERIPHC_HOST1X,
305 PERIPHC_21h,
306 PERIPHC_TVO,
307 PERIPHC_HDMI,
308 PERIPHC_24h,
309 PERIPHC_TVDAC,
310 PERIPHC_I2C2,
311 PERIPHC_EMC,
312
313 /* 0x28 */
314 PERIPHC_UART3,
315 PERIPHC_29h,
316 PERIPHC_VI_SENSOR,
317 PERIPHC_2bh,
318 PERIPHC_2ch,
319 PERIPHC_SBC4,
320 PERIPHC_I2C3,
321 PERIPHC_SDMMC3,
322
323 /* 0x30 */
324 PERIPHC_UART4,
325 PERIPHC_UART5,
326 PERIPHC_VDE,
327 PERIPHC_OWR,
328 PERIPHC_NOR,
329 PERIPHC_CSITE,
330 PERIPHC_I2S0,
331 PERIPHC_37h,
332
333 PERIPHC_VW_FIRST,
334 /* 0x38 */
335 PERIPHC_G3D2 = PERIPHC_VW_FIRST,
336 PERIPHC_MSELECT,
337 PERIPHC_TSENSOR,
338 PERIPHC_I2S3,
339 PERIPHC_I2S4,
340 PERIPHC_I2C4,
341 PERIPHC_SBC5,
342 PERIPHC_SBC6,
343
344 /* 0x40 */
345 PERIPHC_AUDIO,
346 PERIPHC_41h,
347 PERIPHC_DAM0,
348 PERIPHC_DAM1,
349 PERIPHC_DAM2,
350 PERIPHC_HDA2CODEC2X,
351 PERIPHC_ACTMON,
352 PERIPHC_EXTPERIPH1,
353
354 /* 0x48 */
355 PERIPHC_EXTPERIPH2,
356 PERIPHC_EXTPERIPH3,
357 PERIPHC_NANDSPEED,
358 PERIPHC_I2CSLOW,
359 PERIPHC_SYS,
360 PERIPHC_SPEEDO,
361 PERIPHC_4eh,
362 PERIPHC_4fh,
363
364 /* 0x50 */
365 PERIPHC_50h,
366 PERIPHC_51h,
367 PERIPHC_52h,
368 PERIPHC_53h,
369 PERIPHC_SATAOOB,
370 PERIPHC_SATA,
371 PERIPHC_HDA,
372
373 PERIPHC_COUNT,
374
375 PERIPHC_NONE = -1,
376};
377
378/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
379#define PERIPH_REG(id) \
380 (id < PERIPH_ID_VW_FIRST) ? \
381 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
382
383/* Mask value for a clock (within PERIPH_REG(id)) */
384#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
385
386/* return 1 if a PLL ID is in range */
387#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
388
389/* return 1 if a peripheral ID is in range */
390#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
391 (id) < PERIPH_ID_COUNT)
392
393#endif /* _TEGRA114_CLOCK_TABLES_H_ */