Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * R8A779A0 processor support - PFC hardware block. |
| 4 | * |
| 5 | * Copyright (C) 2021 Renesas Electronics Corp. |
| 6 | * |
| 7 | * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c |
| 8 | */ |
| 9 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 10 | #include <dm.h> |
| 11 | #include <errno.h> |
| 12 | #include <dm/pinctrl.h> |
| 13 | #include <linux/bitops.h> |
| 14 | #include <linux/kernel.h> |
| 15 | |
| 16 | #include "sh_pfc.h" |
| 17 | |
| 18 | #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) |
| 19 | |
| 20 | #define CPU_ALL_GP(fn, sfx) \ |
| 21 | PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
| 22 | PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
| 23 | PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \ |
| 24 | PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \ |
| 25 | PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \ |
| 26 | PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \ |
| 27 | PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \ |
| 28 | PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \ |
| 29 | PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \ |
| 30 | PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ |
| 31 | PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ |
| 32 | PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ |
| 33 | PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ |
| 34 | PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \ |
| 35 | PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \ |
| 36 | PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \ |
| 37 | PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \ |
| 38 | PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \ |
| 39 | PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \ |
| 40 | PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \ |
| 41 | PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \ |
| 42 | PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \ |
| 43 | PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \ |
| 44 | PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \ |
| 45 | PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \ |
| 46 | PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \ |
| 47 | PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \ |
| 48 | PORT_GP_CFG_25(4, fn, sfx, CFG_FLAGS), \ |
| 49 | PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \ |
| 50 | PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \ |
| 51 | PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \ |
| 52 | PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33) |
| 53 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 54 | #define CPU_ALL_NOGP(fn) \ |
| 55 | PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ |
| 56 | PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ |
| 57 | PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ |
| 58 | PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25) |
| 59 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 60 | /* GPSR0 */ |
| 61 | #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8) |
| 62 | #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4) |
| 63 | #define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0) |
| 64 | #define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28) |
| 65 | #define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24) |
| 66 | #define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20) |
| 67 | #define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16) |
| 68 | #define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12) |
| 69 | #define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8) |
| 70 | #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4) |
| 71 | #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0) |
| 72 | #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28) |
| 73 | #define GPSR0_6 F_(IRQ0, IP0SR0_27_24) |
| 74 | #define GPSR0_5 F_(IRQ1, IP0SR0_23_20) |
| 75 | #define GPSR0_4 F_(IRQ2, IP0SR0_19_16) |
| 76 | #define GPSR0_3 F_(IRQ3, IP0SR0_15_12) |
| 77 | #define GPSR0_2 F_(GP0_02, IP0SR0_11_8) |
| 78 | #define GPSR0_1 F_(GP0_01, IP0SR0_7_4) |
| 79 | #define GPSR0_0 F_(GP0_00, IP0SR0_3_0) |
| 80 | |
| 81 | /* GPSR1 */ |
| 82 | #define GPSR1_28 F_(HTX3, IP3SR1_19_16) |
| 83 | #define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12) |
| 84 | #define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8) |
| 85 | #define GPSR1_25 F_(HSCK3, IP3SR1_7_4) |
| 86 | #define GPSR1_24 F_(HRX3, IP3SR1_3_0) |
| 87 | #define GPSR1_23 F_(GP1_23, IP2SR1_31_28) |
| 88 | #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24) |
| 89 | #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20) |
| 90 | #define GPSR1_20 F_(SSI_SD, IP2SR1_19_16) |
| 91 | #define GPSR1_19 F_(SSI_WS, IP2SR1_15_12) |
| 92 | #define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8) |
| 93 | #define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4) |
| 94 | #define GPSR1_16 F_(HRX0, IP2SR1_3_0) |
| 95 | #define GPSR1_15 F_(HSCK0, IP1SR1_31_28) |
| 96 | #define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24) |
| 97 | #define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20) |
| 98 | #define GPSR1_12 F_(HTX0, IP1SR1_19_16) |
| 99 | #define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12) |
| 100 | #define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8) |
| 101 | #define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4) |
| 102 | #define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0) |
| 103 | #define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28) |
| 104 | #define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24) |
| 105 | #define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20) |
| 106 | #define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16) |
| 107 | #define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12) |
| 108 | #define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8) |
| 109 | #define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4) |
| 110 | #define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0) |
| 111 | |
| 112 | /* GPSR2 */ |
| 113 | #define GPSR2_19 F_(CANFD7_RX, IP2SR2_15_12) |
| 114 | #define GPSR2_18 F_(CANFD7_TX, IP2SR2_11_8) |
| 115 | #define GPSR2_17 F_(CANFD4_RX, IP2SR2_7_4) |
| 116 | #define GPSR2_16 F_(CANFD4_TX, IP2SR2_3_0) |
| 117 | #define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28) |
| 118 | #define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24) |
| 119 | #define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20) |
| 120 | #define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16) |
| 121 | #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12) |
| 122 | #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8) |
| 123 | #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4) |
| 124 | #define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0) |
| 125 | #define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28) |
| 126 | #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24) |
| 127 | #define GPSR2_5 F_(FXR_TXENB_N, IP0SR2_23_20) |
| 128 | #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16) |
| 129 | #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12) |
| 130 | #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8) |
| 131 | #define GPSR2_1 F_(FXR_TXENA_N, IP0SR2_7_4) |
| 132 | #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0) |
| 133 | |
| 134 | /* GPSR3 */ |
| 135 | #define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20) |
| 136 | #define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16) |
| 137 | #define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12) |
| 138 | #define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8) |
| 139 | #define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4) |
| 140 | #define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0) |
| 141 | #define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28) |
| 142 | #define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24) |
| 143 | #define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20) |
| 144 | #define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16) |
| 145 | #define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12) |
| 146 | #define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8) |
| 147 | #define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4) |
| 148 | #define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0) |
| 149 | #define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28) |
| 150 | #define GPSR3_14 F_(IPC_CLKOUT, IP1SR3_27_24) |
| 151 | #define GPSR3_13 F_(IPC_CLKIN, IP1SR3_23_20) |
| 152 | #define GPSR3_12 F_(SD_WP, IP1SR3_19_16) |
| 153 | #define GPSR3_11 F_(SD_CD, IP1SR3_15_12) |
| 154 | #define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8) |
| 155 | #define GPSR3_9 F_(MMC_D6, IP1SR3_7_4) |
| 156 | #define GPSR3_8 F_(MMC_D7, IP1SR3_3_0) |
| 157 | #define GPSR3_7 F_(MMC_D4, IP0SR3_31_28) |
| 158 | #define GPSR3_6 F_(MMC_D5, IP0SR3_27_24) |
| 159 | #define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20) |
| 160 | #define GPSR3_4 F_(MMC_DS, IP0SR3_19_16) |
| 161 | #define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12) |
| 162 | #define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8) |
| 163 | #define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4) |
| 164 | #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0) |
| 165 | |
| 166 | /* GPSR4 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 167 | #define GPSR4_24 F_(AVS1, IP3SR4_3_0) |
| 168 | #define GPSR4_23 F_(AVS0, IP2SR4_31_28) |
| 169 | #define GPSR4_22 F_(PCIE1_CLKREQ_N, IP2SR4_27_24) |
| 170 | #define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20) |
| 171 | #define GPSR4_20 F_(TSN0_TXCREFCLK, IP2SR4_19_16) |
| 172 | #define GPSR4_19 F_(TSN0_TD2, IP2SR4_15_12) |
| 173 | #define GPSR4_18 F_(TSN0_TD3, IP2SR4_11_8) |
| 174 | #define GPSR4_17 F_(TSN0_RD2, IP2SR4_7_4) |
| 175 | #define GPSR4_16 F_(TSN0_RD3, IP2SR4_3_0) |
| 176 | #define GPSR4_15 F_(TSN0_TD0, IP1SR4_31_28) |
| 177 | #define GPSR4_14 F_(TSN0_TD1, IP1SR4_27_24) |
| 178 | #define GPSR4_13 F_(TSN0_RD1, IP1SR4_23_20) |
| 179 | #define GPSR4_12 F_(TSN0_TXC, IP1SR4_19_16) |
| 180 | #define GPSR4_11 F_(TSN0_RXC, IP1SR4_15_12) |
| 181 | #define GPSR4_10 F_(TSN0_RD0, IP1SR4_11_8) |
| 182 | #define GPSR4_9 F_(TSN0_TX_CTL, IP1SR4_7_4) |
| 183 | #define GPSR4_8 F_(TSN0_AVTP_PPS0, IP1SR4_3_0) |
| 184 | #define GPSR4_7 F_(TSN0_RX_CTL, IP0SR4_31_28) |
| 185 | #define GPSR4_6 F_(TSN0_AVTP_CAPTURE, IP0SR4_27_24) |
| 186 | #define GPSR4_5 F_(TSN0_AVTP_MATCH, IP0SR4_23_20) |
| 187 | #define GPSR4_4 F_(TSN0_LINK, IP0SR4_19_16) |
| 188 | #define GPSR4_3 F_(TSN0_PHY_INT, IP0SR4_15_12) |
| 189 | #define GPSR4_2 F_(TSN0_AVTP_PPS1, IP0SR4_11_8) |
| 190 | #define GPSR4_1 F_(TSN0_MDC, IP0SR4_7_4) |
| 191 | #define GPSR4_0 F_(TSN0_MDIO, IP0SR4_3_0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 192 | |
| 193 | /* GPSR 5 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 194 | #define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16) |
| 195 | #define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12) |
| 196 | #define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8) |
| 197 | #define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4) |
| 198 | #define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0) |
| 199 | #define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28) |
| 200 | #define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24) |
| 201 | #define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20) |
| 202 | #define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16) |
| 203 | #define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12) |
| 204 | #define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8) |
| 205 | #define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4) |
| 206 | #define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0) |
| 207 | #define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28) |
| 208 | #define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24) |
| 209 | #define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20) |
| 210 | #define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16) |
| 211 | #define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12) |
| 212 | #define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8) |
| 213 | #define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4) |
| 214 | #define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 215 | |
| 216 | /* GPSR 6 */ |
| 217 | #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16) |
| 218 | #define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12) |
| 219 | #define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8) |
| 220 | #define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4) |
| 221 | #define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0) |
| 222 | #define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28) |
| 223 | #define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24) |
| 224 | #define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20) |
| 225 | #define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16) |
| 226 | #define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12) |
| 227 | #define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8) |
| 228 | #define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4) |
| 229 | #define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0) |
| 230 | #define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28) |
| 231 | #define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24) |
| 232 | #define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20) |
| 233 | #define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16) |
| 234 | #define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12) |
| 235 | #define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8) |
| 236 | #define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4) |
| 237 | #define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0) |
| 238 | |
| 239 | /* GPSR7 */ |
| 240 | #define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16) |
| 241 | #define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12) |
| 242 | #define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8) |
| 243 | #define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4) |
| 244 | #define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0) |
| 245 | #define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28) |
| 246 | #define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24) |
| 247 | #define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20) |
| 248 | #define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16) |
| 249 | #define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12) |
| 250 | #define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8) |
| 251 | #define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4) |
| 252 | #define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0) |
| 253 | #define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28) |
| 254 | #define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24) |
| 255 | #define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20) |
| 256 | #define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16) |
| 257 | #define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12) |
| 258 | #define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8) |
| 259 | #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4) |
| 260 | #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0) |
| 261 | |
| 262 | /* GPSR8 */ |
| 263 | #define GPSR8_13 F_(GP8_13, IP1SR8_23_20) |
| 264 | #define GPSR8_12 F_(GP8_12, IP1SR8_19_16) |
| 265 | #define GPSR8_11 F_(SDA5, IP1SR8_15_12) |
| 266 | #define GPSR8_10 F_(SCL5, IP1SR8_11_8) |
| 267 | #define GPSR8_9 F_(SDA4, IP1SR8_7_4) |
| 268 | #define GPSR8_8 F_(SCL4, IP1SR8_3_0) |
| 269 | #define GPSR8_7 F_(SDA3, IP0SR8_31_28) |
| 270 | #define GPSR8_6 F_(SCL3, IP0SR8_27_24) |
| 271 | #define GPSR8_5 F_(SDA2, IP0SR8_23_20) |
| 272 | #define GPSR8_4 F_(SCL2, IP0SR8_19_16) |
| 273 | #define GPSR8_3 F_(SDA1, IP0SR8_15_12) |
| 274 | #define GPSR8_2 F_(SCL1, IP0SR8_11_8) |
| 275 | #define GPSR8_1 F_(SDA0, IP0SR8_7_4) |
| 276 | #define GPSR8_0 F_(SCL0, IP0SR8_3_0) |
| 277 | |
| 278 | /* SR0 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 279 | /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 280 | #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 281 | #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 282 | #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 283 | #define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 284 | #define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 285 | #define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 286 | #define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 287 | #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 288 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 289 | /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 290 | #define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 291 | #define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 292 | #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 293 | #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 294 | #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 295 | #define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 296 | #define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 297 | #define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 298 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 299 | /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 300 | #define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 301 | #define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 302 | #define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 303 | |
| 304 | /* SR1 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 305 | /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 306 | #define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 307 | #define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 308 | #define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 309 | #define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 310 | #define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 311 | #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 312 | #define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 313 | #define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 314 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 315 | /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 316 | #define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 317 | #define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 318 | #define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 319 | #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 320 | #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 321 | #define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 322 | #define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 323 | #define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 324 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 325 | /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 326 | #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 327 | #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 328 | #define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 329 | #define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 330 | #define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 331 | #define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 332 | #define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 333 | #define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 334 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 335 | /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 336 | #define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 337 | #define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 338 | #define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 339 | #define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 340 | #define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 341 | |
| 342 | /* SR2 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 343 | /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 344 | #define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 345 | #define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 346 | #define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 347 | #define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 348 | #define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 349 | #define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 350 | #define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 351 | #define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 352 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 353 | /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 354 | #define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 355 | #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 356 | #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 357 | #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 358 | #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 359 | #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 360 | #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 361 | #define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 362 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 363 | /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 364 | #define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 365 | #define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 366 | #define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 367 | #define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 368 | |
| 369 | /* SR3 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 370 | /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 371 | #define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 372 | #define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 373 | #define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 374 | #define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 375 | #define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 376 | #define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 377 | #define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 378 | #define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 379 | |
| 380 | /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 381 | #define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 382 | #define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 383 | #define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 384 | #define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 385 | #define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 386 | #define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 387 | #define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 388 | #define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 389 | |
| 390 | /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 391 | #define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 392 | #define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 393 | #define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 394 | #define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 395 | #define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 396 | #define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 397 | #define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 398 | #define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 399 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 400 | /* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 401 | #define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 402 | #define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 403 | #define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 404 | #define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 405 | #define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 406 | #define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 407 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 408 | /* SR4 */ |
| 409 | /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 410 | #define IP0SR4_3_0 FM(TSN0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 411 | #define IP0SR4_7_4 FM(TSN0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 412 | #define IP0SR4_11_8 FM(TSN0_AVTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 413 | #define IP0SR4_15_12 FM(TSN0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 414 | #define IP0SR4_19_16 FM(TSN0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 415 | #define IP0SR4_23_20 FM(TSN0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 416 | #define IP0SR4_27_24 FM(TSN0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 417 | #define IP0SR4_31_28 FM(TSN0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 418 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 419 | /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 420 | #define IP1SR4_3_0 FM(TSN0_AVTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 421 | #define IP1SR4_7_4 FM(TSN0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 422 | #define IP1SR4_11_8 FM(TSN0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 423 | #define IP1SR4_15_12 FM(TSN0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 424 | #define IP1SR4_19_16 FM(TSN0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 425 | #define IP1SR4_23_20 FM(TSN0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 426 | #define IP1SR4_27_24 FM(TSN0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 427 | #define IP1SR4_31_28 FM(TSN0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 428 | |
| 429 | /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 430 | #define IP2SR4_3_0 FM(TSN0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 431 | #define IP2SR4_7_4 FM(TSN0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 432 | #define IP2SR4_11_8 FM(TSN0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 433 | #define IP2SR4_15_12 FM(TSN0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 434 | #define IP2SR4_19_16 FM(TSN0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 435 | #define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 436 | #define IP2SR4_27_24 FM(PCIE1_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 437 | #define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 438 | |
| 439 | /* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 440 | #define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 441 | |
| 442 | /* SR5 */ |
| 443 | /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 444 | #define IP0SR5_3_0 FM(AVB2_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 445 | #define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 446 | #define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 447 | #define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 448 | #define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 449 | #define IP0SR5_23_20 FM(AVB2_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 450 | #define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 451 | #define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 452 | |
| 453 | /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 454 | #define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 455 | #define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 456 | #define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 457 | #define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 458 | #define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 459 | #define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 460 | #define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 461 | #define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 462 | |
| 463 | /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 464 | #define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 465 | #define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 466 | #define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 467 | #define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 468 | #define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 469 | |
| 470 | /* SR6 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 471 | /* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 472 | #define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 473 | #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 474 | #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 475 | #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 476 | #define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 477 | #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 478 | #define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 479 | #define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 480 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 481 | /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 482 | #define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 483 | #define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 484 | #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 485 | #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 486 | #define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 487 | #define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 488 | #define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 489 | #define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 490 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 491 | /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 492 | #define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 493 | #define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 494 | #define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 495 | #define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 496 | #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 497 | |
| 498 | /* SR7 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 499 | /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 500 | #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 501 | #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 502 | #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 503 | #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 504 | #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 505 | #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 506 | #define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 507 | #define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 508 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 509 | /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 510 | #define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 511 | #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 512 | #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 513 | #define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 514 | #define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 515 | #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 516 | #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 517 | #define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 518 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 519 | /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 520 | #define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 521 | #define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 522 | #define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 523 | #define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 524 | #define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 525 | |
| 526 | /* SR8 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 527 | /* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 528 | #define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 529 | #define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 530 | #define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 531 | #define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 532 | #define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 533 | #define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 534 | #define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 535 | #define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 536 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 537 | /* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ |
| 538 | #define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 539 | #define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 540 | #define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 541 | #define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 542 | #define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 543 | #define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 544 | |
| 545 | #define PINMUX_GPSR \ |
| 546 | GPSR3_29 \ |
| 547 | GPSR1_28 GPSR3_28 \ |
| 548 | GPSR1_27 GPSR3_27 \ |
| 549 | GPSR1_26 GPSR3_26 \ |
| 550 | GPSR1_25 GPSR3_25 \ |
| 551 | GPSR1_24 GPSR3_24 GPSR4_24 \ |
| 552 | GPSR1_23 GPSR3_23 GPSR4_23 \ |
| 553 | GPSR1_22 GPSR3_22 GPSR4_22 \ |
| 554 | GPSR1_21 GPSR3_21 GPSR4_21 \ |
| 555 | GPSR1_20 GPSR3_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 \ |
| 556 | GPSR1_19 GPSR2_19 GPSR3_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 \ |
| 557 | GPSR0_18 GPSR1_18 GPSR2_18 GPSR3_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 \ |
| 558 | GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 \ |
| 559 | GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 \ |
| 560 | GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \ |
| 561 | GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \ |
| 562 | GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 \ |
| 563 | GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 \ |
| 564 | GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 \ |
| 565 | GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 \ |
| 566 | GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 \ |
| 567 | GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 \ |
| 568 | GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 \ |
| 569 | GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 \ |
| 570 | GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 \ |
| 571 | GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 \ |
| 572 | GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 \ |
| 573 | GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 \ |
| 574 | GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 \ |
| 575 | GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 |
| 576 | |
| 577 | #define PINMUX_IPSR \ |
| 578 | \ |
| 579 | FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \ |
| 580 | FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \ |
| 581 | FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \ |
| 582 | FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \ |
| 583 | FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \ |
| 584 | FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \ |
| 585 | FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \ |
| 586 | FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \ |
| 587 | \ |
| 588 | FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \ |
| 589 | FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \ |
| 590 | FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \ |
| 591 | FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \ |
| 592 | FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \ |
| 593 | FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 \ |
| 594 | FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \ |
| 595 | FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \ |
| 596 | \ |
| 597 | FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \ |
| 598 | FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \ |
| 599 | FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \ |
| 600 | FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \ |
| 601 | FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \ |
| 602 | FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \ |
| 603 | FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \ |
| 604 | FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \ |
| 605 | \ |
| 606 | FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \ |
| 607 | FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \ |
| 608 | FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \ |
| 609 | FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \ |
| 610 | FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \ |
| 611 | FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \ |
| 612 | FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \ |
| 613 | FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \ |
| 614 | \ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 615 | FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \ |
| 616 | FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \ |
| 617 | FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \ |
| 618 | FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \ |
| 619 | FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \ |
| 620 | FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \ |
| 621 | FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \ |
| 622 | FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \ |
| 623 | \ |
| 624 | FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \ |
| 625 | FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ |
| 626 | FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ |
| 627 | FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ |
| 628 | FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ |
| 629 | FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \ |
| 630 | FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \ |
| 631 | FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \ |
| 632 | \ |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 633 | FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \ |
| 634 | FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \ |
| 635 | FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \ |
| 636 | FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \ |
| 637 | FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \ |
| 638 | FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \ |
| 639 | FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \ |
| 640 | FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \ |
| 641 | \ |
| 642 | FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \ |
| 643 | FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \ |
| 644 | FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \ |
| 645 | FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \ |
| 646 | FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \ |
| 647 | FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \ |
| 648 | FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \ |
| 649 | FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \ |
| 650 | \ |
| 651 | FM(IP0SR8_3_0) IP0SR8_3_0 FM(IP1SR8_3_0) IP1SR8_3_0 \ |
| 652 | FM(IP0SR8_7_4) IP0SR8_7_4 FM(IP1SR8_7_4) IP1SR8_7_4 \ |
| 653 | FM(IP0SR8_11_8) IP0SR8_11_8 FM(IP1SR8_11_8) IP1SR8_11_8 \ |
| 654 | FM(IP0SR8_15_12) IP0SR8_15_12 FM(IP1SR8_15_12) IP1SR8_15_12 \ |
| 655 | FM(IP0SR8_19_16) IP0SR8_19_16 FM(IP1SR8_19_16) IP1SR8_19_16 \ |
| 656 | FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \ |
| 657 | FM(IP0SR8_27_24) IP0SR8_27_24 \ |
| 658 | FM(IP0SR8_31_28) IP0SR8_31_28 |
| 659 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 660 | /* MOD_SEL8 */ /* 0 */ /* 1 */ |
| 661 | #define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1) |
| 662 | #define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1) |
| 663 | #define MOD_SEL8_9 FM(SEL_SDA4_0) FM(SEL_SDA4_1) |
| 664 | #define MOD_SEL8_8 FM(SEL_SCL4_0) FM(SEL_SCL4_1) |
| 665 | #define MOD_SEL8_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1) |
| 666 | #define MOD_SEL8_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1) |
| 667 | #define MOD_SEL8_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1) |
| 668 | #define MOD_SEL8_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1) |
| 669 | #define MOD_SEL8_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1) |
| 670 | #define MOD_SEL8_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1) |
| 671 | #define MOD_SEL8_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1) |
| 672 | #define MOD_SEL8_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1) |
| 673 | |
| 674 | #define PINMUX_MOD_SELS \ |
| 675 | \ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 676 | MOD_SEL8_11 \ |
| 677 | MOD_SEL8_10 \ |
| 678 | MOD_SEL8_9 \ |
| 679 | MOD_SEL8_8 \ |
| 680 | MOD_SEL8_7 \ |
| 681 | MOD_SEL8_6 \ |
| 682 | MOD_SEL8_5 \ |
| 683 | MOD_SEL8_4 \ |
| 684 | MOD_SEL8_3 \ |
| 685 | MOD_SEL8_2 \ |
| 686 | MOD_SEL8_1 \ |
| 687 | MOD_SEL8_0 |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 688 | |
| 689 | enum { |
| 690 | PINMUX_RESERVED = 0, |
| 691 | |
| 692 | PINMUX_DATA_BEGIN, |
| 693 | GP_ALL(DATA), |
| 694 | PINMUX_DATA_END, |
| 695 | |
| 696 | #define F_(x, y) |
| 697 | #define FM(x) FN_##x, |
| 698 | PINMUX_FUNCTION_BEGIN, |
| 699 | GP_ALL(FN), |
| 700 | PINMUX_GPSR |
| 701 | PINMUX_IPSR |
| 702 | PINMUX_MOD_SELS |
| 703 | PINMUX_FUNCTION_END, |
| 704 | #undef F_ |
| 705 | #undef FM |
| 706 | |
| 707 | #define F_(x, y) |
| 708 | #define FM(x) x##_MARK, |
| 709 | PINMUX_MARK_BEGIN, |
| 710 | PINMUX_GPSR |
| 711 | PINMUX_IPSR |
| 712 | PINMUX_MOD_SELS |
| 713 | PINMUX_MARK_END, |
| 714 | #undef F_ |
| 715 | #undef FM |
| 716 | }; |
| 717 | |
| 718 | static const u16 pinmux_data[] = { |
| 719 | PINMUX_DATA_GP_ALL(), |
| 720 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 721 | /* IP0SR0 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 722 | PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 723 | PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A), |
| 724 | |
| 725 | PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1), |
| 726 | |
| 727 | PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2), |
| 728 | |
| 729 | PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3), |
| 730 | PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK), |
| 731 | |
| 732 | PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2), |
| 733 | PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD), |
| 734 | |
| 735 | PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1), |
| 736 | PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD), |
| 737 | |
| 738 | PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0), |
| 739 | PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC), |
| 740 | |
| 741 | PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2), |
| 742 | |
| 743 | /* IP1SR0 */ |
| 744 | PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1), |
| 745 | |
| 746 | PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC), |
| 747 | |
| 748 | PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD), |
| 749 | |
| 750 | PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK), |
| 751 | |
| 752 | PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD), |
| 753 | |
| 754 | PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2), |
| 755 | PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1), |
| 756 | PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_A), |
| 757 | |
| 758 | PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1), |
| 759 | PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1), |
| 760 | PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1), |
| 761 | |
| 762 | PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC), |
| 763 | PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1), |
| 764 | PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1), |
| 765 | |
| 766 | /* IP2SR0 */ |
| 767 | PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD), |
| 768 | PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N), |
| 769 | PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N), |
| 770 | |
| 771 | PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK), |
| 772 | PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N), |
| 773 | PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N), |
| 774 | |
| 775 | PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD), |
| 776 | PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1), |
| 777 | PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1), |
| 778 | |
| 779 | /* IP0SR1 */ |
| 780 | PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2), |
| 781 | PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A), |
| 782 | PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3), |
| 783 | |
| 784 | PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1), |
| 785 | PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_A), |
| 786 | PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3), |
| 787 | |
| 788 | PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC), |
| 789 | PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_A), |
| 790 | PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N), |
| 791 | |
| 792 | PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK), |
| 793 | PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A), |
| 794 | PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N), |
| 795 | |
| 796 | PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD), |
| 797 | PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A), |
| 798 | PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3), |
| 799 | |
| 800 | PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD), |
| 801 | |
| 802 | PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2), |
| 803 | PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X), |
| 804 | PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_X), |
| 805 | |
| 806 | PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1), |
| 807 | PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X), |
| 808 | PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_X), |
| 809 | |
| 810 | /* IP1SR1 */ |
| 811 | PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC), |
| 812 | PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_X), |
| 813 | PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_X), |
| 814 | PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B), |
| 815 | |
| 816 | PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD), |
| 817 | PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_X), |
| 818 | PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_X), |
| 819 | PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B), |
| 820 | |
| 821 | PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK), |
| 822 | PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X), |
| 823 | PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_X), |
| 824 | |
| 825 | PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD), |
| 826 | |
| 827 | PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0), |
| 828 | PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0), |
| 829 | |
| 830 | PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N), |
| 831 | PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N), |
| 832 | PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A), |
| 833 | |
| 834 | PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N), |
| 835 | PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N), |
| 836 | PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A), |
| 837 | |
| 838 | PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0), |
| 839 | PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0), |
| 840 | PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A), |
| 841 | |
| 842 | /* IP2SR1 */ |
| 843 | PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0), |
| 844 | PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0), |
| 845 | |
| 846 | PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK), |
| 847 | PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A), |
| 848 | |
| 849 | PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK), |
| 850 | PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3), |
| 851 | |
| 852 | PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS), |
| 853 | PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4), |
| 854 | |
| 855 | PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD), |
| 856 | PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_A), |
| 857 | |
| 858 | PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT), |
| 859 | PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A), |
| 860 | |
| 861 | PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN), |
| 862 | PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A), |
| 863 | |
| 864 | PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2), |
| 865 | PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1), |
| 866 | PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B), |
| 867 | |
| 868 | /* IP3SR1 */ |
| 869 | PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3), |
| 870 | PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A), |
| 871 | PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2), |
| 872 | |
| 873 | PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3), |
| 874 | PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A), |
| 875 | PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK), |
| 876 | PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A), |
| 877 | |
| 878 | PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N), |
| 879 | PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A), |
| 880 | PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD), |
| 881 | PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A), |
| 882 | |
| 883 | PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N), |
| 884 | PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A), |
| 885 | PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD), |
| 886 | |
| 887 | PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3), |
| 888 | PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A), |
| 889 | PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC), |
| 890 | |
| 891 | /* IP0SR2 */ |
| 892 | PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA), |
| 893 | PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX), |
| 894 | PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A), |
| 895 | |
| 896 | PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N), |
| 897 | PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX), |
| 898 | PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A), |
| 899 | |
| 900 | PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR), |
| 901 | PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX), |
| 902 | PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5), |
| 903 | |
| 904 | PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR), |
| 905 | PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX), |
| 906 | PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B), |
| 907 | |
| 908 | PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR), |
| 909 | |
| 910 | PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N), |
| 911 | |
| 912 | PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB), |
| 913 | |
| 914 | PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1), |
| 915 | PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX), |
| 916 | PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_B), |
| 917 | |
| 918 | /* IP1SR2 */ |
| 919 | PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0), |
| 920 | PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX), |
| 921 | PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A), |
| 922 | |
| 923 | PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK), |
| 924 | PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_X), |
| 925 | |
| 926 | PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX), |
| 927 | PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_X), |
| 928 | |
| 929 | PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX), |
| 930 | PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR), |
| 931 | |
| 932 | PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX), |
| 933 | PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2), |
| 934 | PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_A), |
| 935 | |
| 936 | PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX), |
| 937 | PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3), |
| 938 | PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B), |
| 939 | PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A), |
| 940 | |
| 941 | PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX), |
| 942 | PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B), |
| 943 | |
| 944 | PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX), |
| 945 | PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B), |
| 946 | |
| 947 | /* IP2SR2 */ |
| 948 | PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX), |
| 949 | PINMUX_IPSR_GPSR(IP2SR2_3_0, PWM4), |
| 950 | |
| 951 | PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD4_RX), |
| 952 | PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM5), |
| 953 | |
| 954 | PINMUX_IPSR_GPSR(IP2SR2_11_8, CANFD7_TX), |
| 955 | PINMUX_IPSR_GPSR(IP2SR2_11_8, PWM6), |
| 956 | |
| 957 | PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD7_RX), |
| 958 | PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM7), |
| 959 | |
| 960 | /* IP0SR3 */ |
| 961 | PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1), |
| 962 | PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0), |
| 963 | PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2), |
| 964 | PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK), |
| 965 | PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS), |
| 966 | PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3), |
| 967 | PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5), |
| 968 | PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4), |
| 969 | |
| 970 | /* IP1SR3 */ |
| 971 | PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7), |
| 972 | |
| 973 | PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6), |
| 974 | |
| 975 | PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD), |
| 976 | |
| 977 | PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD), |
| 978 | |
| 979 | PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP), |
| 980 | |
| 981 | PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN), |
| 982 | PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN), |
| 983 | PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A), |
| 984 | PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X), |
| 985 | |
| 986 | PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT), |
| 987 | PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT), |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 988 | PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 989 | PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X), |
| 990 | |
| 991 | PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL), |
| 992 | |
| 993 | /* IP2SR3 */ |
| 994 | PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3), |
| 995 | PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2), |
| 996 | PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1), |
| 997 | PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0), |
| 998 | PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK), |
| 999 | PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0), |
| 1000 | PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK), |
| 1001 | PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1), |
| 1002 | |
| 1003 | /* IP3SR3 */ |
| 1004 | PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2), |
| 1005 | PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL), |
| 1006 | PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3), |
| 1007 | PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N), |
| 1008 | PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N), |
| 1009 | PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N), |
| 1010 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1011 | /* IP0SR4 */ |
| 1012 | PINMUX_IPSR_GPSR(IP0SR4_3_0, TSN0_MDIO), |
| 1013 | PINMUX_IPSR_GPSR(IP0SR4_7_4, TSN0_MDC), |
| 1014 | PINMUX_IPSR_GPSR(IP0SR4_11_8, TSN0_AVTP_PPS1), |
| 1015 | PINMUX_IPSR_GPSR(IP0SR4_15_12, TSN0_PHY_INT), |
| 1016 | PINMUX_IPSR_GPSR(IP0SR4_19_16, TSN0_LINK), |
| 1017 | PINMUX_IPSR_GPSR(IP0SR4_23_20, TSN0_AVTP_MATCH), |
| 1018 | PINMUX_IPSR_GPSR(IP0SR4_27_24, TSN0_AVTP_CAPTURE), |
| 1019 | PINMUX_IPSR_GPSR(IP0SR4_31_28, TSN0_RX_CTL), |
| 1020 | |
| 1021 | /* IP1SR4 */ |
| 1022 | PINMUX_IPSR_GPSR(IP1SR4_3_0, TSN0_AVTP_PPS0), |
| 1023 | PINMUX_IPSR_GPSR(IP1SR4_7_4, TSN0_TX_CTL), |
| 1024 | PINMUX_IPSR_GPSR(IP1SR4_11_8, TSN0_RD0), |
| 1025 | PINMUX_IPSR_GPSR(IP1SR4_15_12, TSN0_RXC), |
| 1026 | PINMUX_IPSR_GPSR(IP1SR4_19_16, TSN0_TXC), |
| 1027 | PINMUX_IPSR_GPSR(IP1SR4_23_20, TSN0_RD1), |
| 1028 | PINMUX_IPSR_GPSR(IP1SR4_27_24, TSN0_TD1), |
| 1029 | PINMUX_IPSR_GPSR(IP1SR4_31_28, TSN0_TD0), |
| 1030 | |
| 1031 | /* IP2SR4 */ |
| 1032 | PINMUX_IPSR_GPSR(IP2SR4_3_0, TSN0_RD3), |
| 1033 | PINMUX_IPSR_GPSR(IP2SR4_7_4, TSN0_RD2), |
| 1034 | PINMUX_IPSR_GPSR(IP2SR4_11_8, TSN0_TD3), |
| 1035 | PINMUX_IPSR_GPSR(IP2SR4_15_12, TSN0_TD2), |
| 1036 | PINMUX_IPSR_GPSR(IP2SR4_19_16, TSN0_TXCREFCLK), |
| 1037 | PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N), |
| 1038 | PINMUX_IPSR_GPSR(IP2SR4_27_24, PCIE1_CLKREQ_N), |
| 1039 | PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0), |
| 1040 | |
| 1041 | /* IP3SR4 */ |
| 1042 | PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1), |
| 1043 | |
| 1044 | /* IP0SR5 */ |
| 1045 | PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS), |
| 1046 | PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE), |
| 1047 | PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH), |
| 1048 | PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK), |
| 1049 | PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT), |
| 1050 | PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC), |
| 1051 | PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC), |
| 1052 | PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK), |
| 1053 | |
| 1054 | /* IP1SR5 */ |
| 1055 | PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3), |
| 1056 | PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3), |
| 1057 | PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO), |
| 1058 | PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2), |
| 1059 | PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1), |
| 1060 | PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2), |
| 1061 | PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1), |
| 1062 | PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0), |
| 1063 | |
| 1064 | /* IP2SR5 */ |
| 1065 | PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC), |
| 1066 | PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0), |
| 1067 | PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC), |
| 1068 | PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL), |
| 1069 | PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL), |
| 1070 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1071 | /* IP0SR6 */ |
| 1072 | PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO), |
| 1073 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1074 | PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1075 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1076 | PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1077 | |
| 1078 | PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT), |
| 1079 | |
| 1080 | PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK), |
| 1081 | PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER), |
| 1082 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1083 | PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH), |
| 1084 | PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1085 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1086 | PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC), |
| 1087 | PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1088 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1089 | PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL), |
| 1090 | PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1091 | |
| 1092 | /* IP1SR6 */ |
| 1093 | PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC), |
| 1094 | PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC), |
| 1095 | |
| 1096 | PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL), |
| 1097 | PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV), |
| 1098 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1099 | PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS), |
| 1100 | PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1101 | |
| 1102 | PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE), |
| 1103 | PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS), |
| 1104 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1105 | PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1), |
| 1106 | PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1107 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1108 | PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0), |
| 1109 | PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1110 | |
| 1111 | PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1), |
| 1112 | PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1), |
| 1113 | |
| 1114 | PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0), |
| 1115 | PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0), |
| 1116 | |
| 1117 | /* IP2SR6 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1118 | PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2), |
| 1119 | PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1120 | |
| 1121 | PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2), |
| 1122 | PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2), |
| 1123 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1124 | PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3), |
| 1125 | PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1126 | |
| 1127 | PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3), |
| 1128 | PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3), |
| 1129 | |
| 1130 | PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK), |
| 1131 | |
| 1132 | /* IP0SR7 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1133 | PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS), |
| 1134 | PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1135 | |
| 1136 | PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE), |
| 1137 | PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS), |
| 1138 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1139 | PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), |
| 1140 | PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER), |
| 1141 | PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1142 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1143 | PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), |
| 1144 | PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1145 | |
| 1146 | PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK), |
| 1147 | PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER), |
| 1148 | |
| 1149 | PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT), |
| 1150 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1151 | PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2), |
| 1152 | PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1153 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1154 | PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1), |
| 1155 | PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1156 | |
| 1157 | /* IP1SR7 */ |
| 1158 | PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3), |
| 1159 | PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3), |
| 1160 | |
| 1161 | PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK), |
| 1162 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1163 | PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1164 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1165 | PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0), |
| 1166 | PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1167 | |
| 1168 | PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2), |
| 1169 | PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2), |
| 1170 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1171 | PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1172 | |
| 1173 | PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO), |
| 1174 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1175 | PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC), |
| 1176 | PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1177 | |
| 1178 | /* IP2SR7 */ |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1179 | PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL), |
| 1180 | PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1181 | |
| 1182 | PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1), |
| 1183 | PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1), |
| 1184 | |
| 1185 | PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0), |
| 1186 | PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0), |
| 1187 | |
| 1188 | PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC), |
| 1189 | PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC), |
| 1190 | |
| 1191 | PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL), |
| 1192 | PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV), |
| 1193 | |
| 1194 | /* IP0SR8 */ |
| 1195 | PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0), |
| 1196 | PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0), |
| 1197 | PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0), |
| 1198 | PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0), |
| 1199 | PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0), |
| 1200 | PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0), |
| 1201 | PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0), |
| 1202 | PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0), |
| 1203 | |
| 1204 | /* IP1SR8 */ |
| 1205 | PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0), |
| 1206 | PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0), |
| 1207 | PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0), |
| 1208 | |
| 1209 | PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_0), |
| 1210 | PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0), |
| 1211 | PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0), |
| 1212 | |
| 1213 | PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_0), |
| 1214 | PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0), |
| 1215 | PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0), |
| 1216 | |
| 1217 | PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_0), |
| 1218 | PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0), |
| 1219 | |
| 1220 | PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N), |
| 1221 | PINMUX_IPSR_GPSR(IP1SR8_19_16, TX4), |
| 1222 | |
| 1223 | PINMUX_IPSR_GPSR(IP1SR8_23_20, HSCK2), |
| 1224 | PINMUX_IPSR_GPSR(IP1SR8_23_20, RX4), |
| 1225 | }; |
| 1226 | |
| 1227 | /* |
| 1228 | * Pins not associated with a GPIO port. |
| 1229 | */ |
| 1230 | enum { |
| 1231 | GP_ASSIGN_LAST(), |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1232 | NOGP_ALL(), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1233 | }; |
| 1234 | |
| 1235 | static const struct sh_pfc_pin pinmux_pins[] = { |
| 1236 | PINMUX_GPIO_GP_ALL(), |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1237 | PINMUX_NOGP_ALL(), |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1238 | }; |
| 1239 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 1240 | /* - AUDIO CLOCK ----------------------------------------- */ |
| 1241 | static const unsigned int audio_clkin_pins[] = { |
| 1242 | /* CLK IN */ |
| 1243 | RCAR_GP_PIN(1, 22), |
| 1244 | }; |
| 1245 | static const unsigned int audio_clkin_mux[] = { |
| 1246 | AUDIO_CLKIN_MARK, |
| 1247 | }; |
| 1248 | static const unsigned int audio_clkout_pins[] = { |
| 1249 | /* CLK OUT */ |
| 1250 | RCAR_GP_PIN(1, 21), |
| 1251 | }; |
| 1252 | static const unsigned int audio_clkout_mux[] = { |
| 1253 | AUDIO_CLKOUT_MARK, |
| 1254 | }; |
| 1255 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 1256 | /* - AVB0 ------------------------------------------------ */ |
| 1257 | static const unsigned int avb0_link_pins[] = { |
| 1258 | /* AVB0_LINK */ |
| 1259 | RCAR_GP_PIN(7, 4), |
| 1260 | }; |
| 1261 | static const unsigned int avb0_link_mux[] = { |
| 1262 | AVB0_LINK_MARK, |
| 1263 | }; |
| 1264 | static const unsigned int avb0_magic_pins[] = { |
| 1265 | /* AVB0_MAGIC */ |
| 1266 | RCAR_GP_PIN(7, 10), |
| 1267 | }; |
| 1268 | static const unsigned int avb0_magic_mux[] = { |
| 1269 | AVB0_MAGIC_MARK, |
| 1270 | }; |
| 1271 | static const unsigned int avb0_phy_int_pins[] = { |
| 1272 | /* AVB0_PHY_INT */ |
| 1273 | RCAR_GP_PIN(7, 5), |
| 1274 | }; |
| 1275 | static const unsigned int avb0_phy_int_mux[] = { |
| 1276 | AVB0_PHY_INT_MARK, |
| 1277 | }; |
| 1278 | static const unsigned int avb0_mdio_pins[] = { |
| 1279 | /* AVB0_MDC, AVB0_MDIO */ |
| 1280 | RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), |
| 1281 | }; |
| 1282 | static const unsigned int avb0_mdio_mux[] = { |
| 1283 | AVB0_MDC_MARK, AVB0_MDIO_MARK, |
| 1284 | }; |
| 1285 | static const unsigned int avb0_rgmii_pins[] = { |
| 1286 | /* |
| 1287 | * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3, |
| 1288 | * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3, |
| 1289 | */ |
| 1290 | RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15), |
| 1291 | RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), |
| 1292 | RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3), |
| 1293 | RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), |
| 1294 | RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), |
| 1295 | RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), |
| 1296 | }; |
| 1297 | static const unsigned int avb0_rgmii_mux[] = { |
| 1298 | AVB0_TX_CTL_MARK, AVB0_TXC_MARK, |
| 1299 | AVB0_TD0_MARK, AVB0_TD1_MARK, |
| 1300 | AVB0_TD2_MARK, AVB0_TD3_MARK, |
| 1301 | AVB0_RX_CTL_MARK, AVB0_RXC_MARK, |
| 1302 | AVB0_RD0_MARK, AVB0_RD1_MARK, |
| 1303 | AVB0_RD2_MARK, AVB0_RD3_MARK, |
| 1304 | }; |
| 1305 | static const unsigned int avb0_txcrefclk_pins[] = { |
| 1306 | /* AVB0_TXCREFCLK */ |
| 1307 | RCAR_GP_PIN(7, 9), |
| 1308 | }; |
| 1309 | static const unsigned int avb0_txcrefclk_mux[] = { |
| 1310 | AVB0_TXCREFCLK_MARK, |
| 1311 | }; |
| 1312 | static const unsigned int avb0_avtp_pps_pins[] = { |
| 1313 | /* AVB0_AVTP_PPS */ |
| 1314 | RCAR_GP_PIN(7, 0), |
| 1315 | }; |
| 1316 | static const unsigned int avb0_avtp_pps_mux[] = { |
| 1317 | AVB0_AVTP_PPS_MARK, |
| 1318 | }; |
| 1319 | static const unsigned int avb0_avtp_capture_pins[] = { |
| 1320 | /* AVB0_AVTP_CAPTURE */ |
| 1321 | RCAR_GP_PIN(7, 1), |
| 1322 | }; |
| 1323 | static const unsigned int avb0_avtp_capture_mux[] = { |
| 1324 | AVB0_AVTP_CAPTURE_MARK, |
| 1325 | }; |
| 1326 | static const unsigned int avb0_avtp_match_pins[] = { |
| 1327 | /* AVB0_AVTP_MATCH */ |
| 1328 | RCAR_GP_PIN(7, 2), |
| 1329 | }; |
| 1330 | static const unsigned int avb0_avtp_match_mux[] = { |
| 1331 | AVB0_AVTP_MATCH_MARK, |
| 1332 | }; |
| 1333 | |
| 1334 | /* - AVB1 ------------------------------------------------ */ |
| 1335 | static const unsigned int avb1_link_pins[] = { |
| 1336 | /* AVB1_LINK */ |
| 1337 | RCAR_GP_PIN(6, 4), |
| 1338 | }; |
| 1339 | static const unsigned int avb1_link_mux[] = { |
| 1340 | AVB1_LINK_MARK, |
| 1341 | }; |
| 1342 | static const unsigned int avb1_magic_pins[] = { |
| 1343 | /* AVB1_MAGIC */ |
| 1344 | RCAR_GP_PIN(6, 1), |
| 1345 | }; |
| 1346 | static const unsigned int avb1_magic_mux[] = { |
| 1347 | AVB1_MAGIC_MARK, |
| 1348 | }; |
| 1349 | static const unsigned int avb1_phy_int_pins[] = { |
| 1350 | /* AVB1_PHY_INT */ |
| 1351 | RCAR_GP_PIN(6, 3), |
| 1352 | }; |
| 1353 | static const unsigned int avb1_phy_int_mux[] = { |
| 1354 | AVB1_PHY_INT_MARK, |
| 1355 | }; |
| 1356 | static const unsigned int avb1_mdio_pins[] = { |
| 1357 | /* AVB1_MDC, AVB1_MDIO */ |
| 1358 | RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0), |
| 1359 | }; |
| 1360 | static const unsigned int avb1_mdio_mux[] = { |
| 1361 | AVB1_MDC_MARK, AVB1_MDIO_MARK, |
| 1362 | }; |
| 1363 | static const unsigned int avb1_rgmii_pins[] = { |
| 1364 | /* |
| 1365 | * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3, |
| 1366 | * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3, |
| 1367 | */ |
| 1368 | RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), |
| 1369 | RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), |
| 1370 | RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18), |
| 1371 | RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8), |
| 1372 | RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14), |
| 1373 | RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), |
| 1374 | }; |
| 1375 | static const unsigned int avb1_rgmii_mux[] = { |
| 1376 | AVB1_TX_CTL_MARK, AVB1_TXC_MARK, |
| 1377 | AVB1_TD0_MARK, AVB1_TD1_MARK, |
| 1378 | AVB1_TD2_MARK, AVB1_TD3_MARK, |
| 1379 | AVB1_RX_CTL_MARK, AVB1_RXC_MARK, |
| 1380 | AVB1_RD0_MARK, AVB1_RD1_MARK, |
| 1381 | AVB1_RD2_MARK, AVB1_RD3_MARK, |
| 1382 | }; |
| 1383 | static const unsigned int avb1_txcrefclk_pins[] = { |
| 1384 | /* AVB1_TXCREFCLK */ |
| 1385 | RCAR_GP_PIN(6, 20), |
| 1386 | }; |
| 1387 | static const unsigned int avb1_txcrefclk_mux[] = { |
| 1388 | AVB1_TXCREFCLK_MARK, |
| 1389 | }; |
| 1390 | static const unsigned int avb1_avtp_pps_pins[] = { |
| 1391 | /* AVB1_AVTP_PPS */ |
| 1392 | RCAR_GP_PIN(6, 10), |
| 1393 | }; |
| 1394 | static const unsigned int avb1_avtp_pps_mux[] = { |
| 1395 | AVB1_AVTP_PPS_MARK, |
| 1396 | }; |
| 1397 | static const unsigned int avb1_avtp_capture_pins[] = { |
| 1398 | /* AVB1_AVTP_CAPTURE */ |
| 1399 | RCAR_GP_PIN(6, 11), |
| 1400 | }; |
| 1401 | static const unsigned int avb1_avtp_capture_mux[] = { |
| 1402 | AVB1_AVTP_CAPTURE_MARK, |
| 1403 | }; |
| 1404 | static const unsigned int avb1_avtp_match_pins[] = { |
| 1405 | /* AVB1_AVTP_MATCH */ |
| 1406 | RCAR_GP_PIN(6, 5), |
| 1407 | }; |
| 1408 | static const unsigned int avb1_avtp_match_mux[] = { |
| 1409 | AVB1_AVTP_MATCH_MARK, |
| 1410 | }; |
| 1411 | |
| 1412 | /* - AVB2 ------------------------------------------------ */ |
| 1413 | static const unsigned int avb2_link_pins[] = { |
| 1414 | /* AVB2_LINK */ |
| 1415 | RCAR_GP_PIN(5, 3), |
| 1416 | }; |
| 1417 | static const unsigned int avb2_link_mux[] = { |
| 1418 | AVB2_LINK_MARK, |
| 1419 | }; |
| 1420 | static const unsigned int avb2_magic_pins[] = { |
| 1421 | /* AVB2_MAGIC */ |
| 1422 | RCAR_GP_PIN(5, 5), |
| 1423 | }; |
| 1424 | static const unsigned int avb2_magic_mux[] = { |
| 1425 | AVB2_MAGIC_MARK, |
| 1426 | }; |
| 1427 | static const unsigned int avb2_phy_int_pins[] = { |
| 1428 | /* AVB2_PHY_INT */ |
| 1429 | RCAR_GP_PIN(5, 4), |
| 1430 | }; |
| 1431 | static const unsigned int avb2_phy_int_mux[] = { |
| 1432 | AVB2_PHY_INT_MARK, |
| 1433 | }; |
| 1434 | static const unsigned int avb2_mdio_pins[] = { |
| 1435 | /* AVB2_MDC, AVB2_MDIO */ |
| 1436 | RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10), |
| 1437 | }; |
| 1438 | static const unsigned int avb2_mdio_mux[] = { |
| 1439 | AVB2_MDC_MARK, AVB2_MDIO_MARK, |
| 1440 | }; |
| 1441 | static const unsigned int avb2_rgmii_pins[] = { |
| 1442 | /* |
| 1443 | * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3, |
| 1444 | * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3, |
| 1445 | */ |
| 1446 | RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16), |
| 1447 | RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12), |
| 1448 | RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8), |
| 1449 | RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18), |
| 1450 | RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14), |
| 1451 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9), |
| 1452 | }; |
| 1453 | static const unsigned int avb2_rgmii_mux[] = { |
| 1454 | AVB2_TX_CTL_MARK, AVB2_TXC_MARK, |
| 1455 | AVB2_TD0_MARK, AVB2_TD1_MARK, |
| 1456 | AVB2_TD2_MARK, AVB2_TD3_MARK, |
| 1457 | AVB2_RX_CTL_MARK, AVB2_RXC_MARK, |
| 1458 | AVB2_RD0_MARK, AVB2_RD1_MARK, |
| 1459 | AVB2_RD2_MARK, AVB2_RD3_MARK, |
| 1460 | }; |
| 1461 | static const unsigned int avb2_txcrefclk_pins[] = { |
| 1462 | /* AVB2_TXCREFCLK */ |
| 1463 | RCAR_GP_PIN(5, 7), |
| 1464 | }; |
| 1465 | static const unsigned int avb2_txcrefclk_mux[] = { |
| 1466 | AVB2_TXCREFCLK_MARK, |
| 1467 | }; |
| 1468 | static const unsigned int avb2_avtp_pps_pins[] = { |
| 1469 | /* AVB2_AVTP_PPS */ |
| 1470 | RCAR_GP_PIN(5, 0), |
| 1471 | }; |
| 1472 | static const unsigned int avb2_avtp_pps_mux[] = { |
| 1473 | AVB2_AVTP_PPS_MARK, |
| 1474 | }; |
| 1475 | static const unsigned int avb2_avtp_capture_pins[] = { |
| 1476 | /* AVB2_AVTP_CAPTURE */ |
| 1477 | RCAR_GP_PIN(5, 1), |
| 1478 | }; |
| 1479 | static const unsigned int avb2_avtp_capture_mux[] = { |
| 1480 | AVB2_AVTP_CAPTURE_MARK, |
| 1481 | }; |
| 1482 | static const unsigned int avb2_avtp_match_pins[] = { |
| 1483 | /* AVB2_AVTP_MATCH */ |
| 1484 | RCAR_GP_PIN(5, 2), |
| 1485 | }; |
| 1486 | static const unsigned int avb2_avtp_match_mux[] = { |
| 1487 | AVB2_AVTP_MATCH_MARK, |
| 1488 | }; |
| 1489 | |
| 1490 | /* - CANFD0 ----------------------------------------------------------------- */ |
| 1491 | static const unsigned int canfd0_data_pins[] = { |
| 1492 | /* CANFD0_TX, CANFD0_RX */ |
| 1493 | RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), |
| 1494 | }; |
| 1495 | static const unsigned int canfd0_data_mux[] = { |
| 1496 | CANFD0_TX_MARK, CANFD0_RX_MARK, |
| 1497 | }; |
| 1498 | |
| 1499 | /* - CANFD1 ----------------------------------------------------------------- */ |
| 1500 | static const unsigned int canfd1_data_pins[] = { |
| 1501 | /* CANFD1_TX, CANFD1_RX */ |
| 1502 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), |
| 1503 | }; |
| 1504 | static const unsigned int canfd1_data_mux[] = { |
| 1505 | CANFD1_TX_MARK, CANFD1_RX_MARK, |
| 1506 | }; |
| 1507 | |
| 1508 | /* - CANFD2 ----------------------------------------------------------------- */ |
| 1509 | static const unsigned int canfd2_data_pins[] = { |
| 1510 | /* CANFD2_TX, CANFD2_RX */ |
| 1511 | RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), |
| 1512 | }; |
| 1513 | static const unsigned int canfd2_data_mux[] = { |
| 1514 | CANFD2_TX_MARK, CANFD2_RX_MARK, |
| 1515 | }; |
| 1516 | |
| 1517 | /* - CANFD3 ----------------------------------------------------------------- */ |
| 1518 | static const unsigned int canfd3_data_pins[] = { |
| 1519 | /* CANFD3_TX, CANFD3_RX */ |
| 1520 | RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), |
| 1521 | }; |
| 1522 | static const unsigned int canfd3_data_mux[] = { |
| 1523 | CANFD3_TX_MARK, CANFD3_RX_MARK, |
| 1524 | }; |
| 1525 | |
| 1526 | /* - CANFD4 ----------------------------------------------------------------- */ |
| 1527 | static const unsigned int canfd4_data_pins[] = { |
| 1528 | /* CANFD4_TX, CANFD4_RX */ |
| 1529 | RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), |
| 1530 | }; |
| 1531 | static const unsigned int canfd4_data_mux[] = { |
| 1532 | CANFD4_TX_MARK, CANFD4_RX_MARK, |
| 1533 | }; |
| 1534 | |
| 1535 | /* - CANFD5 ----------------------------------------------------------------- */ |
| 1536 | static const unsigned int canfd5_data_pins[] = { |
| 1537 | /* CANFD5_TX, CANFD5_RX */ |
| 1538 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), |
| 1539 | }; |
| 1540 | static const unsigned int canfd5_data_mux[] = { |
| 1541 | CANFD5_TX_MARK, CANFD5_RX_MARK, |
| 1542 | }; |
| 1543 | |
| 1544 | /* - CANFD5_B ----------------------------------------------------------------- */ |
| 1545 | static const unsigned int canfd5_data_b_pins[] = { |
| 1546 | /* CANFD5_TX_B, CANFD5_RX_B */ |
| 1547 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), |
| 1548 | }; |
| 1549 | static const unsigned int canfd5_data_b_mux[] = { |
| 1550 | CANFD5_TX_B_MARK, CANFD5_RX_B_MARK, |
| 1551 | }; |
| 1552 | |
| 1553 | /* - CANFD6 ----------------------------------------------------------------- */ |
| 1554 | static const unsigned int canfd6_data_pins[] = { |
| 1555 | /* CANFD6_TX, CANFD6_RX */ |
| 1556 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), |
| 1557 | }; |
| 1558 | static const unsigned int canfd6_data_mux[] = { |
| 1559 | CANFD6_TX_MARK, CANFD6_RX_MARK, |
| 1560 | }; |
| 1561 | |
| 1562 | /* - CANFD7 ----------------------------------------------------------------- */ |
| 1563 | static const unsigned int canfd7_data_pins[] = { |
| 1564 | /* CANFD7_TX, CANFD7_RX */ |
| 1565 | RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), |
| 1566 | }; |
| 1567 | static const unsigned int canfd7_data_mux[] = { |
| 1568 | CANFD7_TX_MARK, CANFD7_RX_MARK, |
| 1569 | }; |
| 1570 | |
| 1571 | /* - CANFD Clock ------------------------------------------------------------ */ |
| 1572 | static const unsigned int can_clk_pins[] = { |
| 1573 | /* CAN_CLK */ |
| 1574 | RCAR_GP_PIN(2, 9), |
| 1575 | }; |
| 1576 | static const unsigned int can_clk_mux[] = { |
| 1577 | CAN_CLK_MARK, |
| 1578 | }; |
| 1579 | |
| 1580 | /* - HSCIF0 ----------------------------------------------------------------- */ |
| 1581 | static const unsigned int hscif0_data_pins[] = { |
| 1582 | /* HRX0, HTX0 */ |
| 1583 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12), |
| 1584 | }; |
| 1585 | static const unsigned int hscif0_data_mux[] = { |
| 1586 | HRX0_MARK, HTX0_MARK, |
| 1587 | }; |
| 1588 | static const unsigned int hscif0_clk_pins[] = { |
| 1589 | /* HSCK0 */ |
| 1590 | RCAR_GP_PIN(1, 15), |
| 1591 | }; |
| 1592 | static const unsigned int hscif0_clk_mux[] = { |
| 1593 | HSCK0_MARK, |
| 1594 | }; |
| 1595 | static const unsigned int hscif0_ctrl_pins[] = { |
| 1596 | /* HRTS0_N, HCTS0_N */ |
| 1597 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), |
| 1598 | }; |
| 1599 | static const unsigned int hscif0_ctrl_mux[] = { |
| 1600 | HRTS0_N_MARK, HCTS0_N_MARK, |
| 1601 | }; |
| 1602 | |
| 1603 | /* - HSCIF1 ----------------------------------------------------------------- */ |
| 1604 | static const unsigned int hscif1_data_pins[] = { |
| 1605 | /* HRX1, HTX1 */ |
| 1606 | RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), |
| 1607 | }; |
| 1608 | static const unsigned int hscif1_data_mux[] = { |
| 1609 | HRX1_MARK, HTX1_MARK, |
| 1610 | }; |
| 1611 | static const unsigned int hscif1_clk_pins[] = { |
| 1612 | /* HSCK1 */ |
| 1613 | RCAR_GP_PIN(0, 18), |
| 1614 | }; |
| 1615 | static const unsigned int hscif1_clk_mux[] = { |
| 1616 | HSCK1_MARK, |
| 1617 | }; |
| 1618 | static const unsigned int hscif1_ctrl_pins[] = { |
| 1619 | /* HRTS1_N, HCTS1_N */ |
| 1620 | RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), |
| 1621 | }; |
| 1622 | static const unsigned int hscif1_ctrl_mux[] = { |
| 1623 | HRTS1_N_MARK, HCTS1_N_MARK, |
| 1624 | }; |
| 1625 | |
| 1626 | /* - HSCIF1_X---------------------------------------------------------------- */ |
| 1627 | static const unsigned int hscif1_data_x_pins[] = { |
| 1628 | /* HRX1_X, HTX1_X */ |
| 1629 | RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), |
| 1630 | }; |
| 1631 | static const unsigned int hscif1_data_x_mux[] = { |
| 1632 | HRX1_X_MARK, HTX1_X_MARK, |
| 1633 | }; |
| 1634 | static const unsigned int hscif1_clk_x_pins[] = { |
| 1635 | /* HSCK1_X */ |
| 1636 | RCAR_GP_PIN(1, 10), |
| 1637 | }; |
| 1638 | static const unsigned int hscif1_clk_x_mux[] = { |
| 1639 | HSCK1_X_MARK, |
| 1640 | }; |
| 1641 | static const unsigned int hscif1_ctrl_x_pins[] = { |
| 1642 | /* HRTS1_N_X, HCTS1_N_X */ |
| 1643 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), |
| 1644 | }; |
| 1645 | static const unsigned int hscif1_ctrl_x_mux[] = { |
| 1646 | HRTS1_N_X_MARK, HCTS1_N_X_MARK, |
| 1647 | }; |
| 1648 | |
| 1649 | /* - HSCIF2 ----------------------------------------------------------------- */ |
| 1650 | static const unsigned int hscif2_data_pins[] = { |
| 1651 | /* HRX2, HTX2 */ |
| 1652 | RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), |
| 1653 | }; |
| 1654 | static const unsigned int hscif2_data_mux[] = { |
| 1655 | HRX2_MARK, HTX2_MARK, |
| 1656 | }; |
| 1657 | static const unsigned int hscif2_clk_pins[] = { |
| 1658 | /* HSCK2 */ |
| 1659 | RCAR_GP_PIN(8, 13), |
| 1660 | }; |
| 1661 | static const unsigned int hscif2_clk_mux[] = { |
| 1662 | HSCK2_MARK, |
| 1663 | }; |
| 1664 | static const unsigned int hscif2_ctrl_pins[] = { |
| 1665 | /* HRTS2_N, HCTS2_N */ |
| 1666 | RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12), |
| 1667 | }; |
| 1668 | static const unsigned int hscif2_ctrl_mux[] = { |
| 1669 | HRTS2_N_MARK, HCTS2_N_MARK, |
| 1670 | }; |
| 1671 | |
| 1672 | /* - HSCIF3 ----------------------------------------------------------------- */ |
| 1673 | static const unsigned int hscif3_data_pins[] = { |
| 1674 | /* HRX3, HTX3 */ |
| 1675 | RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28), |
| 1676 | }; |
| 1677 | static const unsigned int hscif3_data_mux[] = { |
| 1678 | HRX3_MARK, HTX3_MARK, |
| 1679 | }; |
| 1680 | static const unsigned int hscif3_clk_pins[] = { |
| 1681 | /* HSCK3 */ |
| 1682 | RCAR_GP_PIN(1, 25), |
| 1683 | }; |
| 1684 | static const unsigned int hscif3_clk_mux[] = { |
| 1685 | HSCK3_MARK, |
| 1686 | }; |
| 1687 | static const unsigned int hscif3_ctrl_pins[] = { |
| 1688 | /* HRTS3_N, HCTS3_N */ |
| 1689 | RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27), |
| 1690 | }; |
| 1691 | static const unsigned int hscif3_ctrl_mux[] = { |
| 1692 | HRTS3_N_MARK, HCTS3_N_MARK, |
| 1693 | }; |
| 1694 | |
| 1695 | /* - HSCIF3_A ----------------------------------------------------------------- */ |
| 1696 | static const unsigned int hscif3_data_a_pins[] = { |
| 1697 | /* HRX3_A, HTX3_A */ |
| 1698 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), |
| 1699 | }; |
| 1700 | static const unsigned int hscif3_data_a_mux[] = { |
| 1701 | HRX3_A_MARK, HTX3_A_MARK, |
| 1702 | }; |
| 1703 | static const unsigned int hscif3_clk_a_pins[] = { |
| 1704 | /* HSCK3_A */ |
| 1705 | RCAR_GP_PIN(1, 3), |
| 1706 | }; |
| 1707 | static const unsigned int hscif3_clk_a_mux[] = { |
| 1708 | HSCK3_A_MARK, |
| 1709 | }; |
| 1710 | static const unsigned int hscif3_ctrl_a_pins[] = { |
| 1711 | /* HRTS3_N_A, HCTS3_N_A */ |
| 1712 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), |
| 1713 | }; |
| 1714 | static const unsigned int hscif3_ctrl_a_mux[] = { |
| 1715 | HRTS3_N_A_MARK, HCTS3_N_A_MARK, |
| 1716 | }; |
| 1717 | |
| 1718 | /* - I2C0 ------------------------------------------------------------------- */ |
| 1719 | static const unsigned int i2c0_pins[] = { |
| 1720 | /* SDA0, SCL0 */ |
| 1721 | RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0), |
| 1722 | }; |
| 1723 | static const unsigned int i2c0_mux[] = { |
| 1724 | SDA0_MARK, SCL0_MARK, |
| 1725 | }; |
| 1726 | |
| 1727 | /* - I2C1 ------------------------------------------------------------------- */ |
| 1728 | static const unsigned int i2c1_pins[] = { |
| 1729 | /* SDA1, SCL1 */ |
| 1730 | RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2), |
| 1731 | }; |
| 1732 | static const unsigned int i2c1_mux[] = { |
| 1733 | SDA1_MARK, SCL1_MARK, |
| 1734 | }; |
| 1735 | |
| 1736 | /* - I2C2 ------------------------------------------------------------------- */ |
| 1737 | static const unsigned int i2c2_pins[] = { |
| 1738 | /* SDA2, SCL2 */ |
| 1739 | RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4), |
| 1740 | }; |
| 1741 | static const unsigned int i2c2_mux[] = { |
| 1742 | SDA2_MARK, SCL2_MARK, |
| 1743 | }; |
| 1744 | |
| 1745 | /* - I2C3 ------------------------------------------------------------------- */ |
| 1746 | static const unsigned int i2c3_pins[] = { |
| 1747 | /* SDA3, SCL3 */ |
| 1748 | RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6), |
| 1749 | }; |
| 1750 | static const unsigned int i2c3_mux[] = { |
| 1751 | SDA3_MARK, SCL3_MARK, |
| 1752 | }; |
| 1753 | |
| 1754 | /* - I2C4 ------------------------------------------------------------------- */ |
| 1755 | static const unsigned int i2c4_pins[] = { |
| 1756 | /* SDA4, SCL4 */ |
| 1757 | RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8), |
| 1758 | }; |
| 1759 | static const unsigned int i2c4_mux[] = { |
| 1760 | SDA4_MARK, SCL4_MARK, |
| 1761 | }; |
| 1762 | |
| 1763 | /* - I2C5 ------------------------------------------------------------------- */ |
| 1764 | static const unsigned int i2c5_pins[] = { |
| 1765 | /* SDA5, SCL5 */ |
| 1766 | RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10), |
| 1767 | }; |
| 1768 | static const unsigned int i2c5_mux[] = { |
| 1769 | SDA5_MARK, SCL5_MARK, |
| 1770 | }; |
| 1771 | |
| 1772 | /* - MMC -------------------------------------------------------------------- */ |
| 1773 | static const unsigned int mmc_data_pins[] = { |
| 1774 | /* MMC_SD_D[0:3], MMC_D[4:7] */ |
| 1775 | RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), |
| 1776 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5), |
| 1777 | RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), |
| 1778 | RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8), |
| 1779 | }; |
| 1780 | static const unsigned int mmc_data_mux[] = { |
| 1781 | MMC_SD_D0_MARK, MMC_SD_D1_MARK, |
| 1782 | MMC_SD_D2_MARK, MMC_SD_D3_MARK, |
| 1783 | MMC_D4_MARK, MMC_D5_MARK, |
| 1784 | MMC_D6_MARK, MMC_D7_MARK, |
| 1785 | }; |
| 1786 | static const unsigned int mmc_ctrl_pins[] = { |
| 1787 | /* MMC_SD_CLK, MMC_SD_CMD */ |
| 1788 | RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10), |
| 1789 | }; |
| 1790 | static const unsigned int mmc_ctrl_mux[] = { |
| 1791 | MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, |
| 1792 | }; |
| 1793 | static const unsigned int mmc_cd_pins[] = { |
| 1794 | /* SD_CD */ |
| 1795 | RCAR_GP_PIN(3, 11), |
| 1796 | }; |
| 1797 | static const unsigned int mmc_cd_mux[] = { |
| 1798 | SD_CD_MARK, |
| 1799 | }; |
| 1800 | static const unsigned int mmc_wp_pins[] = { |
| 1801 | /* SD_WP */ |
| 1802 | RCAR_GP_PIN(3, 12), |
| 1803 | }; |
| 1804 | static const unsigned int mmc_wp_mux[] = { |
| 1805 | SD_WP_MARK, |
| 1806 | }; |
| 1807 | static const unsigned int mmc_ds_pins[] = { |
| 1808 | /* MMC_DS */ |
| 1809 | RCAR_GP_PIN(3, 4), |
| 1810 | }; |
| 1811 | static const unsigned int mmc_ds_mux[] = { |
| 1812 | MMC_DS_MARK, |
| 1813 | }; |
| 1814 | |
| 1815 | /* - MSIOF0 ----------------------------------------------------------------- */ |
| 1816 | static const unsigned int msiof0_clk_pins[] = { |
| 1817 | /* MSIOF0_SCK */ |
| 1818 | RCAR_GP_PIN(1, 10), |
| 1819 | }; |
| 1820 | static const unsigned int msiof0_clk_mux[] = { |
| 1821 | MSIOF0_SCK_MARK, |
| 1822 | }; |
| 1823 | static const unsigned int msiof0_sync_pins[] = { |
| 1824 | /* MSIOF0_SYNC */ |
| 1825 | RCAR_GP_PIN(1, 8), |
| 1826 | }; |
| 1827 | static const unsigned int msiof0_sync_mux[] = { |
| 1828 | MSIOF0_SYNC_MARK, |
| 1829 | }; |
| 1830 | static const unsigned int msiof0_ss1_pins[] = { |
| 1831 | /* MSIOF0_SS1 */ |
| 1832 | RCAR_GP_PIN(1, 7), |
| 1833 | }; |
| 1834 | static const unsigned int msiof0_ss1_mux[] = { |
| 1835 | MSIOF0_SS1_MARK, |
| 1836 | }; |
| 1837 | static const unsigned int msiof0_ss2_pins[] = { |
| 1838 | /* MSIOF0_SS2 */ |
| 1839 | RCAR_GP_PIN(1, 6), |
| 1840 | }; |
| 1841 | static const unsigned int msiof0_ss2_mux[] = { |
| 1842 | MSIOF0_SS2_MARK, |
| 1843 | }; |
| 1844 | static const unsigned int msiof0_txd_pins[] = { |
| 1845 | /* MSIOF0_TXD */ |
| 1846 | RCAR_GP_PIN(1, 9), |
| 1847 | }; |
| 1848 | static const unsigned int msiof0_txd_mux[] = { |
| 1849 | MSIOF0_TXD_MARK, |
| 1850 | }; |
| 1851 | static const unsigned int msiof0_rxd_pins[] = { |
| 1852 | /* MSIOF0_RXD */ |
| 1853 | RCAR_GP_PIN(1, 11), |
| 1854 | }; |
| 1855 | static const unsigned int msiof0_rxd_mux[] = { |
| 1856 | MSIOF0_RXD_MARK, |
| 1857 | }; |
| 1858 | |
| 1859 | /* - MSIOF1 ----------------------------------------------------------------- */ |
| 1860 | static const unsigned int msiof1_clk_pins[] = { |
| 1861 | /* MSIOF1_SCK */ |
| 1862 | RCAR_GP_PIN(1, 3), |
| 1863 | }; |
| 1864 | static const unsigned int msiof1_clk_mux[] = { |
| 1865 | MSIOF1_SCK_MARK, |
| 1866 | }; |
| 1867 | static const unsigned int msiof1_sync_pins[] = { |
| 1868 | /* MSIOF1_SYNC */ |
| 1869 | RCAR_GP_PIN(1, 2), |
| 1870 | }; |
| 1871 | static const unsigned int msiof1_sync_mux[] = { |
| 1872 | MSIOF1_SYNC_MARK, |
| 1873 | }; |
| 1874 | static const unsigned int msiof1_ss1_pins[] = { |
| 1875 | /* MSIOF1_SS1 */ |
| 1876 | RCAR_GP_PIN(1, 1), |
| 1877 | }; |
| 1878 | static const unsigned int msiof1_ss1_mux[] = { |
| 1879 | MSIOF1_SS1_MARK, |
| 1880 | }; |
| 1881 | static const unsigned int msiof1_ss2_pins[] = { |
| 1882 | /* MSIOF1_SS2 */ |
| 1883 | RCAR_GP_PIN(1, 0), |
| 1884 | }; |
| 1885 | static const unsigned int msiof1_ss2_mux[] = { |
| 1886 | MSIOF1_SS2_MARK, |
| 1887 | }; |
| 1888 | static const unsigned int msiof1_txd_pins[] = { |
| 1889 | /* MSIOF1_TXD */ |
| 1890 | RCAR_GP_PIN(1, 4), |
| 1891 | }; |
| 1892 | static const unsigned int msiof1_txd_mux[] = { |
| 1893 | MSIOF1_TXD_MARK, |
| 1894 | }; |
| 1895 | static const unsigned int msiof1_rxd_pins[] = { |
| 1896 | /* MSIOF1_RXD */ |
| 1897 | RCAR_GP_PIN(1, 5), |
| 1898 | }; |
| 1899 | static const unsigned int msiof1_rxd_mux[] = { |
| 1900 | MSIOF1_RXD_MARK, |
| 1901 | }; |
| 1902 | |
| 1903 | /* - MSIOF2 ----------------------------------------------------------------- */ |
| 1904 | static const unsigned int msiof2_clk_pins[] = { |
| 1905 | /* MSIOF2_SCK */ |
| 1906 | RCAR_GP_PIN(0, 17), |
| 1907 | }; |
| 1908 | static const unsigned int msiof2_clk_mux[] = { |
| 1909 | MSIOF2_SCK_MARK, |
| 1910 | }; |
| 1911 | static const unsigned int msiof2_sync_pins[] = { |
| 1912 | /* MSIOF2_SYNC */ |
| 1913 | RCAR_GP_PIN(0, 15), |
| 1914 | }; |
| 1915 | static const unsigned int msiof2_sync_mux[] = { |
| 1916 | MSIOF2_SYNC_MARK, |
| 1917 | }; |
| 1918 | static const unsigned int msiof2_ss1_pins[] = { |
| 1919 | /* MSIOF2_SS1 */ |
| 1920 | RCAR_GP_PIN(0, 14), |
| 1921 | }; |
| 1922 | static const unsigned int msiof2_ss1_mux[] = { |
| 1923 | MSIOF2_SS1_MARK, |
| 1924 | }; |
| 1925 | static const unsigned int msiof2_ss2_pins[] = { |
| 1926 | /* MSIOF2_SS2 */ |
| 1927 | RCAR_GP_PIN(0, 13), |
| 1928 | }; |
| 1929 | static const unsigned int msiof2_ss2_mux[] = { |
| 1930 | MSIOF2_SS2_MARK, |
| 1931 | }; |
| 1932 | static const unsigned int msiof2_txd_pins[] = { |
| 1933 | /* MSIOF2_TXD */ |
| 1934 | RCAR_GP_PIN(0, 16), |
| 1935 | }; |
| 1936 | static const unsigned int msiof2_txd_mux[] = { |
| 1937 | MSIOF2_TXD_MARK, |
| 1938 | }; |
| 1939 | static const unsigned int msiof2_rxd_pins[] = { |
| 1940 | /* MSIOF2_RXD */ |
| 1941 | RCAR_GP_PIN(0, 18), |
| 1942 | }; |
| 1943 | static const unsigned int msiof2_rxd_mux[] = { |
| 1944 | MSIOF2_RXD_MARK, |
| 1945 | }; |
| 1946 | |
| 1947 | /* - MSIOF3 ----------------------------------------------------------------- */ |
| 1948 | static const unsigned int msiof3_clk_pins[] = { |
| 1949 | /* MSIOF3_SCK */ |
| 1950 | RCAR_GP_PIN(0, 3), |
| 1951 | }; |
| 1952 | static const unsigned int msiof3_clk_mux[] = { |
| 1953 | MSIOF3_SCK_MARK, |
| 1954 | }; |
| 1955 | static const unsigned int msiof3_sync_pins[] = { |
| 1956 | /* MSIOF3_SYNC */ |
| 1957 | RCAR_GP_PIN(0, 6), |
| 1958 | }; |
| 1959 | static const unsigned int msiof3_sync_mux[] = { |
| 1960 | MSIOF3_SYNC_MARK, |
| 1961 | }; |
| 1962 | static const unsigned int msiof3_ss1_pins[] = { |
| 1963 | /* MSIOF3_SS1 */ |
| 1964 | RCAR_GP_PIN(0, 1), |
| 1965 | }; |
| 1966 | static const unsigned int msiof3_ss1_mux[] = { |
| 1967 | MSIOF3_SS1_MARK, |
| 1968 | }; |
| 1969 | static const unsigned int msiof3_ss2_pins[] = { |
| 1970 | /* MSIOF3_SS2 */ |
| 1971 | RCAR_GP_PIN(0, 2), |
| 1972 | }; |
| 1973 | static const unsigned int msiof3_ss2_mux[] = { |
| 1974 | MSIOF3_SS2_MARK, |
| 1975 | }; |
| 1976 | static const unsigned int msiof3_txd_pins[] = { |
| 1977 | /* MSIOF3_TXD */ |
| 1978 | RCAR_GP_PIN(0, 4), |
| 1979 | }; |
| 1980 | static const unsigned int msiof3_txd_mux[] = { |
| 1981 | MSIOF3_TXD_MARK, |
| 1982 | }; |
| 1983 | static const unsigned int msiof3_rxd_pins[] = { |
| 1984 | /* MSIOF3_RXD */ |
| 1985 | RCAR_GP_PIN(0, 5), |
| 1986 | }; |
| 1987 | static const unsigned int msiof3_rxd_mux[] = { |
| 1988 | MSIOF3_RXD_MARK, |
| 1989 | }; |
| 1990 | |
| 1991 | /* - MSIOF4 ----------------------------------------------------------------- */ |
| 1992 | static const unsigned int msiof4_clk_pins[] = { |
| 1993 | /* MSIOF4_SCK */ |
| 1994 | RCAR_GP_PIN(1, 25), |
| 1995 | }; |
| 1996 | static const unsigned int msiof4_clk_mux[] = { |
| 1997 | MSIOF4_SCK_MARK, |
| 1998 | }; |
| 1999 | static const unsigned int msiof4_sync_pins[] = { |
| 2000 | /* MSIOF4_SYNC */ |
| 2001 | RCAR_GP_PIN(1, 28), |
| 2002 | }; |
| 2003 | static const unsigned int msiof4_sync_mux[] = { |
| 2004 | MSIOF4_SYNC_MARK, |
| 2005 | }; |
| 2006 | static const unsigned int msiof4_ss1_pins[] = { |
| 2007 | /* MSIOF4_SS1 */ |
| 2008 | RCAR_GP_PIN(1, 23), |
| 2009 | }; |
| 2010 | static const unsigned int msiof4_ss1_mux[] = { |
| 2011 | MSIOF4_SS1_MARK, |
| 2012 | }; |
| 2013 | static const unsigned int msiof4_ss2_pins[] = { |
| 2014 | /* MSIOF4_SS2 */ |
| 2015 | RCAR_GP_PIN(1, 24), |
| 2016 | }; |
| 2017 | static const unsigned int msiof4_ss2_mux[] = { |
| 2018 | MSIOF4_SS2_MARK, |
| 2019 | }; |
| 2020 | static const unsigned int msiof4_txd_pins[] = { |
| 2021 | /* MSIOF4_TXD */ |
| 2022 | RCAR_GP_PIN(1, 26), |
| 2023 | }; |
| 2024 | static const unsigned int msiof4_txd_mux[] = { |
| 2025 | MSIOF4_TXD_MARK, |
| 2026 | }; |
| 2027 | static const unsigned int msiof4_rxd_pins[] = { |
| 2028 | /* MSIOF4_RXD */ |
| 2029 | RCAR_GP_PIN(1, 27), |
| 2030 | }; |
| 2031 | static const unsigned int msiof4_rxd_mux[] = { |
| 2032 | MSIOF4_RXD_MARK, |
| 2033 | }; |
| 2034 | |
| 2035 | /* - MSIOF5 ----------------------------------------------------------------- */ |
| 2036 | static const unsigned int msiof5_clk_pins[] = { |
| 2037 | /* MSIOF5_SCK */ |
| 2038 | RCAR_GP_PIN(0, 11), |
| 2039 | }; |
| 2040 | static const unsigned int msiof5_clk_mux[] = { |
| 2041 | MSIOF5_SCK_MARK, |
| 2042 | }; |
| 2043 | static const unsigned int msiof5_sync_pins[] = { |
| 2044 | /* MSIOF5_SYNC */ |
| 2045 | RCAR_GP_PIN(0, 9), |
| 2046 | }; |
| 2047 | static const unsigned int msiof5_sync_mux[] = { |
| 2048 | MSIOF5_SYNC_MARK, |
| 2049 | }; |
| 2050 | static const unsigned int msiof5_ss1_pins[] = { |
| 2051 | /* MSIOF5_SS1 */ |
| 2052 | RCAR_GP_PIN(0, 8), |
| 2053 | }; |
| 2054 | static const unsigned int msiof5_ss1_mux[] = { |
| 2055 | MSIOF5_SS1_MARK, |
| 2056 | }; |
| 2057 | static const unsigned int msiof5_ss2_pins[] = { |
| 2058 | /* MSIOF5_SS2 */ |
| 2059 | RCAR_GP_PIN(0, 7), |
| 2060 | }; |
| 2061 | static const unsigned int msiof5_ss2_mux[] = { |
| 2062 | MSIOF5_SS2_MARK, |
| 2063 | }; |
| 2064 | static const unsigned int msiof5_txd_pins[] = { |
| 2065 | /* MSIOF5_TXD */ |
| 2066 | RCAR_GP_PIN(0, 10), |
| 2067 | }; |
| 2068 | static const unsigned int msiof5_txd_mux[] = { |
| 2069 | MSIOF5_TXD_MARK, |
| 2070 | }; |
| 2071 | static const unsigned int msiof5_rxd_pins[] = { |
| 2072 | /* MSIOF5_RXD */ |
| 2073 | RCAR_GP_PIN(0, 12), |
| 2074 | }; |
| 2075 | static const unsigned int msiof5_rxd_mux[] = { |
| 2076 | MSIOF5_RXD_MARK, |
| 2077 | }; |
| 2078 | |
| 2079 | /* - PCIE ------------------------------------------------------------------- */ |
| 2080 | static const unsigned int pcie0_clkreq_n_pins[] = { |
| 2081 | /* PCIE0_CLKREQ_N */ |
| 2082 | RCAR_GP_PIN(4, 21), |
| 2083 | }; |
| 2084 | |
| 2085 | static const unsigned int pcie0_clkreq_n_mux[] = { |
| 2086 | PCIE0_CLKREQ_N_MARK, |
| 2087 | }; |
| 2088 | |
| 2089 | static const unsigned int pcie1_clkreq_n_pins[] = { |
| 2090 | /* PCIE1_CLKREQ_N */ |
| 2091 | RCAR_GP_PIN(4, 22), |
| 2092 | }; |
| 2093 | |
| 2094 | static const unsigned int pcie1_clkreq_n_mux[] = { |
| 2095 | PCIE1_CLKREQ_N_MARK, |
| 2096 | }; |
| 2097 | |
| 2098 | /* - PWM0_A ------------------------------------------------------------------- */ |
| 2099 | static const unsigned int pwm0_a_pins[] = { |
| 2100 | /* PWM0_A */ |
| 2101 | RCAR_GP_PIN(1, 15), |
| 2102 | }; |
| 2103 | static const unsigned int pwm0_a_mux[] = { |
| 2104 | PWM0_A_MARK, |
| 2105 | }; |
| 2106 | |
| 2107 | /* - PWM1_A ------------------------------------------------------------------- */ |
| 2108 | static const unsigned int pwm1_a_pins[] = { |
| 2109 | /* PWM1_A */ |
| 2110 | RCAR_GP_PIN(3, 13), |
| 2111 | }; |
| 2112 | static const unsigned int pwm1_a_mux[] = { |
| 2113 | PWM1_A_MARK, |
| 2114 | }; |
| 2115 | |
| 2116 | /* - PWM1_B ------------------------------------------------------------------- */ |
| 2117 | static const unsigned int pwm1_b_pins[] = { |
| 2118 | /* PWM1_B */ |
| 2119 | RCAR_GP_PIN(2, 13), |
| 2120 | }; |
| 2121 | static const unsigned int pwm1_b_mux[] = { |
| 2122 | PWM1_B_MARK, |
| 2123 | }; |
| 2124 | |
| 2125 | /* - PWM2_B ------------------------------------------------------------------- */ |
| 2126 | static const unsigned int pwm2_b_pins[] = { |
| 2127 | /* PWM2_B */ |
| 2128 | RCAR_GP_PIN(2, 14), |
| 2129 | }; |
| 2130 | static const unsigned int pwm2_b_mux[] = { |
| 2131 | PWM2_B_MARK, |
| 2132 | }; |
| 2133 | |
| 2134 | /* - PWM3_A ------------------------------------------------------------------- */ |
| 2135 | static const unsigned int pwm3_a_pins[] = { |
| 2136 | /* PWM3_A */ |
| 2137 | RCAR_GP_PIN(1, 22), |
| 2138 | }; |
| 2139 | static const unsigned int pwm3_a_mux[] = { |
| 2140 | PWM3_A_MARK, |
| 2141 | }; |
| 2142 | |
| 2143 | /* - PWM3_B ------------------------------------------------------------------- */ |
| 2144 | static const unsigned int pwm3_b_pins[] = { |
| 2145 | /* PWM3_B */ |
| 2146 | RCAR_GP_PIN(2, 15), |
| 2147 | }; |
| 2148 | static const unsigned int pwm3_b_mux[] = { |
| 2149 | PWM3_B_MARK, |
| 2150 | }; |
| 2151 | |
| 2152 | /* - PWM4 ------------------------------------------------------------------- */ |
| 2153 | static const unsigned int pwm4_pins[] = { |
| 2154 | /* PWM4 */ |
| 2155 | RCAR_GP_PIN(2, 16), |
| 2156 | }; |
| 2157 | static const unsigned int pwm4_mux[] = { |
| 2158 | PWM4_MARK, |
| 2159 | }; |
| 2160 | |
| 2161 | /* - PWM5 ------------------------------------------------------------------- */ |
| 2162 | static const unsigned int pwm5_pins[] = { |
| 2163 | /* PWM5 */ |
| 2164 | RCAR_GP_PIN(2, 17), |
| 2165 | }; |
| 2166 | static const unsigned int pwm5_mux[] = { |
| 2167 | PWM5_MARK, |
| 2168 | }; |
| 2169 | |
| 2170 | /* - PWM6 ------------------------------------------------------------------- */ |
| 2171 | static const unsigned int pwm6_pins[] = { |
| 2172 | /* PWM6 */ |
| 2173 | RCAR_GP_PIN(2, 18), |
| 2174 | }; |
| 2175 | static const unsigned int pwm6_mux[] = { |
| 2176 | PWM6_MARK, |
| 2177 | }; |
| 2178 | |
| 2179 | /* - PWM7 ------------------------------------------------------------------- */ |
| 2180 | static const unsigned int pwm7_pins[] = { |
| 2181 | /* PWM7 */ |
| 2182 | RCAR_GP_PIN(2, 19), |
| 2183 | }; |
| 2184 | static const unsigned int pwm7_mux[] = { |
| 2185 | PWM7_MARK, |
| 2186 | }; |
| 2187 | |
| 2188 | /* - PWM8_A ------------------------------------------------------------------- */ |
| 2189 | static const unsigned int pwm8_a_pins[] = { |
| 2190 | /* PWM8_A */ |
| 2191 | RCAR_GP_PIN(1, 13), |
| 2192 | }; |
| 2193 | static const unsigned int pwm8_a_mux[] = { |
| 2194 | PWM8_A_MARK, |
| 2195 | }; |
| 2196 | |
| 2197 | /* - PWM9_A ------------------------------------------------------------------- */ |
| 2198 | static const unsigned int pwm9_a_pins[] = { |
| 2199 | /* PWM9_A */ |
| 2200 | RCAR_GP_PIN(1, 14), |
| 2201 | }; |
| 2202 | static const unsigned int pwm9_a_mux[] = { |
| 2203 | PWM9_A_MARK, |
| 2204 | }; |
| 2205 | |
| 2206 | /* - QSPI0 ------------------------------------------------------------------ */ |
| 2207 | static const unsigned int qspi0_ctrl_pins[] = { |
| 2208 | /* SPCLK, SSL */ |
| 2209 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15), |
| 2210 | }; |
| 2211 | static const unsigned int qspi0_ctrl_mux[] = { |
| 2212 | QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, |
| 2213 | }; |
| 2214 | static const unsigned int qspi0_data_pins[] = { |
| 2215 | /* MOSI_IO0, MISO_IO1, IO2, IO3 */ |
| 2216 | RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18), |
| 2217 | RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16), |
| 2218 | }; |
| 2219 | static const unsigned int qspi0_data_mux[] = { |
| 2220 | QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, |
| 2221 | QSPI0_IO2_MARK, QSPI0_IO3_MARK |
| 2222 | }; |
| 2223 | |
| 2224 | /* - QSPI1 ------------------------------------------------------------------ */ |
| 2225 | static const unsigned int qspi1_ctrl_pins[] = { |
| 2226 | /* SPCLK, SSL */ |
| 2227 | RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25), |
| 2228 | }; |
| 2229 | static const unsigned int qspi1_ctrl_mux[] = { |
| 2230 | QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, |
| 2231 | }; |
| 2232 | static const unsigned int qspi1_data_pins[] = { |
| 2233 | /* MOSI_IO0, MISO_IO1, IO2, IO3 */ |
| 2234 | RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23), |
| 2235 | RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26), |
| 2236 | }; |
| 2237 | static const unsigned int qspi1_data_mux[] = { |
| 2238 | QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, |
| 2239 | QSPI1_IO2_MARK, QSPI1_IO3_MARK |
| 2240 | }; |
| 2241 | |
| 2242 | /* - SCIF0 ------------------------------------------------------------------ */ |
| 2243 | static const unsigned int scif0_data_pins[] = { |
| 2244 | /* RX0, TX0 */ |
| 2245 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12), |
| 2246 | }; |
| 2247 | static const unsigned int scif0_data_mux[] = { |
| 2248 | RX0_MARK, TX0_MARK, |
| 2249 | }; |
| 2250 | static const unsigned int scif0_clk_pins[] = { |
| 2251 | /* SCK0 */ |
| 2252 | RCAR_GP_PIN(1, 15), |
| 2253 | }; |
| 2254 | static const unsigned int scif0_clk_mux[] = { |
| 2255 | SCK0_MARK, |
| 2256 | }; |
| 2257 | static const unsigned int scif0_ctrl_pins[] = { |
| 2258 | /* RTS0_N, CTS0_N */ |
| 2259 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), |
| 2260 | }; |
| 2261 | static const unsigned int scif0_ctrl_mux[] = { |
| 2262 | RTS0_N_MARK, CTS0_N_MARK, |
| 2263 | }; |
| 2264 | |
| 2265 | /* - SCIF1 ------------------------------------------------------------------ */ |
| 2266 | static const unsigned int scif1_data_pins[] = { |
| 2267 | /* RX1, TX1 */ |
| 2268 | RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), |
| 2269 | }; |
| 2270 | static const unsigned int scif1_data_mux[] = { |
| 2271 | RX1_MARK, TX1_MARK, |
| 2272 | }; |
| 2273 | static const unsigned int scif1_clk_pins[] = { |
| 2274 | /* SCK1 */ |
| 2275 | RCAR_GP_PIN(0, 18), |
| 2276 | }; |
| 2277 | static const unsigned int scif1_clk_mux[] = { |
| 2278 | SCK1_MARK, |
| 2279 | }; |
| 2280 | static const unsigned int scif1_ctrl_pins[] = { |
| 2281 | /* RTS1_N, CTS1_N */ |
| 2282 | RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), |
| 2283 | }; |
| 2284 | static const unsigned int scif1_ctrl_mux[] = { |
| 2285 | RTS1_N_MARK, CTS1_N_MARK, |
| 2286 | }; |
| 2287 | |
| 2288 | /* - SCIF1_X ------------------------------------------------------------------ */ |
| 2289 | static const unsigned int scif1_data_x_pins[] = { |
| 2290 | /* RX1_X, TX1_X */ |
| 2291 | RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), |
| 2292 | }; |
| 2293 | static const unsigned int scif1_data_x_mux[] = { |
| 2294 | RX1_X_MARK, TX1_X_MARK, |
| 2295 | }; |
| 2296 | static const unsigned int scif1_clk_x_pins[] = { |
| 2297 | /* SCK1_X */ |
| 2298 | RCAR_GP_PIN(1, 10), |
| 2299 | }; |
| 2300 | static const unsigned int scif1_clk_x_mux[] = { |
| 2301 | SCK1_X_MARK, |
| 2302 | }; |
| 2303 | static const unsigned int scif1_ctrl_x_pins[] = { |
| 2304 | /* RTS1_N_X, CTS1_N_X */ |
| 2305 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), |
| 2306 | }; |
| 2307 | static const unsigned int scif1_ctrl_x_mux[] = { |
| 2308 | RTS1_N_X_MARK, CTS1_N_X_MARK, |
| 2309 | }; |
| 2310 | |
| 2311 | /* - SCIF3 ------------------------------------------------------------------ */ |
| 2312 | static const unsigned int scif3_data_pins[] = { |
| 2313 | /* RX3, TX3 */ |
| 2314 | RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), |
| 2315 | }; |
| 2316 | static const unsigned int scif3_data_mux[] = { |
| 2317 | RX3_MARK, TX3_MARK, |
| 2318 | }; |
| 2319 | static const unsigned int scif3_clk_pins[] = { |
| 2320 | /* SCK3 */ |
| 2321 | RCAR_GP_PIN(1, 4), |
| 2322 | }; |
| 2323 | static const unsigned int scif3_clk_mux[] = { |
| 2324 | SCK3_MARK, |
| 2325 | }; |
| 2326 | static const unsigned int scif3_ctrl_pins[] = { |
| 2327 | /* RTS3_N, CTS3_N */ |
| 2328 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), |
| 2329 | }; |
| 2330 | static const unsigned int scif3_ctrl_mux[] = { |
| 2331 | RTS3_N_MARK, CTS3_N_MARK, |
| 2332 | }; |
| 2333 | |
| 2334 | /* - SCIF3_A ------------------------------------------------------------------ */ |
| 2335 | static const unsigned int scif3_data_a_pins[] = { |
| 2336 | /* RX3_A, TX3_A */ |
| 2337 | RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28), |
| 2338 | }; |
| 2339 | static const unsigned int scif3_data_a_mux[] = { |
| 2340 | RX3_A_MARK, TX3_A_MARK, |
| 2341 | }; |
| 2342 | static const unsigned int scif3_clk_a_pins[] = { |
| 2343 | /* SCK3_A */ |
| 2344 | RCAR_GP_PIN(1, 24), |
| 2345 | }; |
| 2346 | static const unsigned int scif3_clk_a_mux[] = { |
| 2347 | SCK3_A_MARK, |
| 2348 | }; |
| 2349 | static const unsigned int scif3_ctrl_a_pins[] = { |
| 2350 | /* RTS3_N_A, CTS3_N_A */ |
| 2351 | RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), |
| 2352 | }; |
| 2353 | static const unsigned int scif3_ctrl_a_mux[] = { |
| 2354 | RTS3_N_A_MARK, CTS3_N_A_MARK, |
| 2355 | }; |
| 2356 | |
| 2357 | /* - SCIF4 ------------------------------------------------------------------ */ |
| 2358 | static const unsigned int scif4_data_pins[] = { |
| 2359 | /* RX4, TX4 */ |
| 2360 | RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12), |
| 2361 | }; |
| 2362 | static const unsigned int scif4_data_mux[] = { |
| 2363 | RX4_MARK, TX4_MARK, |
| 2364 | }; |
| 2365 | static const unsigned int scif4_clk_pins[] = { |
| 2366 | /* SCK4 */ |
| 2367 | RCAR_GP_PIN(8, 8), |
| 2368 | }; |
| 2369 | static const unsigned int scif4_clk_mux[] = { |
| 2370 | SCK4_MARK, |
| 2371 | }; |
| 2372 | static const unsigned int scif4_ctrl_pins[] = { |
| 2373 | /* RTS4_N, CTS4_N */ |
| 2374 | RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9), |
| 2375 | }; |
| 2376 | static const unsigned int scif4_ctrl_mux[] = { |
| 2377 | RTS4_N_MARK, CTS4_N_MARK, |
| 2378 | }; |
| 2379 | |
| 2380 | /* - SCIF Clock ------------------------------------------------------------- */ |
| 2381 | static const unsigned int scif_clk_pins[] = { |
| 2382 | /* SCIF_CLK */ |
| 2383 | RCAR_GP_PIN(1, 17), |
| 2384 | }; |
| 2385 | static const unsigned int scif_clk_mux[] = { |
| 2386 | SCIF_CLK_MARK, |
| 2387 | }; |
| 2388 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 2389 | /* - SSI ------------------------------------------------- */ |
| 2390 | static const unsigned int ssi_data_pins[] = { |
| 2391 | /* SSI_SD */ |
| 2392 | RCAR_GP_PIN(1, 20), |
| 2393 | }; |
| 2394 | static const unsigned int ssi_data_mux[] = { |
| 2395 | SSI_SD_MARK, |
| 2396 | }; |
| 2397 | static const unsigned int ssi_ctrl_pins[] = { |
| 2398 | /* SSI_SCK, SSI_WS */ |
| 2399 | RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), |
| 2400 | }; |
| 2401 | static const unsigned int ssi_ctrl_mux[] = { |
| 2402 | SSI_SCK_MARK, SSI_WS_MARK, |
| 2403 | }; |
| 2404 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 2405 | /* - TPU ------------------------------------------------------------------- */ |
| 2406 | static const unsigned int tpu_to0_pins[] = { |
| 2407 | /* TPU0TO0 */ |
| 2408 | RCAR_GP_PIN(2, 8), |
| 2409 | }; |
| 2410 | static const unsigned int tpu_to0_mux[] = { |
| 2411 | TPU0TO0_MARK, |
| 2412 | }; |
| 2413 | static const unsigned int tpu_to1_pins[] = { |
| 2414 | /* TPU0TO1 */ |
| 2415 | RCAR_GP_PIN(2, 7), |
| 2416 | }; |
| 2417 | static const unsigned int tpu_to1_mux[] = { |
| 2418 | TPU0TO1_MARK, |
| 2419 | }; |
| 2420 | static const unsigned int tpu_to2_pins[] = { |
| 2421 | /* TPU0TO2 */ |
| 2422 | RCAR_GP_PIN(2, 12), |
| 2423 | }; |
| 2424 | static const unsigned int tpu_to2_mux[] = { |
| 2425 | TPU0TO2_MARK, |
| 2426 | }; |
| 2427 | static const unsigned int tpu_to3_pins[] = { |
| 2428 | /* TPU0TO3 */ |
| 2429 | RCAR_GP_PIN(2, 13), |
| 2430 | }; |
| 2431 | static const unsigned int tpu_to3_mux[] = { |
| 2432 | TPU0TO3_MARK, |
| 2433 | }; |
| 2434 | |
| 2435 | /* - TPU_A ------------------------------------------------------------------- */ |
| 2436 | static const unsigned int tpu_to0_a_pins[] = { |
| 2437 | /* TPU0TO0_A */ |
| 2438 | RCAR_GP_PIN(1, 25), |
| 2439 | }; |
| 2440 | static const unsigned int tpu_to0_a_mux[] = { |
| 2441 | TPU0TO0_A_MARK, |
| 2442 | }; |
| 2443 | static const unsigned int tpu_to1_a_pins[] = { |
| 2444 | /* TPU0TO1_A */ |
| 2445 | RCAR_GP_PIN(1, 26), |
| 2446 | }; |
| 2447 | static const unsigned int tpu_to1_a_mux[] = { |
| 2448 | TPU0TO1_A_MARK, |
| 2449 | }; |
| 2450 | static const unsigned int tpu_to2_a_pins[] = { |
| 2451 | /* TPU0TO2_A */ |
| 2452 | RCAR_GP_PIN(2, 0), |
| 2453 | }; |
| 2454 | static const unsigned int tpu_to2_a_mux[] = { |
| 2455 | TPU0TO2_A_MARK, |
| 2456 | }; |
| 2457 | static const unsigned int tpu_to3_a_pins[] = { |
| 2458 | /* TPU0TO3_A */ |
| 2459 | RCAR_GP_PIN(2, 1), |
| 2460 | }; |
| 2461 | static const unsigned int tpu_to3_a_mux[] = { |
| 2462 | TPU0TO3_A_MARK, |
| 2463 | }; |
| 2464 | |
| 2465 | /* - TSN0 ------------------------------------------------ */ |
| 2466 | static const unsigned int tsn0_link_pins[] = { |
| 2467 | /* TSN0_LINK */ |
| 2468 | RCAR_GP_PIN(4, 4), |
| 2469 | }; |
| 2470 | static const unsigned int tsn0_link_mux[] = { |
| 2471 | TSN0_LINK_MARK, |
| 2472 | }; |
| 2473 | static const unsigned int tsn0_phy_int_pins[] = { |
| 2474 | /* TSN0_PHY_INT */ |
| 2475 | RCAR_GP_PIN(4, 3), |
| 2476 | }; |
| 2477 | static const unsigned int tsn0_phy_int_mux[] = { |
| 2478 | TSN0_PHY_INT_MARK, |
| 2479 | }; |
| 2480 | static const unsigned int tsn0_mdio_pins[] = { |
| 2481 | /* TSN0_MDC, TSN0_MDIO */ |
| 2482 | RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), |
| 2483 | }; |
| 2484 | static const unsigned int tsn0_mdio_mux[] = { |
| 2485 | TSN0_MDC_MARK, TSN0_MDIO_MARK, |
| 2486 | }; |
| 2487 | static const unsigned int tsn0_rgmii_pins[] = { |
| 2488 | /* |
| 2489 | * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3, |
| 2490 | * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3, |
| 2491 | */ |
| 2492 | RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12), |
| 2493 | RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), |
| 2494 | RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18), |
| 2495 | RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11), |
| 2496 | RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13), |
| 2497 | RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), |
| 2498 | }; |
| 2499 | static const unsigned int tsn0_rgmii_mux[] = { |
| 2500 | TSN0_TX_CTL_MARK, TSN0_TXC_MARK, |
| 2501 | TSN0_TD0_MARK, TSN0_TD1_MARK, |
| 2502 | TSN0_TD2_MARK, TSN0_TD3_MARK, |
| 2503 | TSN0_RX_CTL_MARK, TSN0_RXC_MARK, |
| 2504 | TSN0_RD0_MARK, TSN0_RD1_MARK, |
| 2505 | TSN0_RD2_MARK, TSN0_RD3_MARK, |
| 2506 | }; |
| 2507 | static const unsigned int tsn0_txcrefclk_pins[] = { |
| 2508 | /* TSN0_TXCREFCLK */ |
| 2509 | RCAR_GP_PIN(4, 20), |
| 2510 | }; |
| 2511 | static const unsigned int tsn0_txcrefclk_mux[] = { |
| 2512 | TSN0_TXCREFCLK_MARK, |
| 2513 | }; |
| 2514 | static const unsigned int tsn0_avtp_pps_pins[] = { |
| 2515 | /* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */ |
| 2516 | RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2), |
| 2517 | }; |
| 2518 | static const unsigned int tsn0_avtp_pps_mux[] = { |
| 2519 | TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK, |
| 2520 | }; |
| 2521 | static const unsigned int tsn0_avtp_capture_pins[] = { |
| 2522 | /* TSN0_AVTP_CAPTURE */ |
| 2523 | RCAR_GP_PIN(4, 6), |
| 2524 | }; |
| 2525 | static const unsigned int tsn0_avtp_capture_mux[] = { |
| 2526 | TSN0_AVTP_CAPTURE_MARK, |
| 2527 | }; |
| 2528 | static const unsigned int tsn0_avtp_match_pins[] = { |
| 2529 | /* TSN0_AVTP_MATCH */ |
| 2530 | RCAR_GP_PIN(4, 5), |
| 2531 | }; |
| 2532 | static const unsigned int tsn0_avtp_match_mux[] = { |
| 2533 | TSN0_AVTP_MATCH_MARK, |
| 2534 | }; |
| 2535 | |
| 2536 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 2537 | SH_PFC_PIN_GROUP(audio_clkin), |
| 2538 | SH_PFC_PIN_GROUP(audio_clkout), |
| 2539 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 2540 | SH_PFC_PIN_GROUP(avb0_link), |
| 2541 | SH_PFC_PIN_GROUP(avb0_magic), |
| 2542 | SH_PFC_PIN_GROUP(avb0_phy_int), |
| 2543 | SH_PFC_PIN_GROUP(avb0_mdio), |
| 2544 | SH_PFC_PIN_GROUP(avb0_rgmii), |
| 2545 | SH_PFC_PIN_GROUP(avb0_txcrefclk), |
| 2546 | SH_PFC_PIN_GROUP(avb0_avtp_pps), |
| 2547 | SH_PFC_PIN_GROUP(avb0_avtp_capture), |
| 2548 | SH_PFC_PIN_GROUP(avb0_avtp_match), |
| 2549 | |
| 2550 | SH_PFC_PIN_GROUP(avb1_link), |
| 2551 | SH_PFC_PIN_GROUP(avb1_magic), |
| 2552 | SH_PFC_PIN_GROUP(avb1_phy_int), |
| 2553 | SH_PFC_PIN_GROUP(avb1_mdio), |
| 2554 | SH_PFC_PIN_GROUP(avb1_rgmii), |
| 2555 | SH_PFC_PIN_GROUP(avb1_txcrefclk), |
| 2556 | SH_PFC_PIN_GROUP(avb1_avtp_pps), |
| 2557 | SH_PFC_PIN_GROUP(avb1_avtp_capture), |
| 2558 | SH_PFC_PIN_GROUP(avb1_avtp_match), |
| 2559 | |
| 2560 | SH_PFC_PIN_GROUP(avb2_link), |
| 2561 | SH_PFC_PIN_GROUP(avb2_magic), |
| 2562 | SH_PFC_PIN_GROUP(avb2_phy_int), |
| 2563 | SH_PFC_PIN_GROUP(avb2_mdio), |
| 2564 | SH_PFC_PIN_GROUP(avb2_rgmii), |
| 2565 | SH_PFC_PIN_GROUP(avb2_txcrefclk), |
| 2566 | SH_PFC_PIN_GROUP(avb2_avtp_pps), |
| 2567 | SH_PFC_PIN_GROUP(avb2_avtp_capture), |
| 2568 | SH_PFC_PIN_GROUP(avb2_avtp_match), |
| 2569 | |
| 2570 | SH_PFC_PIN_GROUP(canfd0_data), |
| 2571 | SH_PFC_PIN_GROUP(canfd1_data), |
| 2572 | SH_PFC_PIN_GROUP(canfd2_data), |
| 2573 | SH_PFC_PIN_GROUP(canfd3_data), |
| 2574 | SH_PFC_PIN_GROUP(canfd4_data), |
| 2575 | SH_PFC_PIN_GROUP(canfd5_data), /* suffix might be updated */ |
| 2576 | SH_PFC_PIN_GROUP(canfd5_data_b), /* suffix might be updated */ |
| 2577 | SH_PFC_PIN_GROUP(canfd6_data), |
| 2578 | SH_PFC_PIN_GROUP(canfd7_data), |
| 2579 | SH_PFC_PIN_GROUP(can_clk), |
| 2580 | |
| 2581 | SH_PFC_PIN_GROUP(hscif0_data), |
| 2582 | SH_PFC_PIN_GROUP(hscif0_clk), |
| 2583 | SH_PFC_PIN_GROUP(hscif0_ctrl), |
| 2584 | SH_PFC_PIN_GROUP(hscif1_data), /* suffix might be updated */ |
| 2585 | SH_PFC_PIN_GROUP(hscif1_clk), /* suffix might be updated */ |
| 2586 | SH_PFC_PIN_GROUP(hscif1_ctrl), /* suffix might be updated */ |
| 2587 | SH_PFC_PIN_GROUP(hscif1_data_x), /* suffix might be updated */ |
| 2588 | SH_PFC_PIN_GROUP(hscif1_clk_x), /* suffix might be updated */ |
| 2589 | SH_PFC_PIN_GROUP(hscif1_ctrl_x), /* suffix might be updated */ |
| 2590 | SH_PFC_PIN_GROUP(hscif2_data), |
| 2591 | SH_PFC_PIN_GROUP(hscif2_clk), |
| 2592 | SH_PFC_PIN_GROUP(hscif2_ctrl), |
| 2593 | SH_PFC_PIN_GROUP(hscif3_data), /* suffix might be updated */ |
| 2594 | SH_PFC_PIN_GROUP(hscif3_clk), /* suffix might be updated */ |
| 2595 | SH_PFC_PIN_GROUP(hscif3_ctrl), /* suffix might be updated */ |
| 2596 | SH_PFC_PIN_GROUP(hscif3_data_a), /* suffix might be updated */ |
| 2597 | SH_PFC_PIN_GROUP(hscif3_clk_a), /* suffix might be updated */ |
| 2598 | SH_PFC_PIN_GROUP(hscif3_ctrl_a), /* suffix might be updated */ |
| 2599 | |
| 2600 | SH_PFC_PIN_GROUP(i2c0), |
| 2601 | SH_PFC_PIN_GROUP(i2c1), |
| 2602 | SH_PFC_PIN_GROUP(i2c2), |
| 2603 | SH_PFC_PIN_GROUP(i2c3), |
| 2604 | SH_PFC_PIN_GROUP(i2c4), |
| 2605 | SH_PFC_PIN_GROUP(i2c5), |
| 2606 | |
| 2607 | BUS_DATA_PIN_GROUP(mmc_data, 1), |
| 2608 | BUS_DATA_PIN_GROUP(mmc_data, 4), |
| 2609 | BUS_DATA_PIN_GROUP(mmc_data, 8), |
| 2610 | SH_PFC_PIN_GROUP(mmc_ctrl), |
| 2611 | SH_PFC_PIN_GROUP(mmc_cd), |
| 2612 | SH_PFC_PIN_GROUP(mmc_wp), |
| 2613 | SH_PFC_PIN_GROUP(mmc_ds), |
| 2614 | |
| 2615 | SH_PFC_PIN_GROUP(msiof0_clk), |
| 2616 | SH_PFC_PIN_GROUP(msiof0_sync), |
| 2617 | SH_PFC_PIN_GROUP(msiof0_ss1), |
| 2618 | SH_PFC_PIN_GROUP(msiof0_ss2), |
| 2619 | SH_PFC_PIN_GROUP(msiof0_txd), |
| 2620 | SH_PFC_PIN_GROUP(msiof0_rxd), |
| 2621 | |
| 2622 | SH_PFC_PIN_GROUP(msiof1_clk), |
| 2623 | SH_PFC_PIN_GROUP(msiof1_sync), |
| 2624 | SH_PFC_PIN_GROUP(msiof1_ss1), |
| 2625 | SH_PFC_PIN_GROUP(msiof1_ss2), |
| 2626 | SH_PFC_PIN_GROUP(msiof1_txd), |
| 2627 | SH_PFC_PIN_GROUP(msiof1_rxd), |
| 2628 | |
| 2629 | SH_PFC_PIN_GROUP(msiof2_clk), |
| 2630 | SH_PFC_PIN_GROUP(msiof2_sync), |
| 2631 | SH_PFC_PIN_GROUP(msiof2_ss1), |
| 2632 | SH_PFC_PIN_GROUP(msiof2_ss2), |
| 2633 | SH_PFC_PIN_GROUP(msiof2_txd), |
| 2634 | SH_PFC_PIN_GROUP(msiof2_rxd), |
| 2635 | |
| 2636 | SH_PFC_PIN_GROUP(msiof3_clk), |
| 2637 | SH_PFC_PIN_GROUP(msiof3_sync), |
| 2638 | SH_PFC_PIN_GROUP(msiof3_ss1), |
| 2639 | SH_PFC_PIN_GROUP(msiof3_ss2), |
| 2640 | SH_PFC_PIN_GROUP(msiof3_txd), |
| 2641 | SH_PFC_PIN_GROUP(msiof3_rxd), |
| 2642 | |
| 2643 | SH_PFC_PIN_GROUP(msiof4_clk), |
| 2644 | SH_PFC_PIN_GROUP(msiof4_sync), |
| 2645 | SH_PFC_PIN_GROUP(msiof4_ss1), |
| 2646 | SH_PFC_PIN_GROUP(msiof4_ss2), |
| 2647 | SH_PFC_PIN_GROUP(msiof4_txd), |
| 2648 | SH_PFC_PIN_GROUP(msiof4_rxd), |
| 2649 | |
| 2650 | SH_PFC_PIN_GROUP(msiof5_clk), |
| 2651 | SH_PFC_PIN_GROUP(msiof5_sync), |
| 2652 | SH_PFC_PIN_GROUP(msiof5_ss1), |
| 2653 | SH_PFC_PIN_GROUP(msiof5_ss2), |
| 2654 | SH_PFC_PIN_GROUP(msiof5_txd), |
| 2655 | SH_PFC_PIN_GROUP(msiof5_rxd), |
| 2656 | |
| 2657 | SH_PFC_PIN_GROUP(pcie0_clkreq_n), |
| 2658 | SH_PFC_PIN_GROUP(pcie1_clkreq_n), |
| 2659 | |
| 2660 | SH_PFC_PIN_GROUP(pwm0_a), /* suffix might be updated */ |
| 2661 | SH_PFC_PIN_GROUP(pwm1_a), |
| 2662 | SH_PFC_PIN_GROUP(pwm1_b), |
| 2663 | SH_PFC_PIN_GROUP(pwm2_b), /* suffix might be updated */ |
| 2664 | SH_PFC_PIN_GROUP(pwm3_a), |
| 2665 | SH_PFC_PIN_GROUP(pwm3_b), |
| 2666 | SH_PFC_PIN_GROUP(pwm4), |
| 2667 | SH_PFC_PIN_GROUP(pwm5), |
| 2668 | SH_PFC_PIN_GROUP(pwm6), |
| 2669 | SH_PFC_PIN_GROUP(pwm7), |
| 2670 | SH_PFC_PIN_GROUP(pwm8_a), /* suffix might be updated */ |
| 2671 | SH_PFC_PIN_GROUP(pwm9_a), /* suffix might be updated */ |
| 2672 | |
| 2673 | SH_PFC_PIN_GROUP(qspi0_ctrl), |
| 2674 | BUS_DATA_PIN_GROUP(qspi0_data, 2), |
| 2675 | BUS_DATA_PIN_GROUP(qspi0_data, 4), |
| 2676 | SH_PFC_PIN_GROUP(qspi1_ctrl), |
| 2677 | BUS_DATA_PIN_GROUP(qspi1_data, 2), |
| 2678 | BUS_DATA_PIN_GROUP(qspi1_data, 4), |
| 2679 | |
| 2680 | SH_PFC_PIN_GROUP(scif0_data), |
| 2681 | SH_PFC_PIN_GROUP(scif0_clk), |
| 2682 | SH_PFC_PIN_GROUP(scif0_ctrl), |
| 2683 | SH_PFC_PIN_GROUP(scif1_data), /* suffix might be updated */ |
| 2684 | SH_PFC_PIN_GROUP(scif1_clk), /* suffix might be updated */ |
| 2685 | SH_PFC_PIN_GROUP(scif1_ctrl), /* suffix might be updated */ |
| 2686 | SH_PFC_PIN_GROUP(scif1_data_x), /* suffix might be updated */ |
| 2687 | SH_PFC_PIN_GROUP(scif1_clk_x), /* suffix might be updated */ |
| 2688 | SH_PFC_PIN_GROUP(scif1_ctrl_x), /* suffix might be updated */ |
| 2689 | SH_PFC_PIN_GROUP(scif3_data), /* suffix might be updated */ |
| 2690 | SH_PFC_PIN_GROUP(scif3_clk), /* suffix might be updated */ |
| 2691 | SH_PFC_PIN_GROUP(scif3_ctrl), /* suffix might be updated */ |
| 2692 | SH_PFC_PIN_GROUP(scif3_data_a), /* suffix might be updated */ |
| 2693 | SH_PFC_PIN_GROUP(scif3_clk_a), /* suffix might be updated */ |
| 2694 | SH_PFC_PIN_GROUP(scif3_ctrl_a), /* suffix might be updated */ |
| 2695 | SH_PFC_PIN_GROUP(scif4_data), |
| 2696 | SH_PFC_PIN_GROUP(scif4_clk), |
| 2697 | SH_PFC_PIN_GROUP(scif4_ctrl), |
| 2698 | SH_PFC_PIN_GROUP(scif_clk), |
| 2699 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 2700 | SH_PFC_PIN_GROUP(ssi_data), |
| 2701 | SH_PFC_PIN_GROUP(ssi_ctrl), |
| 2702 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 2703 | SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */ |
| 2704 | SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */ |
| 2705 | SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */ |
| 2706 | SH_PFC_PIN_GROUP(tpu_to1_a), /* suffix might be updated */ |
| 2707 | SH_PFC_PIN_GROUP(tpu_to2), /* suffix might be updated */ |
| 2708 | SH_PFC_PIN_GROUP(tpu_to2_a), /* suffix might be updated */ |
| 2709 | SH_PFC_PIN_GROUP(tpu_to3), /* suffix might be updated */ |
| 2710 | SH_PFC_PIN_GROUP(tpu_to3_a), /* suffix might be updated */ |
| 2711 | |
| 2712 | SH_PFC_PIN_GROUP(tsn0_link), |
| 2713 | SH_PFC_PIN_GROUP(tsn0_phy_int), |
| 2714 | SH_PFC_PIN_GROUP(tsn0_mdio), |
| 2715 | SH_PFC_PIN_GROUP(tsn0_rgmii), |
| 2716 | SH_PFC_PIN_GROUP(tsn0_txcrefclk), |
| 2717 | SH_PFC_PIN_GROUP(tsn0_avtp_pps), |
| 2718 | SH_PFC_PIN_GROUP(tsn0_avtp_capture), |
| 2719 | SH_PFC_PIN_GROUP(tsn0_avtp_match), |
| 2720 | }; |
| 2721 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 2722 | static const char * const audio_clk_groups[] = { |
| 2723 | "audio_clkin", |
| 2724 | "audio_clkout", |
| 2725 | }; |
| 2726 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 2727 | static const char * const avb0_groups[] = { |
| 2728 | "avb0_link", |
| 2729 | "avb0_magic", |
| 2730 | "avb0_phy_int", |
| 2731 | "avb0_mdio", |
| 2732 | "avb0_rgmii", |
| 2733 | "avb0_txcrefclk", |
| 2734 | "avb0_avtp_pps", |
| 2735 | "avb0_avtp_capture", |
| 2736 | "avb0_avtp_match", |
| 2737 | }; |
| 2738 | |
| 2739 | static const char * const avb1_groups[] = { |
| 2740 | "avb1_link", |
| 2741 | "avb1_magic", |
| 2742 | "avb1_phy_int", |
| 2743 | "avb1_mdio", |
| 2744 | "avb1_rgmii", |
| 2745 | "avb1_txcrefclk", |
| 2746 | "avb1_avtp_pps", |
| 2747 | "avb1_avtp_capture", |
| 2748 | "avb1_avtp_match", |
| 2749 | }; |
| 2750 | |
| 2751 | static const char * const avb2_groups[] = { |
| 2752 | "avb2_link", |
| 2753 | "avb2_magic", |
| 2754 | "avb2_phy_int", |
| 2755 | "avb2_mdio", |
| 2756 | "avb2_rgmii", |
| 2757 | "avb2_txcrefclk", |
| 2758 | "avb2_avtp_pps", |
| 2759 | "avb2_avtp_capture", |
| 2760 | "avb2_avtp_match", |
| 2761 | }; |
| 2762 | |
| 2763 | static const char * const canfd0_groups[] = { |
| 2764 | "canfd0_data", |
| 2765 | }; |
| 2766 | |
| 2767 | static const char * const canfd1_groups[] = { |
| 2768 | "canfd1_data", |
| 2769 | }; |
| 2770 | |
| 2771 | static const char * const canfd2_groups[] = { |
| 2772 | "canfd2_data", |
| 2773 | }; |
| 2774 | |
| 2775 | static const char * const canfd3_groups[] = { |
| 2776 | "canfd3_data", |
| 2777 | }; |
| 2778 | |
| 2779 | static const char * const canfd4_groups[] = { |
| 2780 | "canfd4_data", |
| 2781 | }; |
| 2782 | |
| 2783 | static const char * const canfd5_groups[] = { |
| 2784 | /* suffix might be updated */ |
| 2785 | "canfd5_data", |
| 2786 | "canfd5_data_b", |
| 2787 | }; |
| 2788 | |
| 2789 | static const char * const canfd6_groups[] = { |
| 2790 | "canfd6_data", |
| 2791 | }; |
| 2792 | |
| 2793 | static const char * const canfd7_groups[] = { |
| 2794 | "canfd7_data", |
| 2795 | }; |
| 2796 | |
| 2797 | static const char * const can_clk_groups[] = { |
| 2798 | "can_clk", |
| 2799 | }; |
| 2800 | |
| 2801 | static const char * const hscif0_groups[] = { |
| 2802 | "hscif0_data", |
| 2803 | "hscif0_clk", |
| 2804 | "hscif0_ctrl", |
| 2805 | }; |
| 2806 | |
| 2807 | static const char * const hscif1_groups[] = { |
| 2808 | /* suffix might be updated */ |
| 2809 | "hscif1_data", |
| 2810 | "hscif1_clk", |
| 2811 | "hscif1_ctrl", |
| 2812 | "hscif1_data_x", |
| 2813 | "hscif1_clk_x", |
| 2814 | "hscif1_ctrl_x", |
| 2815 | }; |
| 2816 | |
| 2817 | static const char * const hscif2_groups[] = { |
| 2818 | "hscif2_data", |
| 2819 | "hscif2_clk", |
| 2820 | "hscif2_ctrl", |
| 2821 | }; |
| 2822 | |
| 2823 | static const char * const hscif3_groups[] = { |
| 2824 | /* suffix might be updated */ |
| 2825 | "hscif3_data", |
| 2826 | "hscif3_clk", |
| 2827 | "hscif3_ctrl", |
| 2828 | "hscif3_data_a", |
| 2829 | "hscif3_clk_a", |
| 2830 | "hscif3_ctrl_a", |
| 2831 | }; |
| 2832 | |
| 2833 | static const char * const i2c0_groups[] = { |
| 2834 | "i2c0", |
| 2835 | }; |
| 2836 | |
| 2837 | static const char * const i2c1_groups[] = { |
| 2838 | "i2c1", |
| 2839 | }; |
| 2840 | |
| 2841 | static const char * const i2c2_groups[] = { |
| 2842 | "i2c2", |
| 2843 | }; |
| 2844 | |
| 2845 | static const char * const i2c3_groups[] = { |
| 2846 | "i2c3", |
| 2847 | }; |
| 2848 | |
| 2849 | static const char * const i2c4_groups[] = { |
| 2850 | "i2c4", |
| 2851 | }; |
| 2852 | |
| 2853 | static const char * const i2c5_groups[] = { |
| 2854 | "i2c5", |
| 2855 | }; |
| 2856 | |
| 2857 | static const char * const mmc_groups[] = { |
| 2858 | "mmc_data1", |
| 2859 | "mmc_data4", |
| 2860 | "mmc_data8", |
| 2861 | "mmc_ctrl", |
| 2862 | "mmc_cd", |
| 2863 | "mmc_wp", |
| 2864 | "mmc_ds", |
| 2865 | }; |
| 2866 | |
| 2867 | static const char * const msiof0_groups[] = { |
| 2868 | "msiof0_clk", |
| 2869 | "msiof0_sync", |
| 2870 | "msiof0_ss1", |
| 2871 | "msiof0_ss2", |
| 2872 | "msiof0_txd", |
| 2873 | "msiof0_rxd", |
| 2874 | }; |
| 2875 | |
| 2876 | static const char * const msiof1_groups[] = { |
| 2877 | "msiof1_clk", |
| 2878 | "msiof1_sync", |
| 2879 | "msiof1_ss1", |
| 2880 | "msiof1_ss2", |
| 2881 | "msiof1_txd", |
| 2882 | "msiof1_rxd", |
| 2883 | }; |
| 2884 | |
| 2885 | static const char * const msiof2_groups[] = { |
| 2886 | "msiof2_clk", |
| 2887 | "msiof2_sync", |
| 2888 | "msiof2_ss1", |
| 2889 | "msiof2_ss2", |
| 2890 | "msiof2_txd", |
| 2891 | "msiof2_rxd", |
| 2892 | }; |
| 2893 | |
| 2894 | static const char * const msiof3_groups[] = { |
| 2895 | "msiof3_clk", |
| 2896 | "msiof3_sync", |
| 2897 | "msiof3_ss1", |
| 2898 | "msiof3_ss2", |
| 2899 | "msiof3_txd", |
| 2900 | "msiof3_rxd", |
| 2901 | }; |
| 2902 | |
| 2903 | static const char * const msiof4_groups[] = { |
| 2904 | "msiof4_clk", |
| 2905 | "msiof4_sync", |
| 2906 | "msiof4_ss1", |
| 2907 | "msiof4_ss2", |
| 2908 | "msiof4_txd", |
| 2909 | "msiof4_rxd", |
| 2910 | }; |
| 2911 | |
| 2912 | static const char * const msiof5_groups[] = { |
| 2913 | "msiof5_clk", |
| 2914 | "msiof5_sync", |
| 2915 | "msiof5_ss1", |
| 2916 | "msiof5_ss2", |
| 2917 | "msiof5_txd", |
| 2918 | "msiof5_rxd", |
| 2919 | }; |
| 2920 | |
| 2921 | static const char * const pcie_groups[] = { |
| 2922 | "pcie0_clkreq_n", |
| 2923 | "pcie1_clkreq_n", |
| 2924 | }; |
| 2925 | |
| 2926 | static const char * const pwm0_groups[] = { |
| 2927 | /* suffix might be updated */ |
| 2928 | "pwm0_a", |
| 2929 | }; |
| 2930 | |
| 2931 | static const char * const pwm1_groups[] = { |
| 2932 | "pwm1_a", |
| 2933 | "pwm1_b", |
| 2934 | }; |
| 2935 | |
| 2936 | static const char * const pwm2_groups[] = { |
| 2937 | /* suffix might be updated */ |
| 2938 | "pwm2_b", |
| 2939 | }; |
| 2940 | |
| 2941 | static const char * const pwm3_groups[] = { |
| 2942 | "pwm3_a", |
| 2943 | "pwm3_b", |
| 2944 | }; |
| 2945 | |
| 2946 | static const char * const pwm4_groups[] = { |
| 2947 | "pwm4", |
| 2948 | }; |
| 2949 | |
| 2950 | static const char * const pwm5_groups[] = { |
| 2951 | "pwm5", |
| 2952 | }; |
| 2953 | |
| 2954 | static const char * const pwm6_groups[] = { |
| 2955 | "pwm6", |
| 2956 | }; |
| 2957 | |
| 2958 | static const char * const pwm7_groups[] = { |
| 2959 | "pwm7", |
| 2960 | }; |
| 2961 | |
| 2962 | static const char * const pwm8_groups[] = { |
| 2963 | /* suffix might be updated */ |
| 2964 | "pwm8_a", |
| 2965 | }; |
| 2966 | |
| 2967 | static const char * const pwm9_groups[] = { |
| 2968 | /* suffix might be updated */ |
| 2969 | "pwm9_a", |
| 2970 | }; |
| 2971 | |
| 2972 | static const char * const qspi0_groups[] = { |
| 2973 | "qspi0_ctrl", |
| 2974 | "qspi0_data2", |
| 2975 | "qspi0_data4", |
| 2976 | }; |
| 2977 | |
| 2978 | static const char * const qspi1_groups[] = { |
| 2979 | "qspi1_ctrl", |
| 2980 | "qspi1_data2", |
| 2981 | "qspi1_data4", |
| 2982 | }; |
| 2983 | |
| 2984 | static const char * const scif0_groups[] = { |
| 2985 | "scif0_data", |
| 2986 | "scif0_clk", |
| 2987 | "scif0_ctrl", |
| 2988 | }; |
| 2989 | |
| 2990 | static const char * const scif1_groups[] = { |
| 2991 | /* suffix might be updated */ |
| 2992 | "scif1_data", |
| 2993 | "scif1_clk", |
| 2994 | "scif1_ctrl", |
| 2995 | "scif1_data_x", |
| 2996 | "scif1_clk_x", |
| 2997 | "scif1_ctrl_x", |
| 2998 | }; |
| 2999 | |
| 3000 | static const char * const scif3_groups[] = { |
| 3001 | /* suffix might be updated */ |
| 3002 | "scif3_data", |
| 3003 | "scif3_clk", |
| 3004 | "scif3_ctrl", |
| 3005 | "scif3_data_a", |
| 3006 | "scif3_clk_a", |
| 3007 | "scif3_ctrl_a", |
| 3008 | }; |
| 3009 | |
| 3010 | static const char * const scif4_groups[] = { |
| 3011 | "scif4_data", |
| 3012 | "scif4_clk", |
| 3013 | "scif4_ctrl", |
| 3014 | }; |
| 3015 | |
| 3016 | static const char * const scif_clk_groups[] = { |
| 3017 | "scif_clk", |
| 3018 | }; |
| 3019 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3020 | static const char * const ssi_groups[] = { |
| 3021 | "ssi_data", |
| 3022 | "ssi_ctrl", |
| 3023 | }; |
| 3024 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3025 | static const char * const tpu_groups[] = { |
| 3026 | /* suffix might be updated */ |
| 3027 | "tpu_to0", |
| 3028 | "tpu_to0_a", |
| 3029 | "tpu_to1", |
| 3030 | "tpu_to1_a", |
| 3031 | "tpu_to2", |
| 3032 | "tpu_to2_a", |
| 3033 | "tpu_to3", |
| 3034 | "tpu_to3_a", |
| 3035 | }; |
| 3036 | |
| 3037 | static const char * const tsn0_groups[] = { |
| 3038 | "tsn0_link", |
| 3039 | "tsn0_phy_int", |
| 3040 | "tsn0_mdio", |
| 3041 | "tsn0_rgmii", |
| 3042 | "tsn0_txcrefclk", |
| 3043 | "tsn0_avtp_pps", |
| 3044 | "tsn0_avtp_capture", |
| 3045 | "tsn0_avtp_match", |
| 3046 | }; |
| 3047 | |
| 3048 | static const struct sh_pfc_function pinmux_functions[] = { |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3049 | SH_PFC_FUNCTION(audio_clk), |
| 3050 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3051 | SH_PFC_FUNCTION(avb0), |
| 3052 | SH_PFC_FUNCTION(avb1), |
| 3053 | SH_PFC_FUNCTION(avb2), |
| 3054 | |
| 3055 | SH_PFC_FUNCTION(canfd0), |
| 3056 | SH_PFC_FUNCTION(canfd1), |
| 3057 | SH_PFC_FUNCTION(canfd2), |
| 3058 | SH_PFC_FUNCTION(canfd3), |
| 3059 | SH_PFC_FUNCTION(canfd4), |
| 3060 | SH_PFC_FUNCTION(canfd5), |
| 3061 | SH_PFC_FUNCTION(canfd6), |
| 3062 | SH_PFC_FUNCTION(canfd7), |
| 3063 | SH_PFC_FUNCTION(can_clk), |
| 3064 | |
| 3065 | SH_PFC_FUNCTION(hscif0), |
| 3066 | SH_PFC_FUNCTION(hscif1), |
| 3067 | SH_PFC_FUNCTION(hscif2), |
| 3068 | SH_PFC_FUNCTION(hscif3), |
| 3069 | |
| 3070 | SH_PFC_FUNCTION(i2c0), |
| 3071 | SH_PFC_FUNCTION(i2c1), |
| 3072 | SH_PFC_FUNCTION(i2c2), |
| 3073 | SH_PFC_FUNCTION(i2c3), |
| 3074 | SH_PFC_FUNCTION(i2c4), |
| 3075 | SH_PFC_FUNCTION(i2c5), |
| 3076 | |
| 3077 | SH_PFC_FUNCTION(mmc), |
| 3078 | |
| 3079 | SH_PFC_FUNCTION(msiof0), |
| 3080 | SH_PFC_FUNCTION(msiof1), |
| 3081 | SH_PFC_FUNCTION(msiof2), |
| 3082 | SH_PFC_FUNCTION(msiof3), |
| 3083 | SH_PFC_FUNCTION(msiof4), |
| 3084 | SH_PFC_FUNCTION(msiof5), |
| 3085 | |
| 3086 | SH_PFC_FUNCTION(pcie), |
| 3087 | |
| 3088 | SH_PFC_FUNCTION(pwm0), |
| 3089 | SH_PFC_FUNCTION(pwm1), |
| 3090 | SH_PFC_FUNCTION(pwm2), |
| 3091 | SH_PFC_FUNCTION(pwm3), |
| 3092 | SH_PFC_FUNCTION(pwm4), |
| 3093 | SH_PFC_FUNCTION(pwm5), |
| 3094 | SH_PFC_FUNCTION(pwm6), |
| 3095 | SH_PFC_FUNCTION(pwm7), |
| 3096 | SH_PFC_FUNCTION(pwm8), |
| 3097 | SH_PFC_FUNCTION(pwm9), |
| 3098 | |
| 3099 | SH_PFC_FUNCTION(qspi0), |
| 3100 | SH_PFC_FUNCTION(qspi1), |
| 3101 | |
| 3102 | SH_PFC_FUNCTION(scif0), |
| 3103 | SH_PFC_FUNCTION(scif1), |
| 3104 | SH_PFC_FUNCTION(scif3), |
| 3105 | SH_PFC_FUNCTION(scif4), |
| 3106 | SH_PFC_FUNCTION(scif_clk), |
| 3107 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3108 | SH_PFC_FUNCTION(ssi), |
| 3109 | |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3110 | SH_PFC_FUNCTION(tpu), |
| 3111 | |
| 3112 | SH_PFC_FUNCTION(tsn0), |
| 3113 | }; |
| 3114 | |
| 3115 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
| 3116 | #define F_(x, y) FN_##y |
| 3117 | #define FM(x) FN_##x |
| 3118 | { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32, |
| 3119 | GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
| 3120 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 3121 | GROUP( |
| 3122 | /* GP0_31_19 RESERVED */ |
| 3123 | GP_0_18_FN, GPSR0_18, |
| 3124 | GP_0_17_FN, GPSR0_17, |
| 3125 | GP_0_16_FN, GPSR0_16, |
| 3126 | GP_0_15_FN, GPSR0_15, |
| 3127 | GP_0_14_FN, GPSR0_14, |
| 3128 | GP_0_13_FN, GPSR0_13, |
| 3129 | GP_0_12_FN, GPSR0_12, |
| 3130 | GP_0_11_FN, GPSR0_11, |
| 3131 | GP_0_10_FN, GPSR0_10, |
| 3132 | GP_0_9_FN, GPSR0_9, |
| 3133 | GP_0_8_FN, GPSR0_8, |
| 3134 | GP_0_7_FN, GPSR0_7, |
| 3135 | GP_0_6_FN, GPSR0_6, |
| 3136 | GP_0_5_FN, GPSR0_5, |
| 3137 | GP_0_4_FN, GPSR0_4, |
| 3138 | GP_0_3_FN, GPSR0_3, |
| 3139 | GP_0_2_FN, GPSR0_2, |
| 3140 | GP_0_1_FN, GPSR0_1, |
| 3141 | GP_0_0_FN, GPSR0_0, )) |
| 3142 | }, |
| 3143 | { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP( |
| 3144 | 0, 0, |
| 3145 | 0, 0, |
| 3146 | 0, 0, |
| 3147 | GP_1_28_FN, GPSR1_28, |
| 3148 | GP_1_27_FN, GPSR1_27, |
| 3149 | GP_1_26_FN, GPSR1_26, |
| 3150 | GP_1_25_FN, GPSR1_25, |
| 3151 | GP_1_24_FN, GPSR1_24, |
| 3152 | GP_1_23_FN, GPSR1_23, |
| 3153 | GP_1_22_FN, GPSR1_22, |
| 3154 | GP_1_21_FN, GPSR1_21, |
| 3155 | GP_1_20_FN, GPSR1_20, |
| 3156 | GP_1_19_FN, GPSR1_19, |
| 3157 | GP_1_18_FN, GPSR1_18, |
| 3158 | GP_1_17_FN, GPSR1_17, |
| 3159 | GP_1_16_FN, GPSR1_16, |
| 3160 | GP_1_15_FN, GPSR1_15, |
| 3161 | GP_1_14_FN, GPSR1_14, |
| 3162 | GP_1_13_FN, GPSR1_13, |
| 3163 | GP_1_12_FN, GPSR1_12, |
| 3164 | GP_1_11_FN, GPSR1_11, |
| 3165 | GP_1_10_FN, GPSR1_10, |
| 3166 | GP_1_9_FN, GPSR1_9, |
| 3167 | GP_1_8_FN, GPSR1_8, |
| 3168 | GP_1_7_FN, GPSR1_7, |
| 3169 | GP_1_6_FN, GPSR1_6, |
| 3170 | GP_1_5_FN, GPSR1_5, |
| 3171 | GP_1_4_FN, GPSR1_4, |
| 3172 | GP_1_3_FN, GPSR1_3, |
| 3173 | GP_1_2_FN, GPSR1_2, |
| 3174 | GP_1_1_FN, GPSR1_1, |
| 3175 | GP_1_0_FN, GPSR1_0, )) |
| 3176 | }, |
| 3177 | { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32, |
| 3178 | GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
| 3179 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 3180 | GROUP( |
| 3181 | /* GP2_31_20 RESERVED */ |
| 3182 | GP_2_19_FN, GPSR2_19, |
| 3183 | GP_2_18_FN, GPSR2_18, |
| 3184 | GP_2_17_FN, GPSR2_17, |
| 3185 | GP_2_16_FN, GPSR2_16, |
| 3186 | GP_2_15_FN, GPSR2_15, |
| 3187 | GP_2_14_FN, GPSR2_14, |
| 3188 | GP_2_13_FN, GPSR2_13, |
| 3189 | GP_2_12_FN, GPSR2_12, |
| 3190 | GP_2_11_FN, GPSR2_11, |
| 3191 | GP_2_10_FN, GPSR2_10, |
| 3192 | GP_2_9_FN, GPSR2_9, |
| 3193 | GP_2_8_FN, GPSR2_8, |
| 3194 | GP_2_7_FN, GPSR2_7, |
| 3195 | GP_2_6_FN, GPSR2_6, |
| 3196 | GP_2_5_FN, GPSR2_5, |
| 3197 | GP_2_4_FN, GPSR2_4, |
| 3198 | GP_2_3_FN, GPSR2_3, |
| 3199 | GP_2_2_FN, GPSR2_2, |
| 3200 | GP_2_1_FN, GPSR2_1, |
| 3201 | GP_2_0_FN, GPSR2_0, )) |
| 3202 | }, |
| 3203 | { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP( |
| 3204 | 0, 0, |
| 3205 | 0, 0, |
| 3206 | GP_3_29_FN, GPSR3_29, |
| 3207 | GP_3_28_FN, GPSR3_28, |
| 3208 | GP_3_27_FN, GPSR3_27, |
| 3209 | GP_3_26_FN, GPSR3_26, |
| 3210 | GP_3_25_FN, GPSR3_25, |
| 3211 | GP_3_24_FN, GPSR3_24, |
| 3212 | GP_3_23_FN, GPSR3_23, |
| 3213 | GP_3_22_FN, GPSR3_22, |
| 3214 | GP_3_21_FN, GPSR3_21, |
| 3215 | GP_3_20_FN, GPSR3_20, |
| 3216 | GP_3_19_FN, GPSR3_19, |
| 3217 | GP_3_18_FN, GPSR3_18, |
| 3218 | GP_3_17_FN, GPSR3_17, |
| 3219 | GP_3_16_FN, GPSR3_16, |
| 3220 | GP_3_15_FN, GPSR3_15, |
| 3221 | GP_3_14_FN, GPSR3_14, |
| 3222 | GP_3_13_FN, GPSR3_13, |
| 3223 | GP_3_12_FN, GPSR3_12, |
| 3224 | GP_3_11_FN, GPSR3_11, |
| 3225 | GP_3_10_FN, GPSR3_10, |
| 3226 | GP_3_9_FN, GPSR3_9, |
| 3227 | GP_3_8_FN, GPSR3_8, |
| 3228 | GP_3_7_FN, GPSR3_7, |
| 3229 | GP_3_6_FN, GPSR3_6, |
| 3230 | GP_3_5_FN, GPSR3_5, |
| 3231 | GP_3_4_FN, GPSR3_4, |
| 3232 | GP_3_3_FN, GPSR3_3, |
| 3233 | GP_3_2_FN, GPSR3_2, |
| 3234 | GP_3_1_FN, GPSR3_1, |
| 3235 | GP_3_0_FN, GPSR3_0, )) |
| 3236 | }, |
| 3237 | { PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP( |
| 3238 | 0, 0, |
| 3239 | 0, 0, |
| 3240 | 0, 0, |
| 3241 | 0, 0, |
| 3242 | 0, 0, |
| 3243 | 0, 0, |
| 3244 | 0, 0, |
| 3245 | GP_4_24_FN, GPSR4_24, |
| 3246 | GP_4_23_FN, GPSR4_23, |
| 3247 | GP_4_22_FN, GPSR4_22, |
| 3248 | GP_4_21_FN, GPSR4_21, |
| 3249 | GP_4_20_FN, GPSR4_20, |
| 3250 | GP_4_19_FN, GPSR4_19, |
| 3251 | GP_4_18_FN, GPSR4_18, |
| 3252 | GP_4_17_FN, GPSR4_17, |
| 3253 | GP_4_16_FN, GPSR4_16, |
| 3254 | GP_4_15_FN, GPSR4_15, |
| 3255 | GP_4_14_FN, GPSR4_14, |
| 3256 | GP_4_13_FN, GPSR4_13, |
| 3257 | GP_4_12_FN, GPSR4_12, |
| 3258 | GP_4_11_FN, GPSR4_11, |
| 3259 | GP_4_10_FN, GPSR4_10, |
| 3260 | GP_4_9_FN, GPSR4_9, |
| 3261 | GP_4_8_FN, GPSR4_8, |
| 3262 | GP_4_7_FN, GPSR4_7, |
| 3263 | GP_4_6_FN, GPSR4_6, |
| 3264 | GP_4_5_FN, GPSR4_5, |
| 3265 | GP_4_4_FN, GPSR4_4, |
| 3266 | GP_4_3_FN, GPSR4_3, |
| 3267 | GP_4_2_FN, GPSR4_2, |
| 3268 | GP_4_1_FN, GPSR4_1, |
| 3269 | GP_4_0_FN, GPSR4_0, )) |
| 3270 | }, |
| 3271 | { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32, |
| 3272 | GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
| 3273 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 3274 | GROUP( |
| 3275 | /* GP5_31_21 RESERVED */ |
| 3276 | GP_5_20_FN, GPSR5_20, |
| 3277 | GP_5_19_FN, GPSR5_19, |
| 3278 | GP_5_18_FN, GPSR5_18, |
| 3279 | GP_5_17_FN, GPSR5_17, |
| 3280 | GP_5_16_FN, GPSR5_16, |
| 3281 | GP_5_15_FN, GPSR5_15, |
| 3282 | GP_5_14_FN, GPSR5_14, |
| 3283 | GP_5_13_FN, GPSR5_13, |
| 3284 | GP_5_12_FN, GPSR5_12, |
| 3285 | GP_5_11_FN, GPSR5_11, |
| 3286 | GP_5_10_FN, GPSR5_10, |
| 3287 | GP_5_9_FN, GPSR5_9, |
| 3288 | GP_5_8_FN, GPSR5_8, |
| 3289 | GP_5_7_FN, GPSR5_7, |
| 3290 | GP_5_6_FN, GPSR5_6, |
| 3291 | GP_5_5_FN, GPSR5_5, |
| 3292 | GP_5_4_FN, GPSR5_4, |
| 3293 | GP_5_3_FN, GPSR5_3, |
| 3294 | GP_5_2_FN, GPSR5_2, |
| 3295 | GP_5_1_FN, GPSR5_1, |
| 3296 | GP_5_0_FN, GPSR5_0, )) |
| 3297 | }, |
| 3298 | { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32, |
| 3299 | GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
| 3300 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 3301 | GROUP( |
| 3302 | /* GP6_31_21 RESERVED */ |
| 3303 | GP_6_20_FN, GPSR6_20, |
| 3304 | GP_6_19_FN, GPSR6_19, |
| 3305 | GP_6_18_FN, GPSR6_18, |
| 3306 | GP_6_17_FN, GPSR6_17, |
| 3307 | GP_6_16_FN, GPSR6_16, |
| 3308 | GP_6_15_FN, GPSR6_15, |
| 3309 | GP_6_14_FN, GPSR6_14, |
| 3310 | GP_6_13_FN, GPSR6_13, |
| 3311 | GP_6_12_FN, GPSR6_12, |
| 3312 | GP_6_11_FN, GPSR6_11, |
| 3313 | GP_6_10_FN, GPSR6_10, |
| 3314 | GP_6_9_FN, GPSR6_9, |
| 3315 | GP_6_8_FN, GPSR6_8, |
| 3316 | GP_6_7_FN, GPSR6_7, |
| 3317 | GP_6_6_FN, GPSR6_6, |
| 3318 | GP_6_5_FN, GPSR6_5, |
| 3319 | GP_6_4_FN, GPSR6_4, |
| 3320 | GP_6_3_FN, GPSR6_3, |
| 3321 | GP_6_2_FN, GPSR6_2, |
| 3322 | GP_6_1_FN, GPSR6_1, |
| 3323 | GP_6_0_FN, GPSR6_0, )) |
| 3324 | }, |
| 3325 | { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32, |
| 3326 | GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
| 3327 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 3328 | GROUP( |
| 3329 | /* GP7_31_21 RESERVED */ |
| 3330 | GP_7_20_FN, GPSR7_20, |
| 3331 | GP_7_19_FN, GPSR7_19, |
| 3332 | GP_7_18_FN, GPSR7_18, |
| 3333 | GP_7_17_FN, GPSR7_17, |
| 3334 | GP_7_16_FN, GPSR7_16, |
| 3335 | GP_7_15_FN, GPSR7_15, |
| 3336 | GP_7_14_FN, GPSR7_14, |
| 3337 | GP_7_13_FN, GPSR7_13, |
| 3338 | GP_7_12_FN, GPSR7_12, |
| 3339 | GP_7_11_FN, GPSR7_11, |
| 3340 | GP_7_10_FN, GPSR7_10, |
| 3341 | GP_7_9_FN, GPSR7_9, |
| 3342 | GP_7_8_FN, GPSR7_8, |
| 3343 | GP_7_7_FN, GPSR7_7, |
| 3344 | GP_7_6_FN, GPSR7_6, |
| 3345 | GP_7_5_FN, GPSR7_5, |
| 3346 | GP_7_4_FN, GPSR7_4, |
| 3347 | GP_7_3_FN, GPSR7_3, |
| 3348 | GP_7_2_FN, GPSR7_2, |
| 3349 | GP_7_1_FN, GPSR7_1, |
| 3350 | GP_7_0_FN, GPSR7_0, )) |
| 3351 | }, |
| 3352 | { PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32, |
| 3353 | GROUP(-18, 1, 1, 1, 1, |
| 3354 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 3355 | GROUP( |
| 3356 | /* GP8_31_14 RESERVED */ |
| 3357 | GP_8_13_FN, GPSR8_13, |
| 3358 | GP_8_12_FN, GPSR8_12, |
| 3359 | GP_8_11_FN, GPSR8_11, |
| 3360 | GP_8_10_FN, GPSR8_10, |
| 3361 | GP_8_9_FN, GPSR8_9, |
| 3362 | GP_8_8_FN, GPSR8_8, |
| 3363 | GP_8_7_FN, GPSR8_7, |
| 3364 | GP_8_6_FN, GPSR8_6, |
| 3365 | GP_8_5_FN, GPSR8_5, |
| 3366 | GP_8_4_FN, GPSR8_4, |
| 3367 | GP_8_3_FN, GPSR8_3, |
| 3368 | GP_8_2_FN, GPSR8_2, |
| 3369 | GP_8_1_FN, GPSR8_1, |
| 3370 | GP_8_0_FN, GPSR8_0, )) |
| 3371 | }, |
| 3372 | #undef F_ |
| 3373 | #undef FM |
| 3374 | |
| 3375 | #define F_(x, y) x, |
| 3376 | #define FM(x) FN_##x, |
| 3377 | { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP( |
| 3378 | IP0SR0_31_28 |
| 3379 | IP0SR0_27_24 |
| 3380 | IP0SR0_23_20 |
| 3381 | IP0SR0_19_16 |
| 3382 | IP0SR0_15_12 |
| 3383 | IP0SR0_11_8 |
| 3384 | IP0SR0_7_4 |
| 3385 | IP0SR0_3_0)) |
| 3386 | }, |
| 3387 | { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP( |
| 3388 | IP1SR0_31_28 |
| 3389 | IP1SR0_27_24 |
| 3390 | IP1SR0_23_20 |
| 3391 | IP1SR0_19_16 |
| 3392 | IP1SR0_15_12 |
| 3393 | IP1SR0_11_8 |
| 3394 | IP1SR0_7_4 |
| 3395 | IP1SR0_3_0)) |
| 3396 | }, |
| 3397 | { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32, |
| 3398 | GROUP(-20, 4, 4, 4), |
| 3399 | GROUP( |
| 3400 | /* IP2SR0_31_12 RESERVED */ |
| 3401 | IP2SR0_11_8 |
| 3402 | IP2SR0_7_4 |
| 3403 | IP2SR0_3_0)) |
| 3404 | }, |
| 3405 | { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP( |
| 3406 | IP0SR1_31_28 |
| 3407 | IP0SR1_27_24 |
| 3408 | IP0SR1_23_20 |
| 3409 | IP0SR1_19_16 |
| 3410 | IP0SR1_15_12 |
| 3411 | IP0SR1_11_8 |
| 3412 | IP0SR1_7_4 |
| 3413 | IP0SR1_3_0)) |
| 3414 | }, |
| 3415 | { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP( |
| 3416 | IP1SR1_31_28 |
| 3417 | IP1SR1_27_24 |
| 3418 | IP1SR1_23_20 |
| 3419 | IP1SR1_19_16 |
| 3420 | IP1SR1_15_12 |
| 3421 | IP1SR1_11_8 |
| 3422 | IP1SR1_7_4 |
| 3423 | IP1SR1_3_0)) |
| 3424 | }, |
| 3425 | { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP( |
| 3426 | IP2SR1_31_28 |
| 3427 | IP2SR1_27_24 |
| 3428 | IP2SR1_23_20 |
| 3429 | IP2SR1_19_16 |
| 3430 | IP2SR1_15_12 |
| 3431 | IP2SR1_11_8 |
| 3432 | IP2SR1_7_4 |
| 3433 | IP2SR1_3_0)) |
| 3434 | }, |
| 3435 | { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32, |
| 3436 | GROUP(-12, 4, 4, 4, 4, 4), |
| 3437 | GROUP( |
| 3438 | /* IP3SR1_31_20 RESERVED */ |
| 3439 | IP3SR1_19_16 |
| 3440 | IP3SR1_15_12 |
| 3441 | IP3SR1_11_8 |
| 3442 | IP3SR1_7_4 |
| 3443 | IP3SR1_3_0)) |
| 3444 | }, |
| 3445 | { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP( |
| 3446 | IP0SR2_31_28 |
| 3447 | IP0SR2_27_24 |
| 3448 | IP0SR2_23_20 |
| 3449 | IP0SR2_19_16 |
| 3450 | IP0SR2_15_12 |
| 3451 | IP0SR2_11_8 |
| 3452 | IP0SR2_7_4 |
| 3453 | IP0SR2_3_0)) |
| 3454 | }, |
| 3455 | { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP( |
| 3456 | IP1SR2_31_28 |
| 3457 | IP1SR2_27_24 |
| 3458 | IP1SR2_23_20 |
| 3459 | IP1SR2_19_16 |
| 3460 | IP1SR2_15_12 |
| 3461 | IP1SR2_11_8 |
| 3462 | IP1SR2_7_4 |
| 3463 | IP1SR2_3_0)) |
| 3464 | }, |
| 3465 | { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32, |
| 3466 | GROUP(-16, 4, 4, 4, 4), |
| 3467 | GROUP( |
| 3468 | /* IP2SR2_31_16 RESERVED */ |
| 3469 | IP2SR2_15_12 |
| 3470 | IP2SR2_11_8 |
| 3471 | IP2SR2_7_4 |
| 3472 | IP2SR2_3_0)) |
| 3473 | }, |
| 3474 | { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP( |
| 3475 | IP0SR3_31_28 |
| 3476 | IP0SR3_27_24 |
| 3477 | IP0SR3_23_20 |
| 3478 | IP0SR3_19_16 |
| 3479 | IP0SR3_15_12 |
| 3480 | IP0SR3_11_8 |
| 3481 | IP0SR3_7_4 |
| 3482 | IP0SR3_3_0)) |
| 3483 | }, |
| 3484 | { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP( |
| 3485 | IP1SR3_31_28 |
| 3486 | IP1SR3_27_24 |
| 3487 | IP1SR3_23_20 |
| 3488 | IP1SR3_19_16 |
| 3489 | IP1SR3_15_12 |
| 3490 | IP1SR3_11_8 |
| 3491 | IP1SR3_7_4 |
| 3492 | IP1SR3_3_0)) |
| 3493 | }, |
| 3494 | { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP( |
| 3495 | IP2SR3_31_28 |
| 3496 | IP2SR3_27_24 |
| 3497 | IP2SR3_23_20 |
| 3498 | IP2SR3_19_16 |
| 3499 | IP2SR3_15_12 |
| 3500 | IP2SR3_11_8 |
| 3501 | IP2SR3_7_4 |
| 3502 | IP2SR3_3_0)) |
| 3503 | }, |
| 3504 | { PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32, |
| 3505 | GROUP(-8, 4, 4, 4, 4, 4, 4), |
| 3506 | GROUP( |
| 3507 | /* IP3SR3_31_24 RESERVED */ |
| 3508 | IP3SR3_23_20 |
| 3509 | IP3SR3_19_16 |
| 3510 | IP3SR3_15_12 |
| 3511 | IP3SR3_11_8 |
| 3512 | IP3SR3_7_4 |
| 3513 | IP3SR3_3_0)) |
| 3514 | }, |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3515 | { PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32, |
| 3516 | GROUP(4, 4, 4, 4, 4, 4, 4, 4), |
| 3517 | GROUP( |
| 3518 | IP0SR4_31_28 |
| 3519 | IP0SR4_27_24 |
| 3520 | IP0SR4_23_20 |
| 3521 | IP0SR4_19_16 |
| 3522 | IP0SR4_15_12 |
| 3523 | IP0SR4_11_8 |
| 3524 | IP0SR4_7_4 |
| 3525 | IP0SR4_3_0)) |
| 3526 | }, |
| 3527 | { PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32, |
| 3528 | GROUP(4, 4, 4, 4, 4, 4, 4, 4), |
| 3529 | GROUP( |
| 3530 | IP1SR4_31_28 |
| 3531 | IP1SR4_27_24 |
| 3532 | IP1SR4_23_20 |
| 3533 | IP1SR4_19_16 |
| 3534 | IP1SR4_15_12 |
| 3535 | IP1SR4_11_8 |
| 3536 | IP1SR4_7_4 |
| 3537 | IP1SR4_3_0)) |
| 3538 | }, |
| 3539 | { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32, |
| 3540 | GROUP(4, 4, 4, 4, 4, 4, 4, 4), |
| 3541 | GROUP( |
| 3542 | IP2SR4_31_28 |
| 3543 | IP2SR4_27_24 |
| 3544 | IP2SR4_23_20 |
| 3545 | IP2SR4_19_16 |
| 3546 | IP2SR4_15_12 |
| 3547 | IP2SR4_11_8 |
| 3548 | IP2SR4_7_4 |
| 3549 | IP2SR4_3_0)) |
| 3550 | }, |
| 3551 | { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32, |
| 3552 | GROUP(-28, 4), |
| 3553 | GROUP( |
| 3554 | /* IP3SR4_31_4 RESERVED */ |
| 3555 | IP3SR4_3_0)) |
| 3556 | }, |
| 3557 | { PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32, |
| 3558 | GROUP(4, 4, 4, 4, 4, 4, 4, 4), |
| 3559 | GROUP( |
| 3560 | IP0SR5_31_28 |
| 3561 | IP0SR5_27_24 |
| 3562 | IP0SR5_23_20 |
| 3563 | IP0SR5_19_16 |
| 3564 | IP0SR5_15_12 |
| 3565 | IP0SR5_11_8 |
| 3566 | IP0SR5_7_4 |
| 3567 | IP0SR5_3_0)) |
| 3568 | }, |
| 3569 | { PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32, |
| 3570 | GROUP(4, 4, 4, 4, 4, 4, 4, 4), |
| 3571 | GROUP( |
| 3572 | IP1SR5_31_28 |
| 3573 | IP1SR5_27_24 |
| 3574 | IP1SR5_23_20 |
| 3575 | IP1SR5_19_16 |
| 3576 | IP1SR5_15_12 |
| 3577 | IP1SR5_11_8 |
| 3578 | IP1SR5_7_4 |
| 3579 | IP1SR5_3_0)) |
| 3580 | }, |
| 3581 | { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32, |
| 3582 | GROUP(-12, 4, 4, 4, 4, 4), |
| 3583 | GROUP( |
| 3584 | /* IP2SR5_31_20 RESERVED */ |
| 3585 | IP2SR5_19_16 |
| 3586 | IP2SR5_15_12 |
| 3587 | IP2SR5_11_8 |
| 3588 | IP2SR5_7_4 |
| 3589 | IP2SR5_3_0)) |
| 3590 | }, |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3591 | { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP( |
| 3592 | IP0SR6_31_28 |
| 3593 | IP0SR6_27_24 |
| 3594 | IP0SR6_23_20 |
| 3595 | IP0SR6_19_16 |
| 3596 | IP0SR6_15_12 |
| 3597 | IP0SR6_11_8 |
| 3598 | IP0SR6_7_4 |
| 3599 | IP0SR6_3_0)) |
| 3600 | }, |
| 3601 | { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP( |
| 3602 | IP1SR6_31_28 |
| 3603 | IP1SR6_27_24 |
| 3604 | IP1SR6_23_20 |
| 3605 | IP1SR6_19_16 |
| 3606 | IP1SR6_15_12 |
| 3607 | IP1SR6_11_8 |
| 3608 | IP1SR6_7_4 |
| 3609 | IP1SR6_3_0)) |
| 3610 | }, |
| 3611 | { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32, |
| 3612 | GROUP(-12, 4, 4, 4, 4, 4), |
| 3613 | GROUP( |
| 3614 | /* IP2SR6_31_20 RESERVED */ |
| 3615 | IP2SR6_19_16 |
| 3616 | IP2SR6_15_12 |
| 3617 | IP2SR6_11_8 |
| 3618 | IP2SR6_7_4 |
| 3619 | IP2SR6_3_0)) |
| 3620 | }, |
| 3621 | { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP( |
| 3622 | IP0SR7_31_28 |
| 3623 | IP0SR7_27_24 |
| 3624 | IP0SR7_23_20 |
| 3625 | IP0SR7_19_16 |
| 3626 | IP0SR7_15_12 |
| 3627 | IP0SR7_11_8 |
| 3628 | IP0SR7_7_4 |
| 3629 | IP0SR7_3_0)) |
| 3630 | }, |
| 3631 | { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP( |
| 3632 | IP1SR7_31_28 |
| 3633 | IP1SR7_27_24 |
| 3634 | IP1SR7_23_20 |
| 3635 | IP1SR7_19_16 |
| 3636 | IP1SR7_15_12 |
| 3637 | IP1SR7_11_8 |
| 3638 | IP1SR7_7_4 |
| 3639 | IP1SR7_3_0)) |
| 3640 | }, |
| 3641 | { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32, |
| 3642 | GROUP(-12, 4, 4, 4, 4, 4), |
| 3643 | GROUP( |
| 3644 | /* IP2SR7_31_20 RESERVED */ |
| 3645 | IP2SR7_19_16 |
| 3646 | IP2SR7_15_12 |
| 3647 | IP2SR7_11_8 |
| 3648 | IP2SR7_7_4 |
| 3649 | IP2SR7_3_0)) |
| 3650 | }, |
| 3651 | { PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP( |
| 3652 | IP0SR8_31_28 |
| 3653 | IP0SR8_27_24 |
| 3654 | IP0SR8_23_20 |
| 3655 | IP0SR8_19_16 |
| 3656 | IP0SR8_15_12 |
| 3657 | IP0SR8_11_8 |
| 3658 | IP0SR8_7_4 |
| 3659 | IP0SR8_3_0)) |
| 3660 | }, |
| 3661 | { PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32, |
| 3662 | GROUP(-8, 4, 4, 4, 4, 4, 4), |
| 3663 | GROUP( |
| 3664 | /* IP1SR8_31_24 RESERVED */ |
| 3665 | IP1SR8_23_20 |
| 3666 | IP1SR8_19_16 |
| 3667 | IP1SR8_15_12 |
| 3668 | IP1SR8_11_8 |
| 3669 | IP1SR8_7_4 |
| 3670 | IP1SR8_3_0)) |
| 3671 | }, |
| 3672 | #undef F_ |
| 3673 | #undef FM |
| 3674 | |
| 3675 | #define F_(x, y) x, |
| 3676 | #define FM(x) FN_##x, |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3677 | { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32, |
| 3678 | GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 3679 | GROUP( |
| 3680 | /* RESERVED 31-12 */ |
| 3681 | MOD_SEL8_11 |
| 3682 | MOD_SEL8_10 |
| 3683 | MOD_SEL8_9 |
| 3684 | MOD_SEL8_8 |
| 3685 | MOD_SEL8_7 |
| 3686 | MOD_SEL8_6 |
| 3687 | MOD_SEL8_5 |
| 3688 | MOD_SEL8_4 |
| 3689 | MOD_SEL8_3 |
| 3690 | MOD_SEL8_2 |
| 3691 | MOD_SEL8_1 |
| 3692 | MOD_SEL8_0)) |
| 3693 | }, |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3694 | { /* sentinel */ } |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3695 | }; |
| 3696 | |
| 3697 | static const struct pinmux_drive_reg pinmux_drive_regs[] = { |
| 3698 | { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) { |
| 3699 | { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */ |
| 3700 | { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */ |
| 3701 | { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */ |
| 3702 | { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */ |
| 3703 | { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */ |
| 3704 | { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */ |
| 3705 | { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */ |
| 3706 | { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */ |
| 3707 | } }, |
| 3708 | { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) { |
| 3709 | { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */ |
| 3710 | { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */ |
| 3711 | { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */ |
| 3712 | { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */ |
| 3713 | { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */ |
| 3714 | { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */ |
| 3715 | { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */ |
| 3716 | { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */ |
| 3717 | } }, |
| 3718 | { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) { |
| 3719 | { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */ |
| 3720 | { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */ |
| 3721 | { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */ |
| 3722 | } }, |
| 3723 | { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) { |
| 3724 | { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */ |
| 3725 | { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */ |
| 3726 | { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */ |
| 3727 | { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */ |
| 3728 | { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */ |
| 3729 | { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */ |
| 3730 | { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */ |
| 3731 | { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */ |
| 3732 | } }, |
| 3733 | { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) { |
| 3734 | { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */ |
| 3735 | { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */ |
| 3736 | { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */ |
| 3737 | { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */ |
| 3738 | { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */ |
| 3739 | { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */ |
| 3740 | { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */ |
| 3741 | { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */ |
| 3742 | } }, |
| 3743 | { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) { |
| 3744 | { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */ |
| 3745 | { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */ |
| 3746 | { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */ |
| 3747 | { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */ |
| 3748 | { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */ |
| 3749 | { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */ |
| 3750 | { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */ |
| 3751 | { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */ |
| 3752 | } }, |
| 3753 | { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) { |
| 3754 | { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */ |
| 3755 | { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */ |
| 3756 | { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */ |
| 3757 | { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */ |
| 3758 | { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */ |
| 3759 | } }, |
| 3760 | { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) { |
| 3761 | { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */ |
| 3762 | { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */ |
| 3763 | { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */ |
| 3764 | { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */ |
| 3765 | { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */ |
| 3766 | { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */ |
| 3767 | { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */ |
| 3768 | { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */ |
| 3769 | } }, |
| 3770 | { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) { |
| 3771 | { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */ |
| 3772 | { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */ |
| 3773 | { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */ |
| 3774 | { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */ |
| 3775 | { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */ |
| 3776 | { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */ |
| 3777 | { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */ |
| 3778 | { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */ |
| 3779 | } }, |
| 3780 | { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) { |
| 3781 | { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */ |
| 3782 | { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */ |
| 3783 | { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */ |
| 3784 | { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */ |
| 3785 | } }, |
| 3786 | { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) { |
| 3787 | { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */ |
| 3788 | { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */ |
| 3789 | { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */ |
| 3790 | { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */ |
| 3791 | { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */ |
| 3792 | { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */ |
| 3793 | { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */ |
| 3794 | { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */ |
| 3795 | } }, |
| 3796 | { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) { |
| 3797 | { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */ |
| 3798 | { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */ |
| 3799 | { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */ |
| 3800 | { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */ |
| 3801 | { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */ |
| 3802 | { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */ |
| 3803 | { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/ |
| 3804 | { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */ |
| 3805 | } }, |
| 3806 | { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) { |
| 3807 | { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */ |
| 3808 | { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */ |
| 3809 | { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */ |
| 3810 | { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */ |
| 3811 | { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */ |
| 3812 | { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */ |
| 3813 | { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */ |
| 3814 | { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */ |
| 3815 | } }, |
| 3816 | { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) { |
| 3817 | { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */ |
| 3818 | { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */ |
| 3819 | { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */ |
| 3820 | { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */ |
| 3821 | { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */ |
| 3822 | { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */ |
| 3823 | } }, |
| 3824 | { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) { |
| 3825 | { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */ |
| 3826 | { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */ |
| 3827 | { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */ |
| 3828 | { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */ |
| 3829 | { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */ |
| 3830 | { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */ |
| 3831 | { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */ |
| 3832 | { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */ |
| 3833 | } }, |
| 3834 | { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) { |
| 3835 | { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */ |
| 3836 | { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */ |
| 3837 | { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */ |
| 3838 | { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */ |
| 3839 | { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */ |
| 3840 | { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */ |
| 3841 | { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */ |
| 3842 | { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */ |
| 3843 | } }, |
| 3844 | { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) { |
| 3845 | { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */ |
| 3846 | { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */ |
| 3847 | { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */ |
| 3848 | { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */ |
| 3849 | { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */ |
| 3850 | { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */ |
| 3851 | { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */ |
| 3852 | { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */ |
| 3853 | } }, |
| 3854 | { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) { |
| 3855 | { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */ |
| 3856 | } }, |
| 3857 | { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) { |
| 3858 | { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */ |
| 3859 | { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */ |
| 3860 | { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */ |
| 3861 | { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */ |
| 3862 | { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */ |
| 3863 | { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */ |
| 3864 | { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */ |
| 3865 | { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */ |
| 3866 | } }, |
| 3867 | { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) { |
| 3868 | { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */ |
| 3869 | { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */ |
| 3870 | { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */ |
| 3871 | { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */ |
| 3872 | { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */ |
| 3873 | { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */ |
| 3874 | { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */ |
| 3875 | { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */ |
| 3876 | } }, |
| 3877 | { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) { |
| 3878 | { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */ |
| 3879 | { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */ |
| 3880 | { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */ |
| 3881 | { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */ |
| 3882 | { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */ |
| 3883 | } }, |
| 3884 | { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) { |
| 3885 | { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */ |
| 3886 | { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */ |
| 3887 | { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */ |
| 3888 | { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */ |
| 3889 | { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */ |
| 3890 | { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */ |
| 3891 | { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */ |
| 3892 | { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */ |
| 3893 | } }, |
| 3894 | { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) { |
| 3895 | { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */ |
| 3896 | { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */ |
| 3897 | { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */ |
| 3898 | { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */ |
| 3899 | { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */ |
| 3900 | { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */ |
| 3901 | { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */ |
| 3902 | { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */ |
| 3903 | } }, |
| 3904 | { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) { |
| 3905 | { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */ |
| 3906 | { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */ |
| 3907 | { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */ |
| 3908 | { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */ |
| 3909 | { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */ |
| 3910 | } }, |
| 3911 | { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) { |
| 3912 | { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */ |
| 3913 | { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */ |
| 3914 | { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */ |
| 3915 | { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */ |
| 3916 | { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */ |
| 3917 | { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */ |
| 3918 | { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */ |
| 3919 | { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */ |
| 3920 | } }, |
| 3921 | { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) { |
| 3922 | { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */ |
| 3923 | { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */ |
| 3924 | { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */ |
| 3925 | { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */ |
| 3926 | { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */ |
| 3927 | { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */ |
| 3928 | { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */ |
| 3929 | { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */ |
| 3930 | } }, |
| 3931 | { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) { |
| 3932 | { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */ |
| 3933 | { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */ |
| 3934 | { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */ |
| 3935 | { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */ |
| 3936 | { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */ |
| 3937 | } }, |
| 3938 | { PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) { |
| 3939 | { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */ |
| 3940 | { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */ |
| 3941 | { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */ |
| 3942 | { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */ |
| 3943 | { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */ |
| 3944 | { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */ |
| 3945 | { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */ |
| 3946 | { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */ |
| 3947 | } }, |
| 3948 | { PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) { |
| 3949 | { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */ |
| 3950 | { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */ |
| 3951 | { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */ |
| 3952 | { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */ |
| 3953 | { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */ |
| 3954 | { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */ |
| 3955 | } }, |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3956 | { /* sentinel */ } |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3957 | }; |
| 3958 | |
| 3959 | enum ioctrl_regs { |
| 3960 | POC0, |
| 3961 | POC1, |
| 3962 | POC3, |
| 3963 | POC4, |
| 3964 | POC5, |
| 3965 | POC6, |
| 3966 | POC7, |
| 3967 | POC8, |
| 3968 | }; |
| 3969 | |
| 3970 | static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { |
| 3971 | [POC0] = { 0xE60500A0, }, |
| 3972 | [POC1] = { 0xE60508A0, }, |
| 3973 | [POC3] = { 0xE60588A0, }, |
| 3974 | [POC4] = { 0xE60600A0, }, |
| 3975 | [POC5] = { 0xE60608A0, }, |
| 3976 | [POC6] = { 0xE60610A0, }, |
| 3977 | [POC7] = { 0xE60618A0, }, |
| 3978 | [POC8] = { 0xE60680A0, }, |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3979 | { /* sentinel */ } |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3980 | }; |
| 3981 | |
| 3982 | static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) |
| 3983 | { |
| 3984 | int bit = pin & 0x1f; |
| 3985 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3986 | switch (pin) { |
| 3987 | case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18): |
| 3988 | *pocctrl = pinmux_ioctrl_regs[POC0].reg; |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3989 | return bit; |
| 3990 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3991 | case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22): |
| 3992 | *pocctrl = pinmux_ioctrl_regs[POC1].reg; |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3993 | return bit; |
| 3994 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3995 | case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12): |
| 3996 | *pocctrl = pinmux_ioctrl_regs[POC3].reg; |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 3997 | return bit; |
| 3998 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 3999 | case PIN_VDDQ_TSN0: |
| 4000 | *pocctrl = pinmux_ioctrl_regs[POC4].reg; |
| 4001 | return 0; |
| 4002 | |
| 4003 | case PIN_VDDQ_AVB2: |
| 4004 | *pocctrl = pinmux_ioctrl_regs[POC5].reg; |
| 4005 | return 0; |
| 4006 | |
| 4007 | case PIN_VDDQ_AVB1: |
| 4008 | *pocctrl = pinmux_ioctrl_regs[POC6].reg; |
| 4009 | return 0; |
| 4010 | |
| 4011 | case PIN_VDDQ_AVB0: |
| 4012 | *pocctrl = pinmux_ioctrl_regs[POC7].reg; |
| 4013 | return 0; |
| 4014 | |
| 4015 | case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13): |
| 4016 | *pocctrl = pinmux_ioctrl_regs[POC8].reg; |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 4017 | return bit; |
| 4018 | |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 4019 | default: |
| 4020 | return -EINVAL; |
| 4021 | } |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 4022 | } |
| 4023 | |
| 4024 | static const struct pinmux_bias_reg pinmux_bias_regs[] = { |
| 4025 | { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) { |
| 4026 | [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */ |
| 4027 | [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */ |
| 4028 | [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */ |
| 4029 | [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */ |
| 4030 | [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */ |
| 4031 | [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */ |
| 4032 | [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */ |
| 4033 | [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */ |
| 4034 | [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */ |
| 4035 | [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */ |
| 4036 | [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */ |
| 4037 | [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */ |
| 4038 | [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */ |
| 4039 | [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */ |
| 4040 | [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */ |
| 4041 | [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */ |
| 4042 | [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */ |
| 4043 | [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */ |
| 4044 | [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */ |
| 4045 | [19] = SH_PFC_PIN_NONE, |
| 4046 | [20] = SH_PFC_PIN_NONE, |
| 4047 | [21] = SH_PFC_PIN_NONE, |
| 4048 | [22] = SH_PFC_PIN_NONE, |
| 4049 | [23] = SH_PFC_PIN_NONE, |
| 4050 | [24] = SH_PFC_PIN_NONE, |
| 4051 | [25] = SH_PFC_PIN_NONE, |
| 4052 | [26] = SH_PFC_PIN_NONE, |
| 4053 | [27] = SH_PFC_PIN_NONE, |
| 4054 | [28] = SH_PFC_PIN_NONE, |
| 4055 | [29] = SH_PFC_PIN_NONE, |
| 4056 | [30] = SH_PFC_PIN_NONE, |
| 4057 | [31] = SH_PFC_PIN_NONE, |
| 4058 | } }, |
| 4059 | { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) { |
| 4060 | [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */ |
| 4061 | [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */ |
| 4062 | [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */ |
| 4063 | [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */ |
| 4064 | [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */ |
| 4065 | [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */ |
| 4066 | [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */ |
| 4067 | [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */ |
| 4068 | [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */ |
| 4069 | [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */ |
| 4070 | [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */ |
| 4071 | [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */ |
| 4072 | [12] = RCAR_GP_PIN(1, 12), /* HTX0 */ |
| 4073 | [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */ |
| 4074 | [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */ |
| 4075 | [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */ |
| 4076 | [16] = RCAR_GP_PIN(1, 16), /* HRX0 */ |
| 4077 | [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */ |
| 4078 | [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */ |
| 4079 | [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */ |
| 4080 | [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */ |
| 4081 | [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */ |
| 4082 | [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */ |
| 4083 | [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */ |
| 4084 | [24] = RCAR_GP_PIN(1, 24), /* HRX3 */ |
| 4085 | [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */ |
| 4086 | [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */ |
| 4087 | [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */ |
| 4088 | [28] = RCAR_GP_PIN(1, 28), /* HTX3 */ |
| 4089 | [29] = SH_PFC_PIN_NONE, |
| 4090 | [30] = SH_PFC_PIN_NONE, |
| 4091 | [31] = SH_PFC_PIN_NONE, |
| 4092 | } }, |
| 4093 | { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) { |
| 4094 | [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */ |
| 4095 | [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */ |
| 4096 | [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */ |
| 4097 | [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */ |
| 4098 | [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */ |
| 4099 | [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */ |
| 4100 | [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */ |
| 4101 | [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */ |
| 4102 | [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */ |
| 4103 | [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */ |
| 4104 | [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */ |
| 4105 | [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */ |
| 4106 | [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */ |
| 4107 | [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */ |
| 4108 | [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */ |
| 4109 | [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */ |
| 4110 | [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */ |
| 4111 | [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */ |
| 4112 | [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */ |
| 4113 | [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */ |
| 4114 | [20] = SH_PFC_PIN_NONE, |
| 4115 | [21] = SH_PFC_PIN_NONE, |
| 4116 | [22] = SH_PFC_PIN_NONE, |
| 4117 | [23] = SH_PFC_PIN_NONE, |
| 4118 | [24] = SH_PFC_PIN_NONE, |
| 4119 | [25] = SH_PFC_PIN_NONE, |
| 4120 | [26] = SH_PFC_PIN_NONE, |
| 4121 | [27] = SH_PFC_PIN_NONE, |
| 4122 | [28] = SH_PFC_PIN_NONE, |
| 4123 | [29] = SH_PFC_PIN_NONE, |
| 4124 | [30] = SH_PFC_PIN_NONE, |
| 4125 | [31] = SH_PFC_PIN_NONE, |
| 4126 | } }, |
| 4127 | { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) { |
| 4128 | [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */ |
| 4129 | [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */ |
| 4130 | [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */ |
| 4131 | [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */ |
| 4132 | [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */ |
| 4133 | [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */ |
| 4134 | [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */ |
| 4135 | [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */ |
| 4136 | [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */ |
| 4137 | [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */ |
| 4138 | [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */ |
| 4139 | [11] = RCAR_GP_PIN(3, 11), /* SD_CD */ |
| 4140 | [12] = RCAR_GP_PIN(3, 12), /* SD_WP */ |
| 4141 | [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */ |
| 4142 | [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */ |
| 4143 | [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */ |
| 4144 | [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */ |
| 4145 | [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */ |
| 4146 | [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */ |
| 4147 | [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */ |
| 4148 | [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */ |
| 4149 | [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */ |
| 4150 | [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */ |
| 4151 | [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */ |
| 4152 | [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */ |
| 4153 | [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */ |
| 4154 | [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */ |
| 4155 | [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */ |
| 4156 | [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */ |
| 4157 | [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */ |
| 4158 | [30] = SH_PFC_PIN_NONE, |
| 4159 | [31] = SH_PFC_PIN_NONE, |
| 4160 | } }, |
| 4161 | { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) { |
| 4162 | [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */ |
| 4163 | [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */ |
| 4164 | [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */ |
| 4165 | [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */ |
| 4166 | [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */ |
| 4167 | [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */ |
| 4168 | [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */ |
| 4169 | [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */ |
| 4170 | [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */ |
| 4171 | [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */ |
| 4172 | [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */ |
| 4173 | [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */ |
| 4174 | [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */ |
| 4175 | [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */ |
| 4176 | [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */ |
| 4177 | [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */ |
| 4178 | [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */ |
| 4179 | [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */ |
| 4180 | [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */ |
| 4181 | [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */ |
| 4182 | [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */ |
| 4183 | [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */ |
| 4184 | [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */ |
| 4185 | [23] = RCAR_GP_PIN(4, 23), /* AVS0 */ |
| 4186 | [24] = RCAR_GP_PIN(4, 24), /* AVS1 */ |
| 4187 | [25] = SH_PFC_PIN_NONE, |
| 4188 | [26] = SH_PFC_PIN_NONE, |
| 4189 | [27] = SH_PFC_PIN_NONE, |
| 4190 | [28] = SH_PFC_PIN_NONE, |
| 4191 | [29] = SH_PFC_PIN_NONE, |
| 4192 | [30] = SH_PFC_PIN_NONE, |
| 4193 | [31] = SH_PFC_PIN_NONE, |
| 4194 | } }, |
| 4195 | { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) { |
| 4196 | [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */ |
| 4197 | [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */ |
| 4198 | [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */ |
| 4199 | [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */ |
| 4200 | [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */ |
| 4201 | [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */ |
| 4202 | [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */ |
| 4203 | [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */ |
| 4204 | [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */ |
| 4205 | [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */ |
| 4206 | [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */ |
| 4207 | [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */ |
| 4208 | [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */ |
| 4209 | [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */ |
| 4210 | [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */ |
| 4211 | [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */ |
| 4212 | [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */ |
| 4213 | [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */ |
| 4214 | [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */ |
| 4215 | [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */ |
| 4216 | [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */ |
| 4217 | [21] = SH_PFC_PIN_NONE, |
| 4218 | [22] = SH_PFC_PIN_NONE, |
| 4219 | [23] = SH_PFC_PIN_NONE, |
| 4220 | [24] = SH_PFC_PIN_NONE, |
| 4221 | [25] = SH_PFC_PIN_NONE, |
| 4222 | [26] = SH_PFC_PIN_NONE, |
| 4223 | [27] = SH_PFC_PIN_NONE, |
| 4224 | [28] = SH_PFC_PIN_NONE, |
| 4225 | [29] = SH_PFC_PIN_NONE, |
| 4226 | [30] = SH_PFC_PIN_NONE, |
| 4227 | [31] = SH_PFC_PIN_NONE, |
| 4228 | } }, |
| 4229 | { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) { |
| 4230 | [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */ |
| 4231 | [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */ |
| 4232 | [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */ |
| 4233 | [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */ |
| 4234 | [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */ |
| 4235 | [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */ |
| 4236 | [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */ |
| 4237 | [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */ |
| 4238 | [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */ |
| 4239 | [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */ |
| 4240 | [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */ |
| 4241 | [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */ |
| 4242 | [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */ |
| 4243 | [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */ |
| 4244 | [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/ |
| 4245 | [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */ |
| 4246 | [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */ |
| 4247 | [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */ |
| 4248 | [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */ |
| 4249 | [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */ |
| 4250 | [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */ |
| 4251 | [21] = SH_PFC_PIN_NONE, |
| 4252 | [22] = SH_PFC_PIN_NONE, |
| 4253 | [23] = SH_PFC_PIN_NONE, |
| 4254 | [24] = SH_PFC_PIN_NONE, |
| 4255 | [25] = SH_PFC_PIN_NONE, |
| 4256 | [26] = SH_PFC_PIN_NONE, |
| 4257 | [27] = SH_PFC_PIN_NONE, |
| 4258 | [28] = SH_PFC_PIN_NONE, |
| 4259 | [29] = SH_PFC_PIN_NONE, |
| 4260 | [30] = SH_PFC_PIN_NONE, |
| 4261 | [31] = SH_PFC_PIN_NONE, |
| 4262 | } }, |
| 4263 | { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) { |
| 4264 | [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */ |
| 4265 | [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */ |
| 4266 | [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */ |
| 4267 | [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */ |
| 4268 | [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */ |
| 4269 | [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */ |
| 4270 | [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */ |
| 4271 | [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */ |
| 4272 | [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */ |
| 4273 | [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */ |
| 4274 | [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */ |
| 4275 | [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */ |
| 4276 | [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */ |
| 4277 | [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */ |
| 4278 | [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */ |
| 4279 | [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */ |
| 4280 | [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */ |
| 4281 | [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */ |
| 4282 | [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */ |
| 4283 | [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */ |
| 4284 | [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */ |
| 4285 | [21] = SH_PFC_PIN_NONE, |
| 4286 | [22] = SH_PFC_PIN_NONE, |
| 4287 | [23] = SH_PFC_PIN_NONE, |
| 4288 | [24] = SH_PFC_PIN_NONE, |
| 4289 | [25] = SH_PFC_PIN_NONE, |
| 4290 | [26] = SH_PFC_PIN_NONE, |
| 4291 | [27] = SH_PFC_PIN_NONE, |
| 4292 | [28] = SH_PFC_PIN_NONE, |
| 4293 | [29] = SH_PFC_PIN_NONE, |
| 4294 | [30] = SH_PFC_PIN_NONE, |
| 4295 | [31] = SH_PFC_PIN_NONE, |
| 4296 | } }, |
| 4297 | { PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) { |
| 4298 | [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */ |
| 4299 | [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */ |
| 4300 | [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */ |
| 4301 | [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */ |
| 4302 | [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */ |
| 4303 | [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */ |
| 4304 | [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */ |
| 4305 | [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */ |
| 4306 | [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */ |
| 4307 | [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */ |
| 4308 | [10] = RCAR_GP_PIN(8, 10), /* SCL5 */ |
| 4309 | [11] = RCAR_GP_PIN(8, 11), /* SDA5 */ |
| 4310 | [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */ |
| 4311 | [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */ |
| 4312 | [14] = SH_PFC_PIN_NONE, |
| 4313 | [15] = SH_PFC_PIN_NONE, |
| 4314 | [16] = SH_PFC_PIN_NONE, |
| 4315 | [17] = SH_PFC_PIN_NONE, |
| 4316 | [18] = SH_PFC_PIN_NONE, |
| 4317 | [19] = SH_PFC_PIN_NONE, |
| 4318 | [20] = SH_PFC_PIN_NONE, |
| 4319 | [21] = SH_PFC_PIN_NONE, |
| 4320 | [22] = SH_PFC_PIN_NONE, |
| 4321 | [23] = SH_PFC_PIN_NONE, |
| 4322 | [24] = SH_PFC_PIN_NONE, |
| 4323 | [25] = SH_PFC_PIN_NONE, |
| 4324 | [26] = SH_PFC_PIN_NONE, |
| 4325 | [27] = SH_PFC_PIN_NONE, |
| 4326 | [28] = SH_PFC_PIN_NONE, |
| 4327 | [29] = SH_PFC_PIN_NONE, |
| 4328 | [30] = SH_PFC_PIN_NONE, |
| 4329 | [31] = SH_PFC_PIN_NONE, |
| 4330 | } }, |
Marek Vasut | 8f07e8a | 2023-09-17 16:08:49 +0200 | [diff] [blame] | 4331 | { /* sentinel */ } |
Hai Pham | 9a8aaa3 | 2023-02-28 22:37:03 +0100 | [diff] [blame] | 4332 | }; |
| 4333 | |
| 4334 | static const struct sh_pfc_soc_operations r8a779g0_pin_ops = { |
| 4335 | .pin_to_pocctrl = r8a779g0_pin_to_pocctrl, |
| 4336 | .get_bias = rcar_pinmux_get_bias, |
| 4337 | .set_bias = rcar_pinmux_set_bias, |
| 4338 | }; |
| 4339 | |
| 4340 | const struct sh_pfc_soc_info r8a779g0_pinmux_info = { |
| 4341 | .name = "r8a779g0_pfc", |
| 4342 | .ops = &r8a779g0_pin_ops, |
| 4343 | .unlock_reg = 0x1ff, /* PMMRn mask */ |
| 4344 | |
| 4345 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, |
| 4346 | |
| 4347 | .pins = pinmux_pins, |
| 4348 | .nr_pins = ARRAY_SIZE(pinmux_pins), |
| 4349 | .groups = pinmux_groups, |
| 4350 | .nr_groups = ARRAY_SIZE(pinmux_groups), |
| 4351 | .functions = pinmux_functions, |
| 4352 | .nr_functions = ARRAY_SIZE(pinmux_functions), |
| 4353 | |
| 4354 | .cfg_regs = pinmux_config_regs, |
| 4355 | .drive_regs = pinmux_drive_regs, |
| 4356 | .bias_regs = pinmux_bias_regs, |
| 4357 | .ioctrl_regs = pinmux_ioctrl_regs, |
| 4358 | |
| 4359 | .pinmux_data = pinmux_data, |
| 4360 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), |
| 4361 | }; |