Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 9e4e7ed9099d31c72631088c1f615be89367f231 / . / drivers / crypto / fsl / Kconfig
blob: eaad19633f1dc9c83dd6aeae1cb6149f125692df [file] [log] [blame]
Ruchika Gupta29c1a6b2015-01-23 16:01:55 +0530[diff] [blame]1config FSL_CAAM
2 bool "Freescale Crypto Driver Support"
Tom Rini5bdd9192017-05-15 12:17:49 -0400[diff] [blame]3 select SHA_HW_ACCEL
Alexandru Gagniuc650b7862021-09-02 19:54:21 -0500[diff] [blame]4 # hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL
Gaurav Jaine31dab82022-03-24 11:50:25 +0530[diff] [blame]5 select MISC if DM
Alexandru Gagniuc650b7862021-09-02 19:54:21 -0500[diff] [blame]6 imply SPL_CRYPTO if (ARM && SPL)
Simon Glass027608e2017-05-17 03:25:25 -0600[diff] [blame]7 imply CMD_HASH
Ruchika Gupta29c1a6b2015-01-23 16:01:55 +0530[diff] [blame]8 help
9 Enables the Freescale's Cryptographic Accelerator and Assurance
10 Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
11 Job Ring as interface to communicate with CAAM.
York Sun92c36e22016-12-28 08:43:30 -0800[diff] [blame]12
Tom Rinia01b0092022-07-31 21:08:26 -0400[diff] [blame]13config SYS_FSL_MAX_NUM_OF_SEC
14 int "Number of job rings in the CAAM"
15 depends on FSL_CAAM
16 default 1
17
Ye Li3c3e9a12021-03-25 17:30:36 +0800[diff] [blame]18config CAAM_64BIT
19 bool
Gaurav Jaindb4dd6a2022-03-24 11:50:33 +0530[diff] [blame]20 default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
Ye Li3c3e9a12021-03-25 17:30:36 +0800[diff] [blame]21 help
22 Select Crypto driver for 64 bits CAAM version
23
York Sun92c36e22016-12-28 08:43:30 -0800[diff] [blame]24config SYS_FSL_HAS_SEC
25 bool
26 help
27 Enable Freescale Secure Boot and Trusted Architecture
28
29config SYS_FSL_SEC_COMPAT_2
30 bool
31 help
32 Secure boot and trust architecture compatible version 2
33
34config SYS_FSL_SEC_COMPAT_4
35 bool
36 help
37 Secure boot and trust architecture compatible version 4
38
39config SYS_FSL_SEC_COMPAT_5
40 bool
41 help
42 Secure boot and trust architecture compatible version 5
43
44config SYS_FSL_SEC_COMPAT_6
45 bool
46 help
47 Secure boot and trust architecture compatible version 6
48
York Sunfa4199422016-12-28 08:43:31 -0800[diff] [blame]49config SYS_FSL_SEC_BE
50 bool "Big-endian access to Freescale Secure Boot"
51
York Sun92c36e22016-12-28 08:43:30 -0800[diff] [blame]52config SYS_FSL_SEC_COMPAT
53 int "Freescale Secure Boot compatibility"
54 depends on SYS_FSL_HAS_SEC
55 default 2 if SYS_FSL_SEC_COMPAT_2
56 default 4 if SYS_FSL_SEC_COMPAT_4
57 default 5 if SYS_FSL_SEC_COMPAT_5
58 default 6 if SYS_FSL_SEC_COMPAT_6
York Sunfa4199422016-12-28 08:43:31 -0800[diff] [blame]59
60config SYS_FSL_SEC_LE
61 bool "Little-endian access to Freescale Secure Boot"
Michael Walleb258eb22020-06-27 22:58:53 +0200[diff] [blame]62
63if FSL_CAAM
64
65config FSL_CAAM_RNG
66 bool "Enable Random Number Generator support"
67 depends on DM_RNG
68 default y
69 help
70 Enable support for the hardware based random number generator
71 module of the CAAM. The random data is fetched from the DRGB
72 using the prediction resistance flag which means the DRGB is
73 reseeded from the TRNG every time random data is generated.
74
75endif
Kshitiz Varshney8428a492022-12-22 09:50:27 +0100[diff] [blame]76
77config FSL_DCP_RNG
78 bool "Enable Random Number Generator support"
79 depends on DM_RNG
Kshitiz Varshney8428a492022-12-22 09:50:27 +0100[diff] [blame]80 help
81 Enable support for the hardware based random number generator
82 module of the DCP. It uses the True Random Number Generator (TRNG)
83 and a Pseudo-Random Number Generator (PRNG) to achieve a true
84 randomness and cryptographic strength.