Quentin Schulz | 00a6f60 | 2023-01-09 11:36:45 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2022 Theobroma Systems Design und Consulting GmbH |
| 4 | */ |
| 5 | |
Quentin Schulz | 47d3e0b | 2023-11-03 10:28:12 +0100 | [diff] [blame] | 6 | #include <asm/gpio.h> |
Quentin Schulz | 00a6f60 | 2023-01-09 11:36:45 +0100 | [diff] [blame] | 7 | #include <asm/arch-rockchip/misc.h> |
Quentin Schulz | 47d3e0b | 2023-11-03 10:28:12 +0100 | [diff] [blame] | 8 | #include <linux/delay.h> |
Quentin Schulz | 1e1a92b | 2024-01-17 18:59:10 +0100 | [diff] [blame] | 9 | #include "../common/common.h" |
Quentin Schulz | 00a6f60 | 2023-01-09 11:36:45 +0100 | [diff] [blame] | 10 | |
| 11 | int misc_init_r(void) |
| 12 | { |
| 13 | const u32 cpuid_offset = 0x7; |
| 14 | const u32 cpuid_length = 0x10; |
| 15 | u8 cpuid[cpuid_length]; |
| 16 | int ret; |
| 17 | |
| 18 | ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); |
| 19 | if (ret) |
| 20 | return ret; |
| 21 | |
| 22 | ret = rockchip_cpuid_set(cpuid, cpuid_length); |
| 23 | if (ret) |
| 24 | return ret; |
| 25 | |
| 26 | ret = rockchip_setup_macaddr(); |
| 27 | if (ret) |
| 28 | return ret; |
| 29 | |
| 30 | setup_boottargets(); |
| 31 | |
| 32 | return 0; |
| 33 | } |
Quentin Schulz | 47d3e0b | 2023-11-03 10:28:12 +0100 | [diff] [blame] | 34 | |
| 35 | #define STM32_RST 100 /* GPIO3_A4 */ |
| 36 | #define STM32_BOOT 101 /* GPIO3_A5 */ |
| 37 | |
| 38 | void spl_board_init(void) |
| 39 | { |
| 40 | /* |
| 41 | * Glitches on STM32_BOOT and STM32_RST lines during poweroff or power |
| 42 | * on may put the STM32 companion microcontroller into DFU mode, let's |
| 43 | * always reset it into normal mode instead. |
| 44 | * Toggling the STM32_RST line is safe to do with the ATtiny companion |
| 45 | * microcontroller variant because it will not trigger an MCU reset |
| 46 | * since only a UPDI reset command will. Since a UPDI reset is difficult |
| 47 | * to mistakenly trigger, glitches to the lines are theoretically also |
| 48 | * incapable of triggering an actual ATtiny reset. |
| 49 | */ |
| 50 | int ret; |
| 51 | |
| 52 | ret = gpio_request(STM32_RST, "STM32_RST"); |
| 53 | if (ret) { |
| 54 | debug("Failed to request STM32_RST\n"); |
| 55 | return; |
| 56 | } |
| 57 | |
| 58 | ret = gpio_request(STM32_BOOT, "STM32_BOOT"); |
| 59 | if (ret) { |
| 60 | debug("Failed to request STM32_BOOT\n"); |
| 61 | return; |
| 62 | } |
| 63 | |
| 64 | /* Rely on HW pull-down for inactive level */ |
| 65 | ret = gpio_direction_input(STM32_BOOT); |
| 66 | if (ret) { |
| 67 | debug("Failed to configure STM32_BOOT as input\n"); |
| 68 | return; |
| 69 | } |
| 70 | |
| 71 | ret = gpio_direction_output(STM32_RST, 0); |
| 72 | if (ret) { |
| 73 | debug("Failed to configure STM32_RST as output low\n"); |
| 74 | return; |
| 75 | } |
| 76 | |
| 77 | mdelay(1); |
| 78 | |
| 79 | ret = gpio_direction_output(STM32_RST, 1); |
| 80 | if (ret) { |
| 81 | debug("Failed to configure STM32_RST as output high\n"); |
| 82 | return; |
| 83 | } |
| 84 | } |