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git01.mediatek.com / filogic / uboot / 9e4af83497067b8a055753375f9e69f661fdf495 / . / arch / x86 / cpu / u-boot.lds
blob: b0d8531a605743cca554a00bfe6ccc762476e8a4 [file] [log] [blame]
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]1/*
2 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]6 */
7
Graeme Russc5881f12011-04-13 19:43:25 +1000[diff] [blame]8#include <config.h>
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]9OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
10OUTPUT_ARCH(i386)
11ENTRY(_start)
12
13SECTIONS
14{
Wolfgang Denkfb2759c2010-10-18 23:43:37 +0200[diff] [blame]15 . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
Graeme Russae428db2010-10-07 20:03:31 +1100[diff] [blame]16 __text_start = .;
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]17 .text : { *(.text*); }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]18
19 . = ALIGN(4);
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]20
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]21 . = ALIGN(4);
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]22 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +0000[diff] [blame]23 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]24 }
25
26 . = ALIGN(4);
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]27 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]28
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]29 . = ALIGN(4);
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]30 .data : { *(.data*) }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]31
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]32 . = ALIGN(4);
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]33 .hash : { *(.hash*) }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]34
35 . = ALIGN(4);
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]36 .got : { *(.got*) }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]37
38 . = ALIGN(4);
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]39 __data_end = .;
Simon Glass3e93e332013-03-05 14:39:54 +0000[diff] [blame]40 __init_end = .;
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]41
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]42 . = ALIGN(4);
Simon Glass18cc2bc2013-02-28 19:26:14 +0000[diff] [blame]43 .dynsym : { *(.dynsym*) }
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]44
Graeme Russ078395c2009-11-24 20:04:21 +1100[diff] [blame]45 . = ALIGN(4);
Graeme Russae428db2010-10-07 20:03:31 +1100[diff] [blame]46 __rel_dyn_start = .;
Simon Glass1eb8ebc2014-11-14 18:18:24 -0700[diff] [blame]47 .rel.dyn : {
48 *(.rel*)
49 }
Graeme Russae428db2010-10-07 20:03:31 +1100[diff] [blame]50 __rel_dyn_end = .;
Simon Glass781db8c2013-02-28 19:26:13 +0000[diff] [blame]51 . = ALIGN(4);
52 _end = .;
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]53
Simon Glass18cc2bc2013-02-28 19:26:14 +0000[diff] [blame]54 .bss __rel_dyn_start (OVERLAY) : {
55 __bss_start = .;
56 *(.bss)
57 *(COM*)
58 . = ALIGN(4);
59 __bss_end = .;
60 }
61
Graeme Russfb4e2be2010-10-07 20:03:32 +1100[diff] [blame]62 /DISCARD/ : { *(.dynstr*) }
63 /DISCARD/ : { *(.dynamic*) }
64 /DISCARD/ : { *(.plt*) }
65 /DISCARD/ : { *(.interp*) }
66 /DISCARD/ : { *(.gnu*) }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]67
Simon Glassbfb59802013-02-14 04:18:54 +0000[diff] [blame]68#ifdef CONFIG_X86_RESET_VECTOR
Graeme Russ3fe48602011-02-12 15:11:24 +1100[diff] [blame]69 /*
70 * The following expressions place the 16-bit Real-Mode code and
71 * Reset Vector at the end of the Flash ROM
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]72 */
Simon Glass20ec2532014-11-14 18:18:25 -0700[diff] [blame]73 . = START_16 - RESET_SEG_START;
74 .start16 : AT (START_16) {
75 KEEP(*(.start16));
76 }
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]77
Simon Glass20ec2532014-11-14 18:18:25 -0700[diff] [blame]78 . = RESET_VEC_LOC - RESET_SEG_START;
79 .resetvec : AT (RESET_VEC_LOC) {
80 KEEP(*(.resetvec));
81 }
Gabe Black14f82462012-11-27 21:08:06 +0000[diff] [blame]82#endif
Simon Glass20ec2532014-11-14 18:18:25 -0700[diff] [blame]83
Graeme Russe56d3972008-12-07 10:28:57 +1100[diff] [blame]84}