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wdenk7a428cc2003-06-15 22:40:42 +00001/*
wdenk57b2d802003-06-27 21:31:46 +00002 * linux/drivers/mmc/mmc_pxa.h
wdenk7a428cc2003-06-15 22:40:42 +00003 *
wdenk57b2d802003-06-27 21:31:46 +00004 * Author: Vladimir Shebordaev, Igor Oblakov
wdenk7a428cc2003-06-15 22:40:42 +00005 * Copyright: MontaVista Software Inc.
6 *
7 * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __MMC_PXA_P_H__
14#define __MMC_PXA_P_H__
15
16/* PXA-250 MMC controller registers */
17
18/* MMC_STRPCL */
Wolfgang Denka1be4762008-05-20 16:00:29 +020019#define MMC_STRPCL_STOP_CLK (0x0001UL)
wdenk7a428cc2003-06-15 22:40:42 +000020#define MMC_STRPCL_START_CLK (0x0002UL)
21
22/* MMC_STAT */
23#define MMC_STAT_END_CMD_RES (0x0001UL << 13)
Wolfgang Denka1be4762008-05-20 16:00:29 +020024#define MMC_STAT_PRG_DONE (0x0001UL << 12)
25#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11)
26#define MMC_STAT_CLK_EN (0x0001UL << 8)
27#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7)
28#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6)
29#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5)
wdenk7a428cc2003-06-15 22:40:42 +000030#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4)
Wolfgang Denka1be4762008-05-20 16:00:29 +020031#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3)
32#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2)
33#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1)
34#define MMC_STAT_READ_TIME_OUT (0x0001UL)
wdenk7a428cc2003-06-15 22:40:42 +000035
36#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
37 |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
38 |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
39
40/* MMC_CLKRT */
Wolfgang Denka1be4762008-05-20 16:00:29 +020041#define MMC_CLKRT_20MHZ (0x0000UL)
42#define MMC_CLKRT_10MHZ (0x0001UL)
43#define MMC_CLKRT_5MHZ (0x0002UL)
wdenk7a428cc2003-06-15 22:40:42 +000044#define MMC_CLKRT_2_5MHZ (0x0003UL)
Wolfgang Denka1be4762008-05-20 16:00:29 +020045#define MMC_CLKRT_1_25MHZ (0x0004UL)
46#define MMC_CLKRT_0_625MHZ (0x0005UL)
47#define MMC_CLKRT_0_3125MHZ (0x0006UL)
wdenk7a428cc2003-06-15 22:40:42 +000048
49/* MMC_SPI */
Wolfgang Denka1be4762008-05-20 16:00:29 +020050#define MMC_SPI_DISABLE (0x00UL)
51#define MMC_SPI_EN (0x01UL)
52#define MMC_SPI_CS_EN (0x01UL << 2)
53#define MMC_SPI_CS_ADDRESS (0x01UL << 3)
54#define MMC_SPI_CRC_ON (0x01UL << 1)
wdenk7a428cc2003-06-15 22:40:42 +000055
56/* MMC_CMDAT */
stefano babic43300a12007-11-20 10:40:24 +010057#define MMC_CMDAT_SD_4DAT (0x0001UL << 8)
wdenk7a428cc2003-06-15 22:40:42 +000058#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7)
Wolfgang Denka1be4762008-05-20 16:00:29 +020059#define MMC_CMDAT_INIT (0x0001UL << 6)
60#define MMC_CMDAT_BUSY (0x0001UL << 5)
61#define MMC_CMDAT_BCR (0x0003UL << 5)
wdenk7a428cc2003-06-15 22:40:42 +000062#define MMC_CMDAT_STREAM (0x0001UL << 4)
Wolfgang Denka1be4762008-05-20 16:00:29 +020063#define MMC_CMDAT_BLOCK (0x0000UL << 4)
64#define MMC_CMDAT_WRITE (0x0001UL << 3)
65#define MMC_CMDAT_READ (0x0000UL << 3)
66#define MMC_CMDAT_DATA_EN (0x0001UL << 2)
67#define MMC_CMDAT_R0 (0)
68#define MMC_CMDAT_R1 (0x0001UL)
69#define MMC_CMDAT_R2 (0x0002UL)
70#define MMC_CMDAT_R3 (0x0003UL)
wdenk7a428cc2003-06-15 22:40:42 +000071
72/* MMC_RESTO */
Wolfgang Denka1be4762008-05-20 16:00:29 +020073#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */
wdenk7a428cc2003-06-15 22:40:42 +000074
75/* MMC_RDTO */
Wolfgang Denka1be4762008-05-20 16:00:29 +020076#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */
wdenk7a428cc2003-06-15 22:40:42 +000077
78/* MMC_BLKLEN */
Wolfgang Denka1be4762008-05-20 16:00:29 +020079#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */
wdenk7a428cc2003-06-15 22:40:42 +000080
81/* MMC_PRTBUF */
Wolfgang Denka1be4762008-05-20 16:00:29 +020082#define MMC_PRTBUF_BUF_PART_FULL (0x01UL)
wdenk7a428cc2003-06-15 22:40:42 +000083#define MMC_PRTBUF_BUF_FULL (0x00UL )
84
85/* MMC_I_MASK */
86#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6)
87#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5)
Wolfgang Denka1be4762008-05-20 16:00:29 +020088#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4)
89#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
90#define MMC_I_MASK_END_CMD_RES (0x01UL << 2)
91#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
wdenk7a428cc2003-06-15 22:40:42 +000092#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL)
Wolfgang Denka1be4762008-05-20 16:00:29 +020093#define MMC_I_MASK_ALL (0x07fUL)
wdenk7a428cc2003-06-15 22:40:42 +000094
95
96/* MMC_I_REG */
Wolfgang Denka1be4762008-05-20 16:00:29 +020097#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6)
98#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5)
wdenk7a428cc2003-06-15 22:40:42 +000099#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4)
Wolfgang Denka1be4762008-05-20 16:00:29 +0200100#define MMC_I_REG_STOP_CMD (0x01UL << 3)
101#define MMC_I_REG_END_CMD_RES (0x01UL << 2)
102#define MMC_I_REG_PRG_DONE (0x01UL << 1)
103#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
104#define MMC_I_REG_ALL (0x007fUL)
wdenk7a428cc2003-06-15 22:40:42 +0000105
106/* MMC_CMD */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200107#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */
wdenk7a428cc2003-06-15 22:40:42 +0000108#define CMD(x) (x)
109
110#define MMC_DEFAULT_RCA 1
111
112#define MMC_BLOCK_SIZE 512
wdenk7a428cc2003-06-15 22:40:42 +0000113#define MMC_MAX_BLOCK_SIZE 512
114
115#define MMC_R1_IDLE_STATE 0x01
116#define MMC_R1_ERASE_STATE 0x02
117#define MMC_R1_ILLEGAL_CMD 0x04
118#define MMC_R1_COM_CRC_ERR 0x08
119#define MMC_R1_ERASE_SEQ_ERR 0x01
120#define MMC_R1_ADDR_ERR 0x02
121#define MMC_R1_PARAM_ERR 0x04
122
123#define MMC_R1B_WP_ERASE_SKIP 0x0002
124#define MMC_R1B_ERR 0x0004
125#define MMC_R1B_CC_ERR 0x0008
126#define MMC_R1B_CARD_ECC_ERR 0x0010
127#define MMC_R1B_WP_VIOLATION 0x0020
128#define MMC_R1B_ERASE_PARAM 0x0040
129#define MMC_R1B_OOR 0x0080
130#define MMC_R1B_IDLE_STATE 0x0100
131#define MMC_R1B_ERASE_RESET 0x0200
132#define MMC_R1B_ILLEGAL_CMD 0x0400
133#define MMC_R1B_COM_CRC_ERR 0x0800
134#define MMC_R1B_ERASE_SEQ_ERR 0x1000
135#define MMC_R1B_ADDR_ERR 0x2000
136#define MMC_R1B_PARAM_ERR 0x4000
137
138typedef struct mmc_cid
139{
140/* FIXME: BYTE_ORDER */
141 uchar year:4,
142 month:4;
143 uchar sn[3];
144 uchar fwrev:4,
145 hwrev:4;
146 uchar name[6];
147 uchar id[3];
148} mmc_cid_t;
149
150typedef struct mmc_csd
151{
stefano babic43300a12007-11-20 10:40:24 +0100152 uint8_t csd_structure:2,
153 spec_ver:4,
154 rsvd1:2;
155 uint8_t taac;
156 uint8_t nsac;
157 uint8_t tran_speed;
158 uint16_t ccc:12,
159 read_bl_len:4;
160 uint64_t read_bl_partial:1,
161 write_blk_misalign:1,
162 read_blk_misalign:1,
163 dsr_imp:1,
164 rsvd2:2,
165 c_size:12,
166 vdd_r_curr_min:3,
167 vdd_r_curr_max:3,
168 vdd_w_curr_min:3,
169 vdd_w_curr_max:3,
170 c_size_mult:3,
171 erase_blk_en:1,
172 sector_size:7,
173 wp_grp_size:7,
174 wp_grp_enable:1,
175 default_ecc:2,
176 r2w_factor:3,
177 write_bl_len:4,
178 write_bl_partial:1,
179 rsvd3:4,
180 content_prot_app:1;
181 uint8_t file_format_grp:1,
182 copy:1,
183 perm_write_protect:1,
184 tmp_write_protect:1,
185 file_format:2,
186 ecc:2;
wdenk7a428cc2003-06-15 22:40:42 +0000187} mmc_csd_t;
188
wdenk7a428cc2003-06-15 22:40:42 +0000189#endif /* __MMC_PXA_P_H__ */