stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 1 | /* |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 2 | * (C) Copyright 2000-2005 |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 15 | /* |
| 16 | * High Level Configuration Options |
| 17 | * (easy to change) |
| 18 | */ |
| 19 | |
| 20 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 21 | #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 22 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
| 24 | |
Stefan Roese | d4c0b70 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 25 | /* |
| 26 | * Include common defines/options for all AMCC eval boards |
| 27 | */ |
| 28 | #define CONFIG_HOSTNAME bubinga |
| 29 | #include "amcc-common.h" |
| 30 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 31 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
| 32 | |
| 33 | #define CONFIG_NO_SERIAL_EEPROM |
| 34 | /*#undef CONFIG_NO_SERIAL_EEPROM*/ |
| 35 | /*----------------------------------------------------------------------------*/ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 36 | #ifdef CONFIG_NO_SERIAL_EEPROM |
| 37 | |
| 38 | /* |
| 39 | !------------------------------------------------------------------------------- |
| 40 | ! Defines for entry options. |
| 41 | ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that |
| 42 | ! are plugged in the board will be utilized as non-ECC DIMMs. |
| 43 | !------------------------------------------------------------------------------- |
| 44 | */ |
| 45 | #define AUTO_MEMORY_CONFIG |
| 46 | #define DIMM_READ_ADDR 0xAB |
| 47 | #define DIMM_WRITE_ADDR 0xAA |
| 48 | |
| 49 | /* |
| 50 | !------------------------------------------------------------------------------- |
| 51 | ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, |
| 52 | ! assuming a 33MHz input clock to the 405EP from the C9531. |
| 53 | !------------------------------------------------------------------------------- |
| 54 | */ |
| 55 | #define PLLMR0_DEFAULT PLLMR0_266_133_66 |
| 56 | #define PLLMR1_DEFAULT PLLMR1_266_133_66 |
| 57 | |
| 58 | #endif |
| 59 | /*----------------------------------------------------------------------------*/ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 60 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 61 | /* |
| 62 | * Define here the location of the environment variables (FLASH or NVRAM). |
| 63 | * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only |
| 64 | * supported for backward compatibility. |
| 65 | */ |
| 66 | #if 1 |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 67 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 68 | #else |
Jean-Christophe PLAGNIOL-VILLARD | fdb79c3 | 2008-09-10 22:47:59 +0200 | [diff] [blame] | 69 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 70 | #endif |
| 71 | |
Stefan Roese | d4c0b70 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 72 | /* |
| 73 | * Default environment variables |
| 74 | */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 75 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Stefan Roese | d4c0b70 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 76 | CONFIG_AMCC_DEF_ENV \ |
| 77 | CONFIG_AMCC_DEF_ENV_PPC \ |
| 78 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 79 | "kernel_addr=fff80000\0" \ |
| 80 | "ramdisk_addr=fff90000\0" \ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 81 | "" |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 82 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 83 | #define CONFIG_PHY_ADDR 1 /* PHY address */ |
Stefan Roese | a98dfe6 | 2008-05-08 11:05:15 +0200 | [diff] [blame] | 84 | #define CONFIG_HAS_ETH0 |
Stefan Roese | 00f0d96 | 2005-08-11 17:58:40 +0200 | [diff] [blame] | 85 | #define CONFIG_HAS_ETH1 |
| 86 | #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ |
Stefan Roese | 7f98aec | 2005-10-20 16:34:28 +0200 | [diff] [blame] | 87 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 88 | #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ |
| 89 | |
Jon Loeliger | e54e77a | 2007-07-10 09:29:01 -0500 | [diff] [blame] | 90 | /* |
Stefan Roese | d4c0b70 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 91 | * Commands additional to the ones defined in amcc-common.h |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 92 | */ |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 93 | #define CONFIG_CMD_DATE |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 94 | #define CONFIG_CMD_PCI |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 95 | #define CONFIG_CMD_SDRAM |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 96 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 97 | #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ |
| 98 | |
| 99 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
| 101 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. |
| 102 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 103 | * The Linux BASE_BAUD define should match this configuration. |
| 104 | * baseBaud = cpuClock/(uartDivisor*16) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 106 | * set Linux BASE_BAUD to 403200. |
| 107 | */ |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 108 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
| 110 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
| 111 | #define CONFIG_SYS_BASE_BAUD 691200 |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 112 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 113 | /*----------------------------------------------------------------------- |
| 114 | * I2C stuff |
| 115 | *----------------------------------------------------------------------- |
| 116 | */ |
Dirk Eibach | 42b204f | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 117 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 118 | |
Dirk Eibach | 42b204f | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 119 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 120 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ |
stroese | 5ad6d4d | 2003-12-09 14:54:43 +0000 | [diff] [blame] | 121 | |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 122 | #if defined(CONFIG_CMD_EEPROM) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 123 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ |
| 124 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
stroese | 5ad6d4d | 2003-12-09 14:54:43 +0000 | [diff] [blame] | 125 | #endif |
| 126 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 127 | /*----------------------------------------------------------------------- |
| 128 | * PCI stuff |
| 129 | *----------------------------------------------------------------------- |
| 130 | */ |
| 131 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
| 132 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| 133 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
| 134 | |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 135 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 136 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 137 | /* resource configuration */ |
stroese | 5ad6d4d | 2003-12-09 14:54:43 +0000 | [diff] [blame] | 138 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 139 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 141 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
| 142 | #define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ |
| 143 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ |
| 144 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
| 145 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 146 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ |
| 147 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ |
| 148 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 149 | |
| 150 | /*----------------------------------------------------------------------- |
| 151 | * External peripheral base address |
| 152 | *----------------------------------------------------------------------- |
| 153 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 |
| 155 | #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 |
| 156 | #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 157 | |
| 158 | /*----------------------------------------------------------------------- |
| 159 | * Start addresses for the final memory configuration |
| 160 | * (Set up by the startup code) |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 161 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 162 | #define CONFIG_SYS_SRAM_BASE 0xFFF00000 |
Wolfgang Denk | 2fc54d9 | 2010-09-10 23:04:05 +0200 | [diff] [blame] | 163 | #define CONFIG_SYS_SRAM_SIZE (256 << 10) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 164 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 165 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 166 | /*----------------------------------------------------------------------- |
| 167 | * FLASH organization |
| 168 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 170 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 171 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 173 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 174 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 |
| 176 | #define CONFIG_SYS_FLASH_ADDR1 0x2aaa |
| 177 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 178 | |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 179 | #ifdef CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 180 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 181 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 182 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 183 | |
| 184 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 185 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 186 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 187 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 188 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 189 | /*----------------------------------------------------------------------- |
| 190 | * NVRAM organization |
| 191 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
| 193 | #define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 194 | |
Jean-Christophe PLAGNIOL-VILLARD | fdb79c3 | 2008-09-10 22:47:59 +0200 | [diff] [blame] | 195 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 196 | #define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ |
| 197 | #define CONFIG_ENV_ADDR \ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 198 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 199 | #endif |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 200 | |
| 201 | /* |
| 202 | * Init Memory Controller: |
| 203 | * |
| 204 | * BR0/1 and OR0/1 (FLASH) |
| 205 | */ |
| 206 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 207 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 208 | #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
| 209 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 210 | /*----------------------------------------------------------------------- |
| 211 | * Definitions for initial stack pointer and data area (in data cache) |
| 212 | */ |
| 213 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 215 | |
| 216 | /* On Chip Memory location */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 217 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
| 218 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
| 219 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 220 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 221 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 222 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 224 | |
| 225 | /*----------------------------------------------------------------------- |
| 226 | * External Bus Controller (EBC) Setup |
| 227 | */ |
| 228 | |
| 229 | /* Memory Bank 0 (Flash/SRAM) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 230 | #define CONFIG_SYS_EBC_PB0AP 0x04006000 |
| 231 | #define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 232 | |
| 233 | /* Memory Bank 1 (NVRAM/RTC) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 234 | #define CONFIG_SYS_EBC_PB1AP 0x04041000 |
| 235 | #define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 236 | |
| 237 | /* Memory Bank 2 (not used) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 238 | #define CONFIG_SYS_EBC_PB2AP 0x00000000 |
| 239 | #define CONFIG_SYS_EBC_PB2CR 0x00000000 |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 240 | |
| 241 | /* Memory Bank 2 (not used) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 242 | #define CONFIG_SYS_EBC_PB3AP 0x00000000 |
| 243 | #define CONFIG_SYS_EBC_PB3CR 0x00000000 |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 244 | |
| 245 | /* Memory Bank 4 (FPGA regs) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 246 | #define CONFIG_SYS_EBC_PB4AP 0x01815000 |
| 247 | #define CONFIG_SYS_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 248 | |
| 249 | /*----------------------------------------------------------------------- |
| 250 | * Definitions for Serial Presence Detect EEPROM address |
| 251 | * (to get SDRAM settings) |
| 252 | */ |
| 253 | #define SPD_EEPROM_ADDRESS 0x55 |
| 254 | |
| 255 | /*----------------------------------------------------------------------- |
| 256 | * Definitions for GPIO setup (PPC405EP specific) |
| 257 | * |
| 258 | * GPIO0[0] - External Bus Controller BLAST output |
| 259 | * GPIO0[1-9] - Instruction trace outputs |
| 260 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
| 261 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs |
| 262 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
| 263 | * GPIO0[24-27] - UART0 control signal inputs/outputs |
| 264 | * GPIO0[28-29] - UART1 data signal input/output |
| 265 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs |
| 266 | */ |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 267 | #define CONFIG_SYS_GPIO0_OSRL 0x55555555 |
| 268 | #define CONFIG_SYS_GPIO0_OSRH 0x40000110 |
| 269 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 |
| 270 | #define CONFIG_SYS_GPIO0_ISR1H 0x15555445 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 271 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 272 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 273 | #define CONFIG_SYS_GPIO0_TCR 0xFFFF8014 |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 274 | |
| 275 | /*----------------------------------------------------------------------- |
| 276 | * Some BUBINGA stuff... |
| 277 | */ |
| 278 | #define NVRAM_BASE 0xF0000000 |
| 279 | #define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */ |
| 280 | #define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */ |
| 281 | #define NVRVFY1 0x4f532d4f /* used to determine if state data in */ |
| 282 | #define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/ |
| 283 | |
| 284 | #define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */ |
| 285 | #define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */ |
| 286 | #define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */ |
| 287 | #define FPGA_REG0_LED0 0x04 /* Turn on LED0 */ |
| 288 | #define FPGA_REG0_LED1 0x02 /* Turn on LED1 */ |
| 289 | #define FPGA_REG0_LED2 0x01 /* Turn on LED2 */ |
| 290 | |
| 291 | #define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */ |
| 292 | #define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */ |
| 293 | #define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */ |
| 294 | #define FPGA_REG1_CLOCK_BIT_SHIFT 4 |
| 295 | #define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */ |
| 296 | #define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */ |
| 297 | #define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */ |
| 298 | #define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */ |
| 299 | |
stroese | 9c9acf1 | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 300 | #endif /* __CONFIG_H */ |