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git01.mediatek.com / filogic / uboot / 9dfac0ad892a266bd45e04671d38dbe98ec0c5e3 / . / arch / arm / include / asm / arch-omap4 / clocks.h
blob: cd304e86842e9e6f3f5ecc131f05d934d5a1e5df [file] [log] [blame]
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]1/*
2 * (C) Copyright 2010
3 * Texas Instruments, <www.ti.com>
4 *
5 * Aneesh V <aneesh@ti.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25#ifndef _CLOCKS_OMAP4_H_
26#define _CLOCKS_OMAP4_H_
27#include <common.h>
28
29/*
30 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
31 * loop, allow for a minimum of 2 ms wait (in reality the wait will be
32 * much more than that)
33 */
34#define LDELAY 1000000
35
Aneesh Vcc565582011-07-21 09:10:09 -0400[diff] [blame]36#define CM_CLKMODE_DPLL_CORE 0x4A004120
37#define CM_CLKMODE_DPLL_PER 0x4A008140
38#define CM_CLKMODE_DPLL_MPU 0x4A004160
39#define CM_CLKSEL_CORE 0x4A004100
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]40
41struct omap4_prcm_regs {
42 /* cm1.ckgen */
43 u32 cm_clksel_core;
44 u32 pad001[1];
45 u32 cm_clksel_abe;
46 u32 pad002[1];
47 u32 cm_dll_ctrl;
48 u32 pad003[3];
49 u32 cm_clkmode_dpll_core;
50 u32 cm_idlest_dpll_core;
51 u32 cm_autoidle_dpll_core;
52 u32 cm_clksel_dpll_core;
53 u32 cm_div_m2_dpll_core;
54 u32 cm_div_m3_dpll_core;
55 u32 cm_div_m4_dpll_core;
56 u32 cm_div_m5_dpll_core;
57 u32 cm_div_m6_dpll_core;
58 u32 cm_div_m7_dpll_core;
59 u32 cm_ssc_deltamstep_dpll_core;
60 u32 cm_ssc_modfreqdiv_dpll_core;
61 u32 cm_emu_override_dpll_core;
62 u32 pad004[3];
63 u32 cm_clkmode_dpll_mpu;
64 u32 cm_idlest_dpll_mpu;
65 u32 cm_autoidle_dpll_mpu;
66 u32 cm_clksel_dpll_mpu;
67 u32 cm_div_m2_dpll_mpu;
68 u32 pad005[5];
69 u32 cm_ssc_deltamstep_dpll_mpu;
70 u32 cm_ssc_modfreqdiv_dpll_mpu;
71 u32 pad006[3];
72 u32 cm_bypclk_dpll_mpu;
73 u32 cm_clkmode_dpll_iva;
74 u32 cm_idlest_dpll_iva;
75 u32 cm_autoidle_dpll_iva;
76 u32 cm_clksel_dpll_iva;
77 u32 pad007[2];
78 u32 cm_div_m4_dpll_iva;
79 u32 cm_div_m5_dpll_iva;
80 u32 pad008[2];
81 u32 cm_ssc_deltamstep_dpll_iva;
82 u32 cm_ssc_modfreqdiv_dpll_iva;
83 u32 pad009[3];
84 u32 cm_bypclk_dpll_iva;
85 u32 cm_clkmode_dpll_abe;
86 u32 cm_idlest_dpll_abe;
87 u32 cm_autoidle_dpll_abe;
88 u32 cm_clksel_dpll_abe;
89 u32 cm_div_m2_dpll_abe;
90 u32 cm_div_m3_dpll_abe;
91 u32 pad010[4];
92 u32 cm_ssc_deltamstep_dpll_abe;
93 u32 cm_ssc_modfreqdiv_dpll_abe;
94 u32 pad011[4];
95 u32 cm_clkmode_dpll_ddrphy;
96 u32 cm_idlest_dpll_ddrphy;
97 u32 cm_autoidle_dpll_ddrphy;
98 u32 cm_clksel_dpll_ddrphy;
99 u32 cm_div_m2_dpll_ddrphy;
100 u32 pad012[1];
101 u32 cm_div_m4_dpll_ddrphy;
102 u32 cm_div_m5_dpll_ddrphy;
103 u32 cm_div_m6_dpll_ddrphy;
104 u32 pad013[1];
105 u32 cm_ssc_deltamstep_dpll_ddrphy;
106 u32 pad014[5];
107 u32 cm_shadow_freq_config1;
Aneesh Va47a79f2011-07-21 09:29:36 -0400[diff] [blame]108 u32 pad0141[47];
109 u32 cm_mpu_mpu_clkctrl;
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]110
111 /* cm1.dsp */
Aneesh Va47a79f2011-07-21 09:29:36 -0400[diff] [blame]112 u32 pad015[55];
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]113 u32 cm_dsp_clkstctrl;
114 u32 pad016[7];
115 u32 cm_dsp_dsp_clkctrl;
116
117 /* cm1.abe */
118 u32 pad017[55];
119 u32 cm1_abe_clkstctrl;
120 u32 pad018[7];
121 u32 cm1_abe_l4abe_clkctrl;
122 u32 pad019[1];
123 u32 cm1_abe_aess_clkctrl;
124 u32 pad020[1];
125 u32 cm1_abe_pdm_clkctrl;
126 u32 pad021[1];
127 u32 cm1_abe_dmic_clkctrl;
128 u32 pad022[1];
129 u32 cm1_abe_mcasp_clkctrl;
130 u32 pad023[1];
131 u32 cm1_abe_mcbsp1_clkctrl;
132 u32 pad024[1];
133 u32 cm1_abe_mcbsp2_clkctrl;
134 u32 pad025[1];
135 u32 cm1_abe_mcbsp3_clkctrl;
136 u32 pad026[1];
137 u32 cm1_abe_slimbus_clkctrl;
138 u32 pad027[1];
139 u32 cm1_abe_timer5_clkctrl;
140 u32 pad028[1];
141 u32 cm1_abe_timer6_clkctrl;
142 u32 pad029[1];
143 u32 cm1_abe_timer7_clkctrl;
144 u32 pad030[1];
145 u32 cm1_abe_timer8_clkctrl;
146 u32 pad031[1];
147 u32 cm1_abe_wdt3_clkctrl;
148
149 /* cm2.ckgen */
150 u32 pad032[3805];
151 u32 cm_clksel_mpu_m3_iss_root;
152 u32 cm_clksel_usb_60mhz;
153 u32 cm_scale_fclk;
154 u32 pad033[1];
155 u32 cm_core_dvfs_perf1;
156 u32 cm_core_dvfs_perf2;
157 u32 cm_core_dvfs_perf3;
158 u32 cm_core_dvfs_perf4;
159 u32 pad034[1];
160 u32 cm_core_dvfs_current;
161 u32 cm_iva_dvfs_perf_tesla;
162 u32 cm_iva_dvfs_perf_ivahd;
163 u32 cm_iva_dvfs_perf_abe;
164 u32 pad035[1];
165 u32 cm_iva_dvfs_current;
166 u32 pad036[1];
167 u32 cm_clkmode_dpll_per;
168 u32 cm_idlest_dpll_per;
169 u32 cm_autoidle_dpll_per;
170 u32 cm_clksel_dpll_per;
171 u32 cm_div_m2_dpll_per;
172 u32 cm_div_m3_dpll_per;
173 u32 cm_div_m4_dpll_per;
174 u32 cm_div_m5_dpll_per;
175 u32 cm_div_m6_dpll_per;
176 u32 cm_div_m7_dpll_per;
177 u32 cm_ssc_deltamstep_dpll_per;
178 u32 cm_ssc_modfreqdiv_dpll_per;
179 u32 cm_emu_override_dpll_per;
180 u32 pad037[3];
181 u32 cm_clkmode_dpll_usb;
182 u32 cm_idlest_dpll_usb;
183 u32 cm_autoidle_dpll_usb;
184 u32 cm_clksel_dpll_usb;
185 u32 cm_div_m2_dpll_usb;
186 u32 pad038[5];
187 u32 cm_ssc_deltamstep_dpll_usb;
188 u32 cm_ssc_modfreqdiv_dpll_usb;
189 u32 pad039[1];
190 u32 cm_clkdcoldo_dpll_usb;
191 u32 pad040[2];
192 u32 cm_clkmode_dpll_unipro;
193 u32 cm_idlest_dpll_unipro;
194 u32 cm_autoidle_dpll_unipro;
195 u32 cm_clksel_dpll_unipro;
196 u32 cm_div_m2_dpll_unipro;
197 u32 pad041[5];
198 u32 cm_ssc_deltamstep_dpll_unipro;
199 u32 cm_ssc_modfreqdiv_dpll_unipro;
200
201 /* cm2.core */
202 u32 pad0411[324];
203 u32 cm_l3_1_clkstctrl;
204 u32 pad042[1];
205 u32 cm_l3_1_dynamicdep;
206 u32 pad043[5];
207 u32 cm_l3_1_l3_1_clkctrl;
208 u32 pad044[55];
209 u32 cm_l3_2_clkstctrl;
210 u32 pad045[1];
211 u32 cm_l3_2_dynamicdep;
212 u32 pad046[5];
213 u32 cm_l3_2_l3_2_clkctrl;
214 u32 pad047[1];
215 u32 cm_l3_2_gpmc_clkctrl;
216 u32 pad048[1];
217 u32 cm_l3_2_ocmc_ram_clkctrl;
218 u32 pad049[51];
219 u32 cm_mpu_m3_clkstctrl;
220 u32 cm_mpu_m3_staticdep;
221 u32 cm_mpu_m3_dynamicdep;
222 u32 pad050[5];
223 u32 cm_mpu_m3_mpu_m3_clkctrl;
224 u32 pad051[55];
225 u32 cm_sdma_clkstctrl;
226 u32 cm_sdma_staticdep;
227 u32 cm_sdma_dynamicdep;
228 u32 pad052[5];
229 u32 cm_sdma_sdma_clkctrl;
230 u32 pad053[55];
231 u32 cm_memif_clkstctrl;
232 u32 pad054[7];
233 u32 cm_memif_dmm_clkctrl;
234 u32 pad055[1];
235 u32 cm_memif_emif_fw_clkctrl;
236 u32 pad056[1];
237 u32 cm_memif_emif_1_clkctrl;
238 u32 pad057[1];
239 u32 cm_memif_emif_2_clkctrl;
240 u32 pad058[1];
241 u32 cm_memif_dll_clkctrl;
242 u32 pad059[3];
243 u32 cm_memif_emif_h1_clkctrl;
244 u32 pad060[1];
245 u32 cm_memif_emif_h2_clkctrl;
246 u32 pad061[1];
247 u32 cm_memif_dll_h_clkctrl;
248 u32 pad062[39];
249 u32 cm_c2c_clkstctrl;
250 u32 cm_c2c_staticdep;
251 u32 cm_c2c_dynamicdep;
252 u32 pad063[5];
253 u32 cm_c2c_sad2d_clkctrl;
254 u32 pad064[1];
255 u32 cm_c2c_modem_icr_clkctrl;
256 u32 pad065[1];
257 u32 cm_c2c_sad2d_fw_clkctrl;
258 u32 pad066[51];
259 u32 cm_l4cfg_clkstctrl;
260 u32 pad067[1];
261 u32 cm_l4cfg_dynamicdep;
262 u32 pad068[5];
263 u32 cm_l4cfg_l4_cfg_clkctrl;
264 u32 pad069[1];
265 u32 cm_l4cfg_hw_sem_clkctrl;
266 u32 pad070[1];
267 u32 cm_l4cfg_mailbox_clkctrl;
268 u32 pad071[1];
269 u32 cm_l4cfg_sar_rom_clkctrl;
270 u32 pad072[49];
271 u32 cm_l3instr_clkstctrl;
272 u32 pad073[7];
273 u32 cm_l3instr_l3_3_clkctrl;
274 u32 pad074[1];
275 u32 cm_l3instr_l3_instr_clkctrl;
276 u32 pad075[5];
277 u32 cm_l3instr_intrconn_wp1_clkctrl;
278
279
280 /* cm2.ivahd */
281 u32 pad076[47];
282 u32 cm_ivahd_clkstctrl;
283 u32 pad077[7];
284 u32 cm_ivahd_ivahd_clkctrl;
285 u32 pad078[1];
286 u32 cm_ivahd_sl2_clkctrl;
287
288 /* cm2.cam */
289 u32 pad079[53];
290 u32 cm_cam_clkstctrl;
291 u32 pad080[7];
292 u32 cm_cam_iss_clkctrl;
293 u32 pad081[1];
294 u32 cm_cam_fdif_clkctrl;
295
296 /* cm2.dss */
297 u32 pad082[53];
298 u32 cm_dss_clkstctrl;
299 u32 pad083[7];
300 u32 cm_dss_dss_clkctrl;
301
302 /* cm2.sgx */
303 u32 pad084[55];
304 u32 cm_sgx_clkstctrl;
305 u32 pad085[7];
306 u32 cm_sgx_sgx_clkctrl;
307
308 /* cm2.l3init */
309 u32 pad086[55];
310 u32 cm_l3init_clkstctrl;
311
312 /* cm2.l3init */
313 u32 pad087[9];
314 u32 cm_l3init_hsmmc1_clkctrl;
315 u32 pad088[1];
316 u32 cm_l3init_hsmmc2_clkctrl;
317 u32 pad089[1];
318 u32 cm_l3init_hsi_clkctrl;
319 u32 pad090[7];
320 u32 cm_l3init_hsusbhost_clkctrl;
321 u32 pad091[1];
322 u32 cm_l3init_hsusbotg_clkctrl;
323 u32 pad092[1];
324 u32 cm_l3init_hsusbtll_clkctrl;
325 u32 pad093[3];
326 u32 cm_l3init_p1500_clkctrl;
327 u32 pad094[21];
328 u32 cm_l3init_fsusb_clkctrl;
329 u32 pad095[3];
330 u32 cm_l3init_usbphy_clkctrl;
331
332 /* cm2.l4per */
333 u32 pad096[7];
334 u32 cm_l4per_clkstctrl;
335 u32 pad097[1];
336 u32 cm_l4per_dynamicdep;
337 u32 pad098[5];
338 u32 cm_l4per_adc_clkctrl;
339 u32 pad100[1];
340 u32 cm_l4per_gptimer10_clkctrl;
341 u32 pad101[1];
342 u32 cm_l4per_gptimer11_clkctrl;
343 u32 pad102[1];
344 u32 cm_l4per_gptimer2_clkctrl;
345 u32 pad103[1];
346 u32 cm_l4per_gptimer3_clkctrl;
347 u32 pad104[1];
348 u32 cm_l4per_gptimer4_clkctrl;
349 u32 pad105[1];
350 u32 cm_l4per_gptimer9_clkctrl;
351 u32 pad106[1];
352 u32 cm_l4per_elm_clkctrl;
353 u32 pad107[1];
354 u32 cm_l4per_gpio2_clkctrl;
355 u32 pad108[1];
356 u32 cm_l4per_gpio3_clkctrl;
357 u32 pad109[1];
358 u32 cm_l4per_gpio4_clkctrl;
359 u32 pad110[1];
360 u32 cm_l4per_gpio5_clkctrl;
361 u32 pad111[1];
362 u32 cm_l4per_gpio6_clkctrl;
363 u32 pad112[1];
364 u32 cm_l4per_hdq1w_clkctrl;
365 u32 pad113[1];
366 u32 cm_l4per_hecc1_clkctrl;
367 u32 pad114[1];
368 u32 cm_l4per_hecc2_clkctrl;
369 u32 pad115[1];
370 u32 cm_l4per_i2c1_clkctrl;
371 u32 pad116[1];
372 u32 cm_l4per_i2c2_clkctrl;
373 u32 pad117[1];
374 u32 cm_l4per_i2c3_clkctrl;
375 u32 pad118[1];
376 u32 cm_l4per_i2c4_clkctrl;
377 u32 pad119[1];
378 u32 cm_l4per_l4per_clkctrl;
379 u32 pad1191[3];
380 u32 cm_l4per_mcasp2_clkctrl;
381 u32 pad120[1];
382 u32 cm_l4per_mcasp3_clkctrl;
383 u32 pad121[1];
384 u32 cm_l4per_mcbsp4_clkctrl;
385 u32 pad122[1];
386 u32 cm_l4per_mgate_clkctrl;
387 u32 pad123[1];
388 u32 cm_l4per_mcspi1_clkctrl;
389 u32 pad124[1];
390 u32 cm_l4per_mcspi2_clkctrl;
391 u32 pad125[1];
392 u32 cm_l4per_mcspi3_clkctrl;
393 u32 pad126[1];
394 u32 cm_l4per_mcspi4_clkctrl;
395 u32 pad127[5];
396 u32 cm_l4per_mmcsd3_clkctrl;
397 u32 pad128[1];
398 u32 cm_l4per_mmcsd4_clkctrl;
399 u32 pad129[1];
400 u32 cm_l4per_msprohg_clkctrl;
401 u32 pad130[1];
402 u32 cm_l4per_slimbus2_clkctrl;
403 u32 pad131[1];
404 u32 cm_l4per_uart1_clkctrl;
405 u32 pad132[1];
406 u32 cm_l4per_uart2_clkctrl;
407 u32 pad133[1];
408 u32 cm_l4per_uart3_clkctrl;
409 u32 pad134[1];
410 u32 cm_l4per_uart4_clkctrl;
411 u32 pad135[1];
412 u32 cm_l4per_mmcsd5_clkctrl;
413 u32 pad136[1];
414 u32 cm_l4per_i2c5_clkctrl;
415 u32 pad137[5];
416 u32 cm_l4sec_clkstctrl;
417 u32 cm_l4sec_staticdep;
418 u32 cm_l4sec_dynamicdep;
419 u32 pad138[5];
420 u32 cm_l4sec_aes1_clkctrl;
421 u32 pad139[1];
422 u32 cm_l4sec_aes2_clkctrl;
423 u32 pad140[1];
424 u32 cm_l4sec_des3des_clkctrl;
425 u32 pad141[1];
426 u32 cm_l4sec_pkaeip29_clkctrl;
427 u32 pad142[1];
428 u32 cm_l4sec_rng_clkctrl;
429 u32 pad143[1];
430 u32 cm_l4sec_sha2md51_clkctrl;
431 u32 pad144[3];
432 u32 cm_l4sec_cryptodma_clkctrl;
433 u32 pad145[776841];
434
435 /* l4 wkup regs */
436 u32 pad201[6211];
437 u32 cm_abe_pll_ref_clksel;
438 u32 cm_sys_clksel;
439 u32 pad202[1467];
440 u32 cm_wkup_clkstctrl;
441 u32 pad203[7];
442 u32 cm_wkup_l4wkup_clkctrl;
443 u32 pad204;
444 u32 cm_wkup_wdtimer1_clkctrl;
445 u32 pad205;
446 u32 cm_wkup_wdtimer2_clkctrl;
447 u32 pad206;
448 u32 cm_wkup_gpio1_clkctrl;
449 u32 pad207;
450 u32 cm_wkup_gptimer1_clkctrl;
451 u32 pad208;
452 u32 cm_wkup_gptimer12_clkctrl;
453 u32 pad209;
454 u32 cm_wkup_synctimer_clkctrl;
455 u32 pad210;
456 u32 cm_wkup_usim_clkctrl;
457 u32 pad211;
458 u32 cm_wkup_sarram_clkctrl;
459 u32 pad212[5];
460 u32 cm_wkup_keyboard_clkctrl;
461 u32 pad213;
462 u32 cm_wkup_rtc_clkctrl;
463 u32 pad214;
464 u32 cm_wkup_bandgap_clkctrl;
465 u32 pad215[197];
466 u32 prm_vc_val_bypass;
467 u32 prm_vc_cfg_channel;
468 u32 prm_vc_cfg_i2c_mode;
469 u32 prm_vc_cfg_i2c_clk;
470
471};
472
Chris Lalancette5008c132011-12-13 09:41:12 +0000[diff] [blame]473struct omap4_scrm_regs {
474 u32 revision; /* 0x0000 */
475 u32 pad00[63];
476 u32 clksetuptime; /* 0x0100 */
477 u32 pmicsetuptime; /* 0x0104 */
478 u32 pad01[2];
479 u32 altclksrc; /* 0x0110 */
480 u32 pad02[2];
481 u32 c2cclkm; /* 0x011c */
482 u32 pad03[56];
483 u32 extclkreq; /* 0x0200 */
484 u32 accclkreq; /* 0x0204 */
485 u32 pwrreq; /* 0x0208 */
486 u32 pad04[1];
487 u32 auxclkreq0; /* 0x0210 */
488 u32 auxclkreq1; /* 0x0214 */
489 u32 auxclkreq2; /* 0x0218 */
490 u32 auxclkreq3; /* 0x021c */
491 u32 auxclkreq4; /* 0x0220 */
492 u32 auxclkreq5; /* 0x0224 */
493 u32 pad05[3];
494 u32 c2cclkreq; /* 0x0234 */
495 u32 pad06[54];
496 u32 auxclk0; /* 0x0310 */
497 u32 auxclk1; /* 0x0314 */
498 u32 auxclk2; /* 0x0318 */
499 u32 auxclk3; /* 0x031c */
500 u32 auxclk4; /* 0x0320 */
501 u32 auxclk5; /* 0x0324 */
502 u32 pad07[54];
503 u32 rsttime_reg; /* 0x0400 */
504 u32 pad08[6];
505 u32 c2crstctrl; /* 0x041c */
506 u32 extpwronrstctrl; /* 0x0420 */
507 u32 pad09[59];
508 u32 extwarmrstst_reg; /* 0x0510 */
509 u32 apewarmrstst_reg; /* 0x0514 */
510 u32 pad10[1];
511 u32 c2cwarmrstst_reg; /* 0x051C */
512};
513
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]514/* DPLL register offsets */
515#define CM_CLKMODE_DPLL 0
516#define CM_IDLEST_DPLL 0x4
517#define CM_AUTOIDLE_DPLL 0x8
518#define CM_CLKSEL_DPLL 0xC
519#define CM_DIV_M2_DPLL 0x10
520#define CM_DIV_M3_DPLL 0x14
521#define CM_DIV_M4_DPLL 0x18
522#define CM_DIV_M5_DPLL 0x1C
523#define CM_DIV_M6_DPLL 0x20
524#define CM_DIV_M7_DPLL 0x24
525
526#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
527
528/* CM_CLKMODE_DPLL */
529#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
530#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
531#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
532#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
533#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
534#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
535#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
536#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
537#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
538#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
539#define CM_CLKMODE_DPLL_EN_SHIFT 0
540#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
541
542#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
543#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
544
545#define DPLL_EN_STOP 1
546#define DPLL_EN_MN_BYPASS 4
547#define DPLL_EN_LOW_POWER_BYPASS 5
548#define DPLL_EN_FAST_RELOCK_BYPASS 6
549#define DPLL_EN_LOCK 7
550
551/* CM_IDLEST_DPLL fields */
552#define ST_DPLL_CLK_MASK 1
553
554/* CM_CLKSEL_DPLL */
555#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
556#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
557#define CM_CLKSEL_DPLL_M_SHIFT 8
558#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
559#define CM_CLKSEL_DPLL_N_SHIFT 0
560#define CM_CLKSEL_DPLL_N_MASK 0x7F
Aneesh Va47a79f2011-07-21 09:29:36 -0400[diff] [blame]561#define CM_CLKSEL_DCC_EN_SHIFT 22
562#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]563
564#define OMAP4_DPLL_MAX_N 127
565
566/* CM_SYS_CLKSEL */
567#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
568
569/* CM_CLKSEL_CORE */
570#define CLKSEL_CORE_SHIFT 0
571#define CLKSEL_L3_SHIFT 4
572#define CLKSEL_L4_SHIFT 8
573
574#define CLKSEL_CORE_X2_DIV_1 0
575#define CLKSEL_L3_CORE_DIV_2 1
576#define CLKSEL_L4_L3_DIV_2 1
577
578/* CM_ABE_PLL_REF_CLKSEL */
579#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
580#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
581#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
582#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
583
584/* CM_BYPCLK_DPLL_IVA */
585#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
586#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
587
588#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
589
590/* CM_SHADOW_FREQ_CONFIG1 */
591#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
592#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
593#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
594
595#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
596#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
597
598#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
599#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
600
601/*CM_<clock_domain>__CLKCTRL */
602#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
603#define CD_CLKCTRL_CLKTRCTRL_MASK 3
604
605#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
606#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
607#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
608#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
609
610
611/* CM_<clock_domain>_<module>_CLKCTRL */
612#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
613#define MODULE_CLKCTRL_MODULEMODE_MASK 3
614#define MODULE_CLKCTRL_IDLEST_SHIFT 16
615#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
616
617#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
618#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
619#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
620
621#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
622#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
623#define MODULE_CLKCTRL_IDLEST_IDLE 2
624#define MODULE_CLKCTRL_IDLEST_DISABLED 3
625
626/* CM_L4PER_GPIO4_CLKCTRL */
627#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
628
629/* CM_L3INIT_HSMMCn_CLKCTRL */
630#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
631
632/* CM_WKUP_GPTIMER1_CLKCTRL */
633#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
634
635/* CM_CAM_ISS_CLKCTRL */
636#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
637
638/* CM_DSS_DSS_CLKCTRL */
639#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
640
641/* CM_L3INIT_USBPHY_CLKCTRL */
642#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
643
Aneesh Va47a79f2011-07-21 09:29:36 -0400[diff] [blame]644/* CM_MPU_MPU_CLKCTRL */
645#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
646#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
647#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
648#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
649
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]650/* Clock frequencies */
651#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
652#define OMAP_SYS_CLK_IND_38_4_MHZ 6
653#define OMAP_32K_CLK_FREQ 32768
654
655/* PRM_VC_CFG_I2C_CLK */
656#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
657#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
658#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
659#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
660
661/* PRM_VC_VAL_BYPASS */
662#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
663
664#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000
665#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
666#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
667#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
668#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
669#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
670#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
671
Aneesh V0fa1d1b2011-07-21 09:29:32 -0400[diff] [blame]672/* SMPS */
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]673#define SMPS_I2C_SLAVE_ADDR 0x12
674#define SMPS_REG_ADDR_VCORE1 0x55
675#define SMPS_REG_ADDR_VCORE2 0x5B
676#define SMPS_REG_ADDR_VCORE3 0x61
677
678#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
679#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
680
Aneesh V0fa1d1b2011-07-21 09:29:32 -0400[diff] [blame]681/* TPS */
682#define TPS62361_I2C_SLAVE_ADDR 0x60
683#define TPS62361_REG_ADDR_SET0 0x0
684#define TPS62361_REG_ADDR_SET1 0x1
685#define TPS62361_REG_ADDR_SET2 0x2
686#define TPS62361_REG_ADDR_SET3 0x3
687#define TPS62361_REG_ADDR_CTRL 0x4
688#define TPS62361_REG_ADDR_TEMP 0x5
689#define TPS62361_REG_ADDR_RMP_CTRL 0x6
690#define TPS62361_REG_ADDR_CHIP_ID 0x8
691#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
692
693#define TPS62361_BASE_VOLT_MV 500
694#define TPS62361_VSEL0_GPIO 7
695
Chris Lalancette5008c132011-12-13 09:41:12 +0000[diff] [blame]696/* AUXCLKx reg fields */
697#define AUXCLK_ENABLE_MASK (1 << 8)
698#define AUXCLK_SRCSELECT_SHIFT 1
699#define AUXCLK_SRCSELECT_MASK (3 << 1)
700#define AUXCLK_CLKDIV_SHIFT 16
701#define AUXCLK_CLKDIV_MASK (0xF << 16)
702
703#define AUXCLK_SRCSELECT_SYS_CLK 0
704#define AUXCLK_SRCSELECT_CORE_DPLL 1
705#define AUXCLK_SRCSELECT_PER_DPLL 2
706#define AUXCLK_SRCSELECT_ALTERNATE 3
707
708#define AUXCLK_CLKDIV_2 1
709#define AUXCLK_CLKDIV_16 0xF
710
711/* ALTCLKSRC */
712#define ALTCLKSRC_MODE_MASK 3
713#define ALTCLKSRC_ENABLE_INT_MASK 4
714#define ALTCLKSRC_ENABLE_EXT_MASK 8
715
716#define ALTCLKSRC_MODE_ACTIVE 1
717
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]718/* Defines for DPLL setup */
719#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
720#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
721#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
722
723#define DPLL_NO_LOCK 0
724#define DPLL_LOCK 1
725
726#define NUM_SYS_CLKS 7
727
728struct dpll_regs {
729 u32 cm_clkmode_dpll;
730 u32 cm_idlest_dpll;
731 u32 cm_autoidle_dpll;
732 u32 cm_clksel_dpll;
733 u32 cm_div_m2_dpll;
734 u32 cm_div_m3_dpll;
735 u32 cm_div_m4_dpll;
736 u32 cm_div_m5_dpll;
737 u32 cm_div_m6_dpll;
738 u32 cm_div_m7_dpll;
739};
740
741/* DPLL parameter table */
742struct dpll_params {
743 u32 m;
744 u32 n;
Aneesh Vd97f8b02011-08-20 21:40:26 +0000[diff] [blame]745 s8 m2;
746 s8 m3;
747 s8 m4;
748 s8 m5;
749 s8 m6;
750 s8 m7;
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]751};
752
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]753extern struct omap4_prcm_regs *const prcm;
754extern const u32 sys_clk_array[8];
755
756void scale_vcores(void);
757void do_scale_tps62361(u32 reg, u32 volt_mv);
758u32 omap_ddr_clk(void);
759void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
760void setup_sri2c(void);
761void setup_post_dividers(u32 *const base, const struct dpll_params *params);
762u32 get_sys_clk_index(void);
763void enable_basic_clocks(void);
Sricharan308fe922011-11-15 09:50:03 -0500[diff] [blame]764void enable_basic_uboot_clocks(void);
Sricharan9784f1f2011-11-15 09:49:58 -0500[diff] [blame]765void enable_non_essential_clocks(void);
766void do_enable_clocks(u32 *const *clk_domains,
767 u32 *const *clk_modules_hw_auto,
768 u32 *const *clk_modules_explicit_en,
769 u8 wait_for_enable);
770const struct dpll_params *get_mpu_dpll_params(void);
771const struct dpll_params *get_core_dpll_params(void);
772const struct dpll_params *get_per_dpll_params(void);
773const struct dpll_params *get_iva_dpll_params(void);
774const struct dpll_params *get_usb_dpll_params(void);
775const struct dpll_params *get_abe_dpll_params(void);
Aneesh V0d2628b2011-07-21 09:10:07 -0400[diff] [blame]776#endif /* _CLOCKS_OMAP4_H_ */